JPH01218283A - High efficient coding device for television signal - Google Patents

Abstract

PURPOSE:To simplify the constitution and to quicken the processing speed by replacing the multiplication in the coding operation into a multiplication using a conversion table. CONSTITUTION:A data representing a dynamic range DR and a data representing an assigned bit number BITS are fed to a conversion circuit 26. Moreover, the selection signal representing the coding method is supplied to the conversion circuit 26. A conversion table is provided to the conversion circuit 26. The output of the conversion circuit 26 is given to a multiplier circuit 27 via a register 30, where it is multiplied with an output from a subtraction circuit 25. The output of the multiplier circuit 27 is outputted via a register 31 and a rounding circuit 28 and a register 32. The rounding processing in the rounding circuit 28 is switched by the selection signal of the coding method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device for television signals, and particularly to the technology of the encoding section thereof.

[Summary of the invention]

This invention blocks digital television signals,
In a device that detects the dynamic range of each block and performs high-efficiency encoding of a television signal by utilizing the fact that the dynamic range of each block is smaller than the dynamic range of the entire screen, division in the encoding operation is By generating the reciprocal of the divisor in advance and replacing it with multiplication, the structure is simple, the processing speed is high, and it is suitable for IC implementation.

[Conventional technology]

The present inventors have developed an adaptive dynamic range coding method (hereinafter referred to as ADR) as a high-efficiency coding method for television signals.
(December 11, 1986)
Address to the Institute of Electronics and Communication Engineers, Japan (MR86-43).

This ^i) MC method is an encoding method that utilizes the strong spatio-temporal correlation of television signals.

In other words, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation.Therefore, in the 1) MC method, the image is divided into blocks, the dynamic range of each block is determined, and the adaptive By re-encoding the pixel data, each pixel data can be compressed to a smaller number of bits than the original number of bits.

Image block division methods include division only in the horizontal line direction (one-dimensional ADRC), division into rectangular areas in both horizontal and vertical directions (two-dimensional ADRC), and division considering spatial areas spanning multiple frames (three-dimensional ADRC). To〇R
C) has been proposed (for example, JP-A-61-1449
90, JP-A-61-144989, and JP-A-62-92620).

In three-dimensional ADRC, motion detection between two frames is performed for each block, and even more efficient encoding can be achieved by performing so-called frame dropping for static blocks, for example, without sending data of subsequent frames.

However, in this case, each block requires a 1-bit motion information code, but data can be compressed to 1/2 in the still area.

The number of bits for each block during re-encoding is assigned as a constant value smaller than the number of bits of the original 1i prime data, and the quantization step width is changed according to the dynamic range of each block (hereinafter referred to as fixed length). In addition to RC (referred to as RC; see the above publication), a method (hereinafter referred to as variable length ADRC) in which the number of bits allocated to each block is changed according to the size of the dynamic range of each block has also been proposed (for example, (See Japanese Patent Application Laid-Open No. 147689/1989).

FIG. 3 shows an example of the configuration of a variable length ADRC system.

That is, the television signal through the input terminal (1) is supplied to the ^/D converter (2), and each pixel is converted into, for example, 8-bit digital data.

This digital data is supplied to a block dividing circuit (3) and is divided into blocks, for example, every two-dimensional small block of 3 lines xsss. The data for each block is supplied to a maximum/minimum value detection circuit (4) to determine the maximum value MAX and minimum value MIN' of pixel data in each block.

The data for each block from the block division circuit (3) is
In addition, a delay circuit (
5) to the subtraction circuit (6). This subtraction circuit (6) is supplied with the minimum value MIN in the block from the detection circuit (4) and is supplied with each i! of this block. The minimum value MIN within the block is subtracted from the raw data to create difference data Δ
DATA is obtained. And the difference data ΔDAT
A is fed to an adaptive encoder (7).

On the other hand, the maximum value MA for each block from the detection circuit (4)
The data of Information indicating the allocated focus number BITS is formed.

The DR and BITS information from the detection circuit (8) is then supplied to the encoder (7), from which the differential data ΔDATA is compressed into data BPL with a number of bits smaller than the original 8 bits. In variable length ADRC,
This data BPL has the same number of bits within a block, but differs depending on the intra-block dynamic range for different blocks.

The pixel data within the l block belongs within the dynamic range DR from the minimum value MIN to the maximum value MAX. In adaptive encoder, intra-block dynamic range DR
is divided according to the number of allocated bits BITS in the block,
A code corresponding to each divided level range is set, it is determined to which level range each pixel data belongs, and a code corresponding to the level range to which each pixel belongs is set as output data HPL.

As examples of encoding methods in this case, two methods have been proposed, as shown in FIGS. 4 and 5, depending on which representative level is used as decoded data for each level range during decoding. However, in the examples shown in both figures, the number of bits of the output data BPL is set to 2 bits for ease of explanation.

In the example shown in Fig. gA4, the intra-block dynamic range DR is equally divided into four 2nd & I eyes Mwa, and the median values LO, Ll, L2 . L3 is used as a value during decoding. This method can reduce quantization distortion. This encoding method is called no-edge matching, and is hereinafter abbreviated as NEM.

In the example of FIG. 5, the representative minimum level LO is the minimum value MIN9, and the representative maximum level L3 is the maximum value MAX. That is, in this case, the dynamic range is (2stTg◆
1-2) = 6, and the minimum value MIN is used as the representative level of the division level range on the minimum level side, and
The maximum value MAX is used as the representative level of the 1'J level range closest to the maximum level. During that time, it is divided into two division levels, and the boundary level of each two division levels is set to the representative level L1. Let it be L2.

According to this method, pixel data having a minimum value of MIN and a maximum value of MAX always exist within one block.
There is an advantage that the number of encoded codes with zero error can be increased. This encoding method is called edge matching, hereinafter abbreviated as EM.

The output data BPL of the encoder (7) is defined by the following equation.

(In the case of NEM, it is constant) The output data BPL obtained in this way is sent to the output terminal (91)
transmitted through. At the same time, the intra-block dynamic range DR and the intra-block minimum value MIN are transmitted through the output terminals (92) and (91).

In this case, the additional codes to be transmitted in addition to the data BPL are the dynamic range DR and the maximum value in the block MAX.
Or the minimum value within the block MIN and the maximum value within the block MAX
The transmitted data BPL, which may be , is supplied to the adaptive decoder (12) through an input terminal (111) on the decoding side. In addition, the transmitted intra-block dynamic range DR is supplied to the adaptive decoder (12) through the input terminal (11'3) and also to the BITS detection circuit (13).
The allocated bit number old TS according to R is obtained from this, and this information BITS is supplied to the adaptive decoder (12).

Further, the transmitted intra-block minimum value MIN is supplied to the adder circuit (14) through the input terminal (112).

In the adaptive decoder (12), as shown in FIGS. 4 and 5, representative levels LO, Ll, L2 . Difference data ΔDATA'' is obtained by subtracting the minimum value MIN from each of L3, and this is supplied to the adder circuit (14) and decoded pixel data DAT
Since this decoded S pixel data 0^TA" is data for each block, the block is decomposed in the block decomposition circuit (15) and returned to the original time-series pixel data, which is converted into D. The /^ converter (16) converts it back to an analog signal and outputs it to the output terminal (17).

The calculation performed by the decoder (12) can be expressed as the following equation.

However, in the case of BITS-0, the NEM and EM are the same.

[Problem to be solved by the invention]

By the way, the above-mentioned ADRC type adaptive encoder (7
), even if the encoding method is NEM, E
Since M also includes division as shown in equations (1) and (2) above, it is not easy to configure this encoder with hardware.

Further, when the encoding method is EM, as shown in equation (2), the multiplication also includes a number other than a power of 2, which further makes implementation in hardware difficult.

And when I tried to convert the encoder to IC, NEM
It is desirable that the hardware be compatible with both the EM and EM encoding methods, but having two lines of hardware that perform the calculations of equations (1) and (2), respectively, would complicate the configuration and is therefore undesirable. do not have.

This invention aims to provide something that can eliminate all of the above-mentioned inconveniences.

[Means to solve the problem]

In order to achieve the above object, the first encoding method and the second encoding method can be selected, particularly in the encoding means of the high efficiency encoding device according to the present invention, and when the first encoding method is selected, the first encoding method and the second encoding method are selected. is the first arithmetic expression, which performs the arithmetic operation, and as this arithmetic means, the difference data Δ0^T^ obtained by the subtraction means (25) of the first or second arithmetic expression is to be multiplied. means (26) (33) for obtaining data;
Multiplying means (27) (34) for multiplying the data to be multiplied by the difference data ΔDATA and the difference data ΔDAT^
and means (28) (35) for obtaining output data BPL by truncating or rounding off the decimal parts of the data corresponding to the multiplication output of the multiplication means (27) (34).
).

(Operation) □ Means (26) for obtaining the data to be multiplied by the difference data 8DAT^ in the first or second arithmetic expression; the data from (33) and the subtractor [1! is multiplied by the multiplication means (27) (34), and when the first encoding method is selected by the means (2B) (35) for obtaining the output data BPL, the multiplication means (27) (34) selects the first encoding method.
7) A rounding operation is performed on the multiplication output in (34), and when the second encoding method is selected, a rounding operation is performed on the multiplication output.

(Embodiment) FIG. 1 is a diagram showing an embodiment of the above-mentioned adaptive encoder, in which pixel data is 8 bits, and variable length A
This is the case of IIRC, and the output data BPL is an example of a maximum of 4 bits.

In FIG. 1, (26) is a conversion circuit, and the data indicating the dynamic range DH and the allocated bit number BIT are obtained from the dynamic range detection circuit (8) of the example in FIG.
Data indicating S is input to the input terminals (22) and (
23) to this conversion circuit (26).

1. This conversion circuit (26) has an encoding method of NE.
An M or EM selection signal is supplied through the input terminal (24). This conversion circuit (26) is equipped with a ROM. This ROM contains the above (1) 12
) should be multiplied by the difference data of the formula, 2 kllTS/D
Data corresponding to the value of R or (2 pull 1S-1)/DR is stored in advance. When the encoding method is NEM, 2
When data corresponding to the old TS/OR and the encoding method is EM, data corresponding to (28"-1>/DR) is obtained by the conversion circuit (26) (hereinafter referred to as
The data corresponding to 21g1Tg/pH or (2""-1)/DR is referred to as 1ICIP).

Here, HECI considering the scale of the conversion circuit (26) etc.
The lIk number of bits to represent P will be explained below.

First, let us consider the number of bits for representing the integer part of RlICIP in different cases.

(a) In the case of dynamic range DR-0, there is no need to consider BPL, so there is no need to consider IHcIP either.

In the case of 81TS-0, there is no BPL, so there is no need to consider RlICIP.

(01 Dynamic range DR≧2stts 1 In this case, DR is less than the expression gradation that can be expressed with the given BITS, so BPL is as described in (1) above.
(2) may be followed, but BPL=I
NT (DATA-M I N) or BPL electronic RNL)
(DATA-MIN).

If BPL is based on equations (1) and (2), the possible range of RECIP is O≦RHCIP≦16 when BITS is a maximum of 4 bits. This maximum 1
If you want to represent RECIP up to 6, the integer part will be 5.
Bits are required.

However, as mentioned above, in the case of I) R≧2 rs-1, B P L -I NT
N) or HPL-RND (DATA-MIN), it can be set to 1tEclP -1. Therefore, including the case of DR<24117g-1, the possible range of ugcip is O≦RHCIP:51
Therefore, the integer to represent RlICIP can be 1 bit, which means RECIP is (l).

The number of bits representing the integer part of RhCIP is 4 bits less than when formula (2) is used, and the scale of the conversion circuit (26) can be reduced accordingly.

Therefore, if DR≧281g-1, )? E
CIP -1, and the integer part of RlCIP is 1 bit.

Next, the number of bits for representing the decimal point in RHCIP will be explained.

In order to accurately represent MlICfP, it is conceivable to increase the number of points below the decimal point.

However, as described below, there are problems that cannot be solved simply by increasing the number of bits.

In other words, for example, N-15, DR-76, BItS-1, N-15, DR-76, BItS-1
In the case of °NEM, it is possible to calculate the BPL as follows.

RlICIP = -X 215-862.3...7
When calculating BPL by rounding off the value of , the result is 0. However, when calculating BPL by hand, the result is different from the previous calculation.

This is what is placed after the decimal point when the R#ICIP force is quantized.

Therefore, as long as rounding is performed during RECIP quantization, this will occur.

So, I? It is conceivable to round up to the nearest whole number instead of rounding off to the nearest whole number during HCIP quantization. That is, in the example above, RHCIP is 862
．． Round up the decimal part of 3-... to 863. Then, the result matches the result obtained by hand calculation. Therefore, Ml
When determining the number of bits representing the decimal point of ICIP,
Be sure to round up. When the pixel data is 8 bits and the output data BPL is 4 bits, the number of bits after the decimal point in RIECIP is 15 bits as a result of simulation if rounding up is enough to obtain an accurate result. there were.

Therefore, in this example, the integer part of RHCIP is 1 bit and the part below the decimal point is 15 bits.

This RlICIP is connected from the conversion circuit (26) to the multiplication circuit (2
7).

(25) is a subtraction circuit, and the delay circuit (5) in the example in Fig. 3
Pixel data 0 for each block of television signal through
^T^ is connected to this subtraction circuit (25) through the input terminal (20).
) and the minimum value MIN(
8 bits) is supplied to this subtraction circuit (25), from which differential data ΔDATA=DATA-MIN (8 bits) is obtained. This differential data ΔDAT is then supplied to a multiplication circuit (27).

Then, in this multiplication circuit (27), the difference data ΔDA
A multiplication of T^ and ICIP is performed. In this example in Figure 1, MuICIP is 16 bits, so this 16 bit RECIP and 8 bits ΔDAT
The multiplication circuit (27) with 8 bits is used. The multiplication result of the multiplication circuit (27) is supplied to a rounding circuit (28) having a ROM for converting it into a clipped, truncated or rounded version.

This conversion circuit (28) has the above-mentioned input terminal (24).
A selection signal for selecting whether the encoding method is NEM or EM is also supplied from the input terminal.

When the encoding method is EM, the rounding circuit (28)
Output data BPL of 4 bif I· is obtained by rounding off the decimal value F of the multiplication result from the multiplication circuit (27).

When the encoding method is NEM, the rounding circuit (28) obtains the multiplication result from the multiplication circuit (27) by truncating the decimal parts. Then, output data HPL in the case of NEM is obtained. Here, the arithmetic expression representing the output data BPL in the case of the above-mentioned NEM is shown below again.

In the above equation (5), in the case of NEM, DATA is M
At the time of AX value, ΔDA1' rib (equal to D R, ΔD
ATA x 2 & I TS 7 DR-21j ITs. 13PL is a code from 0 to 2ksLTSl, that is, in the case of the example in Figure 1, it is a code up to 4 bits, and does not represent 281Tli, and the code is Therefore, the number of bits of the integer part of the output data of the multiplication circuit (27) is set to 5 bits, which is one bit more than the number of bits of BPL, so that 2&IITS can also be expressed.

When the multiplication result data supplied to the rounding circuit (28) is 21jlTS, this data is clipped so that the BPL becomes 2MITS-1.As described above, the multiplication circuit The number of bits of the output data in (27) is 6 bits in total, with 5 bits for the integer part and 1 bit for the decimal point, considering both the NEM and EM methods.

In FIG. 1, (29) to (32) are pipeline registers for high-speed processing. These registers (29) to (32) are connected to each circuit (25) to (28).
This is not necessary if the system operates at a sufficiently high speed.

FIG. 9A2 is a diagram showing another embodiment of the adaptive encoder.

Note that this example in Figure 2 is )! 1: By representing CIP in a floating point system, the multiplication circuit can be made smaller than the one in the example shown in FIG. 1. The principle thereof will be described below.

REC1')' in the case of the example in Figure 1 is as follows (6), (7
It can be expressed by one equation.

In the case of NEM, in the case of EM, where N indicates the number of bits below the decimal point, and "round up ()" neglects to round up the decimal point if the decimal point of the value in () is not 0.

When ut:cip is expressed as in equations (6) and (7), all N bits are used even if RHCIP is small and most of the high-order bits are 0, and there are few effective digits. It has been multiplied.

Therefore, in the example in Figure 2, if )+1ICIP is small, the significant digits of )IEcIP are shifted to the left so that l is always set in the upper bit of the eel, and this RHCIP is
is multiplied by ΔDATA, and after this multiplication, it is shifted to the right by the shifted amount.

Now, assuming that the number of digits to be shifted is 5HI)'T, this S old 1'T can be expressed by the following formula 181 (91).

At NEM, 5IIIFT = I N'l' (log2DR-B
ITS) ” (at 81EM, 5) IIFT-I N T (log2DR-log
2(2””-1)) ・・・(
9) uactp with the significant figures shifted to the left by S old FT shown in equations (8) and (9) above is as follows (10),
It can be expressed by equation (11).

At NEM, at EM, multiply RlICIP and ΔDATA,
By shifting this multiplication result to the right by S old ↑, the scale of the multiplication circuit can be reduced. In other words, REC
The number of bits representing IP can be reduced. Note that when the pixel data is 8 bits and the output data BPL is 4 bits, the simulation result is N-11 bif I.
was found to be sufficient.

The example shown in FIG. 2 will be described in detail below. Note that this second
Similar to the example in Figure 1, the example in the figure is an example in which the pixel data is 8 pins and the output data BPL is IJJ' variable at a maximum of 4 bits. It is attached.

In FIG. 2, (33) is a conversion circuit, and data indicating the dynamic range DI (and data indicating the number of allocated bits) are input terminals (22) and (23), respectively.
) is supplied to this conversion circuit (33). A selection signal indicating whether the encoding method is NEM or EM is supplied to the conversion circuit (33) through the input terminal (24).

This conversion circuit (33) is equipped with a ROM,
RIJCI shown in the above-mentioned formula (lO) or formula (11)
Data corresponding to P is stored in advance. Then, the supplied dynamic range L)R, the number of bits BITS
Then, RECI according to the selection signal of NEM or EM
The data (12 bits) corresponding to P is the multiplication circuit (34)
Then, the data (3 bits) indicating 5HIFT is R
It is fed to a rounding circuit (35) with OM.

The multiplication circuit (34) receives the data corresponding to the RHCIP described above as well as the difference data ΔD from the subtraction circuit (25).
ATA (8 bits) is supplied. Then, in this multiplication circuit (34), the difference data Δ0^TA and RECIP
Multiplication with data corresponding to is performed. This multiplier circuit (34) is 8 bits x 12 bits, later used, and the multiplier circuit (2'?> (8 bits x
16 bits). The multiplication result of this multiplication circuit (34) is supplied to a rounding circuit (35).

A multiplication circuit (34) is operated by a rounding circuit (35) in response to data indicating 5HIFT supplied from a circuit (33).
The result obtained by shifting the calculation result to the right is obtained.

Then, the rounding circuit (35) outputs the output data H, in which the decimal point of the shifted data is truncated or rounded off, depending on whether it is NEM or EM, as in the case of the example in FIG.
Get PL.

In addition, in this example in FIG. 2, DR≦2BITS-1
In the case of )l) ICIP = 1, as in the example in Figure 1,
It is made so that. Also, when NEM, DAT
A is the MAX value and ΔDATA×2kilTs/DR
= 2111Ts, as in the example in Figure 1,
It is designed so that it becomes 2 BITS 1 by crib.

In addition, (29), (36) to (
4o) is a pipeline register, and each circuit (25)
.

If (33) to (35) operate at a sufficiently high speed, then
Not necessarily necessary.

In addition, in the example of FIG. 1 and the example of FIG. 2, the conversion circuit (2
In 6) and (33), the RtICIP and 5HIFT are generated using a ROM, but they may also be implemented using an iterative method or constructed using logic.

Furthermore, the rounding circuits (2B) and (35) may also be constructed from logic.

In the above example, the case of variable length At)RC was explained, but in fixed length ^DRC, only B and ITS are constant, and it can be applied in exactly the same way.

〔Effect of the invention〕

As described above, according to the present invention, in an apparatus for highly efficient encoding of television signals, multiplication in encoding operation is replaced with multiplication using a conversion table. Easy and fast processing
Moreover, there is an effect that a highly efficient encoding device suitable for tC can be realized.

Furthermore, the present invention is applicable to any block size of television signals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the encoder of the high-efficiency encoding device according to the present invention, FIG. 2 is a diagram showing another embodiment of the encoder of the high-efficiency encoding device according to the present invention, and FIG. FIG. 4 is a block diagram of an example of an efficiency encoding device, FIG. 4 is an explanatory diagram of the first encoding method (NEM), and FIG. 5 is an explanatory diagram of the second encoding method (EM). (25) is a subtraction circuit, (26), (33) is a conversion circuit, (27) (34) is a multiplication circuit, (2B),
(35) is a rounding circuit.

Claims (1)

[Scope of Claims] Means for determining the maximum value of a plurality of pixel data and the minimum value of the plurality of pixel data included in a predetermined block of a digital television signal; subtracting means for obtaining differential data ΔDATA by subtracting from the maximum value and minimum value; and a dynamic range DR for each block from the maximum value and minimum value.
a means for detecting the difference data ΔDATA according to the detected dynamic range, the number of bits B being smaller than the original pixel data;
An apparatus comprising means for encoding with ITS, and means for transmitting at least two additional codes among the dynamic range information, the maximum value, and the minimum value, and the encoded code BPL. In the above encoding means, the first encoding method and the second encoding method can be selected, and in the case of the first encoding method, the first arithmetic expression, BPL=INT(ΔDATA× 2^B^I^T^S/D
R), and in the case of the second encoding method, the second calculation formula, BPL=R
ND{[ΔDATA×(2^B^I^T^S-1)]/
DR}, and as a means of this calculation,
Upon receiving the selection signal for the first encoding method and the second encoding method, the dynamic range DR, and the number of bits BITS, the first encoding method and the second encoding method are received. means for obtaining the data to be multiplied by the difference data ΔDATA out of the first or second arithmetic expression, and the data to be multiplied by the difference data ΔDATA obtained by the subtraction means. Difference data Δ
a multiplier for multiplying DATA; and receiving a multiplication output of the multiplier and a selection signal between the first encoding method and the second encoding method, and selecting the first encoding method. A high-efficiency encoding device for a television signal, comprising: means for rounding down when the second encoding method is selected, and rounding off when the second encoding method is selected to obtain output data BPL.