JPH0368597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for interframe encoding television signals.

In the digital transmission of television signals, the number of transmission bits is significantly reduced compared to when using normal PCM by using interframe coding, which encodes and transmits the differential signal of adjacent frames (bandwidth reduction compression). (referred to as ``PCM''), and a large compression ratio (ratio in which the number of transmitted bits is reduced compared to PCM), especially for pictures with small movements.
can be obtained. However, for pictures with large movements, there is a drawback that the compression ratio described above decreases because the difference signal between adjacent frames becomes large.

As a countermeasure to this, "motion compensated interframe coding"
(hereinafter referred to as known example 1) is considered. As shown in Figure 1, this method detects the motion vector V of the image, shifts the previous frame signal by the motion vector, calculates the difference with the current frame signal, and encodes and transmits the difference signal and motion vector. It is.

In this method, image motion detection is performed as follows. That is, the TV screen is divided into small blocks, each block is shifted with respect to the same position in the previous frame as a reference (this amount of shift is called a shift vector), the difference is calculated, and the evaluation function ( Various evaluation functions have been considered, such as the sum of the squares of the difference signals, the sum of the absolute values of the difference signals, or the number of cases where the absolute value of the difference signals exceeds a certain function value.This value measures the degree of similarity between the two. ) is determined, and the shift vector with the minimum value of the evaluation function is set as the motion vector for that block. but,
Since quite large movements can occur in television signals, it is necessary to calculate the above-mentioned evaluation function for quite a large number of shift vectors, and the amount of calculation becomes enormous, resulting in a large-scale apparatus. For example, if we detect movement in the range of 8 samples left and right and 8 lines above and below, (2×
The aforementioned evaluation function values are determined for 8+1)×(2×8+1)=289 shift vectors.

As a method to overcome this drawback, "Motion compensation in interframe coding" (Material No. IE78-6,) was presented at the Institute of Electronics and Communication Engineers Image Engineering Study Group on May 26, 1978.
There is a method published under the title. In this method, the motion vector detected in the block of the previous field (or previous frame) is used as the initial vector for detecting the motion vector of the block of the current frame, and the velocity detection range is narrowed based on the initial vector to detect the velocity. is being simplified. To give a concrete example, if the motion vector detected in the block of the previous frame is (V _xp , V _yp ), then the neighborhood, for example, V _xp -2≦V _x ≦V _xp +2, 25 shift vectors (V _x , V _y ) in the range of V _yp −2≦V _y ≦V _yp +2 (1)
In this method, the value of the above-mentioned evaluation function is determined only for the block, and the shift vector with the minimum evaluation function value is set as the motion vector for that block.

(Known Example 2) According to this Known Example 2, the number of shift vectors for determining the evaluation function value can be reduced, so that the apparatus can be simplified compared to the Known Example 1. However, in the known example 2, the speed is detected only for shift vectors in a narrow range around the initial vector, so there is no problem if the object is moving at a constant speed.
When a stationary object suddenly starts moving (the same applies when a moving object suddenly stops),
This method has the disadvantage that prediction efficiency decreases because it is no longer possible to follow sudden changes in speed and accurate motion vector detection is no longer possible. In order to prevent the prediction efficiency from decreasing even in such a case, there is no other way than to increase the number of shift vectors. To be able to
Since it is necessary to obtain evaluation function values for 49 shift vectors, the scale of the apparatus becomes large, although not as large as in the known example 1.

The purpose of the present invention is to solve the above-mentioned problems.
To provide an interframe coding device using a motion detection method, which does not significantly increase the device scale even for a fairly wide range of motion, and can accurately detect a motion vector even when the motion of a moving object suddenly changes. There is a particular thing.

Next, the present invention will be explained in detail with reference to the drawings.
In the present invention, the motion vector detected in the block of the previous field is used as the initial vector,
According to the initial vector, a shift vector for obtaining the above-mentioned evaluation function value is determined, and one of the shift vectors is detected as a motion vector, but no calculation is performed on all of the determined shift vectors, and the above-mentioned The present invention is characterized in that the amount of required calculations is further reduced by performing motion vector detection in multiple stages.

Referring to FIGS. 1 and 2, it is shown how motion vectors are detected in two stages.
A shift vector of 1,1 indicates that the previous frame signal is shifted one sample to the right and one horizontal scanning line (line) upward.

First, in Fig. 2 1, if the vector 1,1 (A in the figure) is the motion vector of the block in the previous field, then in the first stage (Fig. 2 1) A, B, C, D, E ,F,G,H,
The values of the above-mentioned evaluation function are determined for the nine first shift vector groups indicated by I, and among them, the shift vector with the minimum evaluation function value is determined. For example, if C is the shift vector with the minimum evaluation function value among A to I, then in the second stage (Fig. 2 2) the second shift vector group C ₁ to C placed near C is Similarly, for _C9 , find the shift vector that minimizes the evaluation function value. Temporarily C ₄
If the evaluation function value is the minimum, let _C4 be the motion vector in that block. At this time, the signal of the previous frame shifted by the shift vector _C4 is used as the prediction signal for the block of the current frame signal.
The difference signal between this predicted signal and the current frame signal and the shift vector C ₄ (or the difference vector between C ₄ and the initial vector A) are encoded and transmitted.

The above explanation is for the case where the motion vector of the block in the previous field is 1,1 and C becomes the minimum evaluation function in the first stage, but if the motion vector of the block in the previous field is another value, Even when other shift vectors have the minimum evaluation function value, motion vector detection is performed in exactly the same way. Furthermore, although the case of two-stage detection has been described here, the same applies even if there are more stages.

Therefore, the present invention provides a method for detecting signals from a previous frame signal (hereinafter abbreviated as "shifted previous frame signal") located at a position shifted from a block of the input television signal on the television screen and the input television signal. A means for obtaining an evaluation function value indicating the degree of similarity between the two, and a motion vector of a block for which motion vector detection has been performed at least one frame before is used as an initial vector, and a motion vector is detected by multi-step detection based on the initial vector. means for generating a predicted signal using the motion vector; and means for predictively encoding the input television signal using the predicted signal.

According to the present invention, it is possible to detect shift vectors in a wider range around the initial vector than in the conventional known example 2, that is, it is possible to follow even larger changes in speed, which is more efficient. Can be encoded.

According to the present invention, in the conventionally known example 1,
Even if it is necessary to calculate the evaluation function value for 200 or more shift vectors, 49 in the case of the known example 2, if the evaluation function value is calculated as shown in Fig. 2, the total of 18 shift vectors, 9 in the first stage and 9 in the second stage, can be calculated. It is only necessary to obtain the evaluation function value for each shift vector, and the amount of required calculations can be significantly reduced, and the device can be simplified.

Next, examples of the present invention will be described. FIG. 3 is a block diagram showing the configuration of an interframe encoding device according to an embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of a decoding device.

In FIG. 3, if the output of the frame memory 14 is connected to the signal line 16 except for the predicted signal generator 11, the second encoder 18, and the multiplexer 20, the configuration becomes exactly the same as that of the conventional interframe encoding device. . Further, in FIG. 4, the demultiplexer 26, the second decoder 37 and the variable delay circuit 3
If the signal lines 25 and 27 and the signal lines 33 and 35 are the same signal line except for the signal line 4, the configuration will be exactly the same as the conventional interframe decoding device. Therefore,
In the following description, components specific to the present invention will be described in detail.

In FIG. 3, it is assumed that an A/D (analog-digital) converted television signal (hereinafter abbreviated as TV signal for simplicity) is input from terminal 1. A TV signal input from terminal 1 is given to delay circuit 3 and predictive signal generator 11 . The delay circuit 3 is used to synchronize the timing of the prediction signal output from the prediction signal generator 11 via the signal line 16 and the TV signal input from the terminal 1 in the subtracter 5 . The delayed TV signal output from the delay circuit 3 through the signal line 4 is subtracted by a subtracter 5 from the prediction signal output from the prediction signal generator 11 through the signal line 16, and this difference signal (prediction error signal ) is input to a quantizer 7 via a signal line 6, quantized, and sent via a signal line 8 to a first encoder 9 and an adder 1.
7 is input. Here, the first encoder 9 performs unequal length encoding on the quantized prediction error signal, similar to that used in a conventional interframe encoding device. The quantized prediction error signal input to the signal line 8 is encoded and output to the signal line 10. On the other hand, the quantized prediction error signal is given to the adder 17 via the signal line 8, added to the prediction signal output from the prediction signal generator 11 to the signal line 16, locally decoded, and sent via the signal line 13. The predicted signal generator 11 is used to generate a predicted signal in the next frame. The predicted signal generator 11 is connected to the signal line 2
The input TV signal input via the signal line 15
From the signal from one frame ago inputted via
The motion vector detection described above is performed and a predicted signal is output to the signal line 16. Further, the predicted signal generating section 11 supplies a signal indicating the detected motion vector to the second encoder 18 via the signal line 19. The second encoder 18 encodes the input signal, for example, performs unequal length encoding, and outputs the encoded signal to the signal line 12 .

The encoded motion vector outputted to the signal line 12 is multiplied by the encoded prediction error signal outputted to the signal line 10 in the multiplexer 20 and sent to the signal line 21. The multiplexed signal on the signal line 21 is written to a transmitting side buffer memory 22 for speed matching with the transmission speed of the transmission line, and the signal written to the transmitting side buffer memory 22 is read out at the transmission speed of the transmission line. Transmission line 2
Sent on 3rd.

Next, the decoding device will be explained with reference to FIG.

The signal output from the encoding device to the transmission path 23 is written to the receiving side buffer memory 24 at the transmission speed of the transmission path, is read out to the signal line 25 by the clock pulse of the decoding device, and is shown as a prediction error signal by the demultiplexer 26. The code and the code indicating the motion vector are separated and output to signal lines 27 and 28, respectively.

The code indicating the prediction error signal is decoded by the first decoder 36, and the prediction error signal is input to the adder 29 via the signal line 31. On the other hand, the shifted previous frame signal, that is, the predicted signal output from the variable delay circuit 34 is inputted to the adder 29 via the signal line 35, and as a result, the signal is inputted via the signal line 31 and the signal line 35. signals are added and the TV
The signal is decoded and output to signal line 30. Also,
The signal on the signal line 30 is written into the frame memory 32 and used for decoding the TV signal of the next frame. Further, the signal read from the frame memory 32 is input to a variable delay circuit 34 (the configuration of which will be described later), and the shifted previous frame signal mentioned above is output.

On the other hand, the code indicating the motion vector outputted from the demultiplexer 26 to the signal line 28 is decoded by the second decoder 33, outputted to the signal line 39 as a shift control signal, and inputted to the variable delay circuit 34. . The variable delay circuit 34 shifts the signal applied via the signal line 33 in accordance with the shift control signal and outputs it to the adder 29 via the signal line. This decodes the TV signal.

Next, the predicted signal generating section 11 will be explained with reference to FIG. Note that an example in which a plurality of horizontal scanning lines of a TV signal are processed in parallel will be described below. The unit of this parallel processing matches the vertical size of the block (in this example, the block size is explained as 8 horizontal scanning lines x 16 pixels, so it is 8), but in particular, it is divided into scanning lines. Unless otherwise necessary for explanation, for example, a single thick line such as the signal line 45 in FIG. 5 will be used as a representative. The prediction signal generation unit 11 receives input
Temporarily stores the TV signal and blocks blocks of the current frame.
The first memory 40 outputs the TV signal at each stage of the motion vector detection described above, and the control circuit 42 temporarily stores the local decoded signal of the previous frame, and outputs the block of the current frame according to the shift vector group of each stage. It includes a memory section 41 that outputs a block of the previous frame at a shifted position. Furthermore, the memory section 41 is
When a motion vector is supplied from the control section 42, a block of the previous frame at a position shifted from the block of the current frame by the amount of the motion vector is provided to the second memory 44. A prediction signal 16 is output from the second memory. A block of the current frame is supplied to the detector 43 from the first memory, and the block of the current frame is supplied to the detector 43 from the first memory.
The block of the previous frame corresponding to the shift vector group of each stage is supplied from the control circuit 42.
This shift vector group is supplied from . Then, the detector 43 obtains the above-mentioned evaluation function value from the given current frame block and the blocks of the previous frame supplied by the number of shift vectors, and selects the shift vector with the minimum evaluation function value. It is transferred to the control circuit 42.

The control circuit 42 includes the vector field memory 1
A first stage shift vector group is generated in accordance with the motion vector obtained from the previous field block outputted from 60, and outputted to signal lines 53-55 as a shift control signal. According to the example explained in FIG. 2, when the motion vector determined in the block of the previous field, that is, the output of the vector field memory 160 is 1,1, the motion vectors shown by A to F in FIG. Shift control signals corresponding to the shift vector group are output to signal lines 53 to 55,
It is applied to the memory section 41. In addition, the control circuit 42
When the evaluation function value calculation for the first shift vector group is completed, the shift vector that shows the minimum evaluation function value among the first shift vector group is the center, and is smaller than the first shift vector group. Shift control signals corresponding to the densely arranged second shift vector group are applied to the memory section 41 via signal lines 53 to 55. According to the example in FIG. 2, if the evaluation function value for shift vector C is the smallest among the first stage shift vector groups A to F, the control circuit 42 controls the second stage shift vector group A to F. As a group, the shift vectors C ₁ to _{C 9} of FIG.
A shift control signal corresponding to the shift control signal is applied to the memory section 41 via signal lines 53 to 55. That is, the first
The memory 40, the memory section 41, and the detecting section 43, which will be described later, are used repeatedly at each stage.

The above is an outline of the configuration and operation of the predicted signal generation section 11. Below, the operation in FIG. 5 will be explained in more detail, and with reference to FIGS. 6 to 9,
The configuration and operation of each component in FIG. 5 will be explained.

The input TV signal input from terminal 1 in FIG. 3 is written into the first memory 40, and every time the aforementioned detection steps are performed, the vertical size of the block (i.e. 8 lines) is read out in parallel. signal line 4
5 is output.

The memory section 41 receives the signal from the frame memory 14 via the signal line 15 from the previous frame, and each time the above-mentioned stages of detection are performed,
Shift control signals corresponding to shift vector groups at each of the above-mentioned stages are inputted from the control circuit 42 via signal lines 53 to 55. The memory section 41 extracts the signal of the previous frame at a position shifted according to the shift control signal with reference to the position on the TV screen corresponding to the block of the current frame, and outputs it to signal lines 46-48. That is, the previous frame signal shifted in response to the shift control signal on the signal line 53 is output to the signal line 46, and the previous frame signal shifted in response to the shift control signal on the signal line 54 is output to the signal line 47. The same applies to the signal line 55 and the signal line 48.

The detector 43 uses the signal of the current frame sent via the signal line 45 and the signal group shifted by an amount corresponding to the shift vector at each stage of motion detection given via the signal lines 46 to 48.
At each stage, the aforementioned evaluation function value is transferred to the signal line 53.
55 to calculate the shift vector that minimizes the evaluation function value, and provides it to the control circuit 42 via the signal line 51 and the minimum value of the function value to the signal line 98.
The signal is applied to the control circuit 42 via the control circuit 42. However, signal line 5
If the control circuit 42 determines the shift vector of the next stage only by the shift control signal inputted through 1, it is not necessary to input the minimum value to the control circuit 42. An example of this case will be described below. The control circuit 42 sends a shift control signal indicating the next stage shift vector group belonging to the shift vector given via the signal line 51 to signal lines 53 to 5.
5 and supplies the memory address to the first memory 40 and memory section 41 via signal lines 50 and 49, respectively, to start the next stage of detection.

Further, at the time when the final stage of motion detection is completed, the control circuit 42 connects the signal line 5 from the detector 43 to the signal line 5.
The shift vector with the minimum evaluation function value given via 1 is sent as is to the signal line 19, and the address is also supplied to the memory section 41 via the signal line 49. The memory section 41 is connected to the signal line 57
A signal obtained by shifting the signal of the previous frame according to the motion vector is outputted and inputted to the second memory 44. Further, the motion vector signal outputted to the signal line 19 is written into the vector field memory 160, and is used as an initial vector in detecting the motion vector of a block in the next field. Also,
The control circuit 42 supplies the address to the third memory 44 via the signal line 52, and the prediction signal is written into the second memory 44. The prediction signal is read out from the second memory 44 and sent to the third memory 44 via the signal line 16.
It is applied to subtracter 5 and adder 17 in the figure.

After the above operations are completed, the control circuit 42 transfers the motion vector in the previous field block from the vector field memory 160 to the signal line 161.
outputs a shift control signal corresponding to the first stage shift vector to the read signal lines 53 to 55, and also outputs a shift control signal corresponding to the first stage shift vector to the read signal lines 53 to 55, and
The address of the next block is supplied to the block via signal lines 49 and 50, and motion detection and prediction signal generation for the next block are performed.

Next, the operation of the memory section 41 will be explained with reference to FIG. The previous frame signal applied from the frame memory 14 in FIG. 3 via the signal line 15 is the third
, and is output to the signal line 64 every time an address signal and a read signal are input from the control circuit 42 via the signal line 49. Here, the number of signals output in parallel through the signal line 64 is based on the assumption that the vertical size of the block is 8 lines, and that motion detection is performed up to 8 lines above and below on the TV screen. Then it becomes 24.

The signal on the signal line 64 is transmitted to variable delay circuits 61 to 6.
3,164. The number of variable delay circuits matches the maximum number of shift vectors in each stage of motion detection if one stage of detection is performed in parallel in one operation (for example, as shown in Figure 2). In the example explained in , there are 9 pieces in the first stage and 9 pieces in the second stage.
There are 9 stages, so there are 9). It is also possible to perform the detection of one stage in multiple steps, but this case will be described later.

The variable delay circuits 61-63 extract the previous frame signals shifted according to the shift control signals inputted via the signal lines 53-55, respectively, from the signals inputted via the signal line 64, and output them to the signal lines 46-46, respectively. 48 to the detection circuit 43.

Furthermore, at the time when the motion vector is detected in the final stage of speed detection, the signal line 19 is stored in the memory section 41.
The motion vector signal is input to the variable delay circuit 164, and the variable delay circuit 164 outputs a signal shifted according to the motion vector to the second memory 44 via the signal line 57.

The variable delay circuits 61-63, 164 will be explained with reference to FIG. However, variable delay circuit 6
Since the operations of circuits 1 to 63 and 164 are completely similar to each other, only the variable delay circuit 61 will be described. In addition, in the above explanation, the signal line 64 is 1 in the drawing.
In this case, the data of 12 horizontal scanning lines is input to the variable delay circuit 61 in parallel (for example, the vertical size of the block is 4 horizontal scanning lines, and 4 horizontal scanning lines above and below). The following describes the case where motion detection is performed up to Therefore, the signal lines 64 are displayed separately as 64 ₁ to 64 ₁₂ . In addition, in the above explanation, each of the signal lines 53 to 55 requires a number of lines corresponding to the number of bits necessary to express the maximum shift amount in each of the vertical and horizontal directions on the television screen. Yes, but
To simplify the explanation, it is represented by one line. Here, the line to which the horizontal shift control signal is sent is 53.
_1. Connect the line to which the vertical shift control signal is sent to 53 ₂
Shown as

In FIG. 7, it is assumed that the input signal lines 64 ₅ to 64 ₈ correspond to blocks of the current frame (i.e., if the vertical movement is 0, the input signal lines 64 5 to 64 8
The signals above 4 ₅ to 64 ₈ are selected as predicted signals).
Also, for convenience, it is defined that the smaller the subscript _N of 64N is, the higher it is on the TV screen.

When a control signal is sent to shift the signal line 53 ₂ up one line in the vertical direction and output it, the multiplexer 70 outputs the signal on the signal line 64 ₄ to the signal line 82 , and the multiplexer 71 outputs the signal on the signal line 64 4 .
_Similarly , the multiplexers 72 and 73 output the signals 64 6 and 64 7 to the signal lines 64 ₆ and 64 ₇ respectively.
The signals are output to signal lines 84 and 85. Similarly, when a vertical shift control signal with another value is input, the signal on the signal line at a position shifted by that value with respect to the signal lines 64 ₅ - 64 ₈ is transferred to the signal lines 82 - 8 .
5 is output.

The operation of the circuit composed of the multiplexers 70 to 73 explained above is basically based on POSITION S
-CALER (e.g. by Signatex)
“SIGNETICS DATA” published in 1976
MANUAL” page 267-page 270-8-BIT
POSIT-ION SCALER N 8243), so if the number of parallel output lines of the third memory 60 in FIG. 6 is small, the above-mentioned integrated circuit can also be used.

In Figure 7, reference numerals 86, 87, 88 and
Since the operation of the part indicated by 89 is exactly the same, the operation of the part indicated by reference numeral 86 will be explained.

The signal output to the signal line 82 is input to the shift register 74 with taps. Here, the number of taps of this shift register is determined by the maximum range of velocity detection in the lateral direction. For example, when detecting lateral movement up to 8 samples left and right, the number of taps is 17. The signals output from each tap of shift register 74 are applied in parallel to multiplexer 78. The multiplexer 78 outputs one of each input to the signal line 46 ₁ in response to the horizontal shift control signal input via the signal line 53 ₁ . In this way, it is possible to obtain the previous frame signal shifted in response to the shift control signals on the signal lines 53 ₁ and 53 ₂ with respect to the current frame signal block.

Here, the variable delay circuit 3 of the decoding device shown in FIG.
In addition to configuration 4, since the output of this variable delay circuit 34 is in units of one horizontal scanning line, this circuit 34 is connected to the variable delay circuit 6 on the transmitting side shown in FIG.
It is sufficient to configure only the part surrounded by the broken line with reference numeral 90 in 1 (in this case, the signal of the signal line corresponding to the position of signal line ₉₄₅ is output when the vertical movement is 0). ).

Next, the operation of the detector 43 will be explained with reference to FIG. As described in relation to the memory section 41, in the present invention, two configurations can be considered, depending on whether the detection of one stage is performed in one parallel operation or in several times. , First, we will discuss the case where detection of one stage is performed by one parallel operation (in this case, register 102 and register 103 are unnecessary. Also, signal lines 98 and 9
9 is also unnecessary.

The signals on the signal lines 46 to 48 are respectively sent to the calculation unit 9.
2 to 94 are input. On the other hand, calculation units 92 to 94
The signal of the block of the current frame is input to the signal line 45, and the above-mentioned evaluation function value is calculated. The calculation results are provided to the comparator 100 via signal lines 95 to 97, respectively. In addition, the comparison section 100
A shift control signal (corresponding to the shift amount of the shifted previous frame signal input via signal lines 46 to 48, respectively) is inputted to via signal lines 53 to 55, and the comparator 100 The evaluation function values input via signal lines 95 to 97 are compared, and a shift control signal corresponding to the one with the smallest evaluation function value is output to the signal line 51 (for example, the evaluation function values input via signal line 95 If the value is the minimum, the shift control signal on the signal line 53 is output to the signal line 51).

Next, a case will be described in which one stage of detection is divided into several times. However, since the operations of the calculation units 92 to 94 are exactly the same, a description thereof will be omitted. In this case, the minimum value of the evaluation function values input via the first signal lines 95 to 97 is the signal line 101.
is applied to register 102 via. Further, a shift control signal outputted via the signal line 51 is given to the register 103. In the second time, a shift control signal corresponding to a shift vector for which an evaluation function value is to be obtained next is applied, and the corresponding evaluation function value is obtained by the calculation units 92 to 94 and applied to the comparison unit 100. The comparator 100 compares the second calculation result (that is, the calculation result for the second input shift control signal) provided via signal lines 95 to 97 with the first calculation result input from the register 102 via signal line 98. A comparison is made with the minimum value detected the first time (the shift vector indicating the first minimum value is also input from the register 103 via the signal line 99). Therefore, from the second time onwards, the evaluation function values input via the signal lines 95 to 97 and 98 are compared, and this is continued until the final result of that stage is obtained. Note that there is no signal input from the signal line 98 at the first time, but if the register 102 is forcibly set to the maximum value that the evaluation function can take, the signal line 98 will be input at the first time. The value input via 98 will never be the minimum value.

Next, the operations of the calculation units 92 to 94 will be explained with reference to FIG. However, since the operations of the calculation units 92 to 94 are exactly the same, only the calculation unit 92 will be described. In addition, in the arithmetic unit 92, parallel processing is performed by the number of lines corresponding to the vertical block size (here, 4 lines are shown), so that the signal line ₄₆₁ in FIG. We will only explain the lineage leading to .

The current frame signal input from the signal line 45 ₁ and the shifted previous frame signal input via the signal line 46 ₁ are subtracted in the subtracter 110 ₁ , and the difference signal is provided to the threshold value determination circuit 111 ₁ . It will be done. The threshold determination circuit 111 ₁ determines whether the absolute value of the input difference signal exceeds a certain threshold, and if so, increments the counter 112 ₁ by one. However, the counter is cleared at the start of motion detection in each stage (if the detection in each stage is divided into multiple times, this can be read as the start of each detection). At the end of each stage of motion detection, the values of the counters 112 ₁ to 112 ₄ are read out and input to the adder 113, and the values are input to the signal line 4.
The calculation results of the four systems starting from 6 ₁ to 46 ₄ are summed and output to the signal line 95 .

Note that in the above explanation, the motion detection evaluation function is
In the case where the evaluation function is "the number of signals whose absolute value exceeds a certain threshold", when the evaluation function is "the sum of the absolute values of the difference signals", the determination circuits 111 ₁ to 111 ₄ Replaced with an absolute value circuit, that is, a circuit that outputs the absolute value of the input, and counter 1
12 ₁ to 112 ₄ may be replaced with accumulators. In addition, when the evaluation function is "sum of squares of difference signals", the determination circuits 111 ₁ to 111 ₄ are
What is necessary is to replace it with a multiplication circuit, that is, a circuit that outputs the square of the input signal, and replace the counters 112 ₁ to 112 ₄ with accumulators.

Next, the comparing section 100 will be explained with reference to FIG. Although FIG. 10 shows a case where the output signals of four arithmetic units and the shift control signals corresponding to each are input, the configuration can be made in the same manner even when the number of input signals is other.

First, the calculation results of the arithmetic unit input through signal lines 95 and 96 are sent to the comparator 120 and multiplexer (hereinafter abbreviated as "XPX"), respectively.
122. Comparator 120 is connected to signal line 95
and the signal value on the signal line 96, and if the signal value on the signal line 95 is smaller, the MPX122
output the value of the signal line 95 to the signal line 135 through the signal line 125; otherwise, the value of the signal line 95 is output to the signal line 135.
Output the value of 6. On the other hand, if it is also connected to the signal MPX132 on the signal line 125 and the value of the signal line 95 is smaller, then the signal line 95 is connected to the signal line 95 on the signal line 125.
The shift control signal of the signal line 53 corresponding to the value of is output to the signal line 137.
A shift control signal of the signal line 54 corresponding to the value of is output.

Comparator 121, MPX123 and MPX133
Exactly the same thing is done for signal lines 97 and 98 depending on the magnitude relationship between the values of signal lines 97 and 98.
and 98, the smaller value is output to the signal line 136, and the shift control signal corresponding to the smaller value is output to the signal line 138.

Further, the values output to signal lines 135 and 136 are input to comparator 124 and MPX 127,
If the value of signal line 135 is smaller, MPX1
34 to the shift control signal of signal line 137 to signal line 5
1, otherwise the signal line 138
output the shift control signal. Also, MPX1
27 outputs the smaller value of signal lines 135 and 136 to signal line 101.

As explained above, according to the present invention, efficient encoding can be performed even for larger speed changes than in conventional known examples 1 and 2.
A motion compensated interframe coding device can be realized with a smaller device scale than the previous method.

In the above explanation, 1 is used as the initial vector for detecting the motion vector of each block.
Although we have explained that the motion vector in the block before the field is used, the motion vector in the previous block or the block one block above on the television screen is used as the initial vector (in principle, the motion vector in the previous block than the current block is used). It is also possible to use a motion vector in a block for which vector detection has been performed) as an initial vector. In that case, only the storage capacity of vector field memory 160 changes.

In addition, in the above explanation, the speed information was explained as if the motion vector detected in each block (C ₄ in the example in Fig. 2) is encoded as is, but the motion vector and initial vector in each block are It is also possible to transform the difference vector of In that case, the output of the vector field memory 160 in FIG. 5 and the output of the control circuit 42 may be output to a subtracter, and the subtracter output may be input to the second encoder 18 in FIG. 3. This configuration has the advantage that the number of bits required for encoding speed information can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a motion compensation interframe coding method. 2. FIGS. 1 and 2 are diagrams for explaining image motion detection in the present invention, and FIGS. 3 and 4 are block diagrams of an interframe coding/decoding device showing an embodiment of the present invention, and FIGS. FIG. 10 is a block diagram showing one embodiment of the components used in the embodiment of the present invention. In the figure, 3...Delay circuit, 5...Subtractor,
7... Quantizer, 9, 18... Encoder, 11...
Prediction signal generation unit, 14...Frame memory, 17
...Adder, 20...Multiplexer, 22...
Transmitting side buffer memory, 24... Receiving side buffer memory, 26... Demultiplexer, 29... Adder, 32... Frame memory, 34... Variable delay circuit, 36, 37... Decoder.

Claims (1)

[Claims] 1 One frame (or one frame) of an input television signal
a motion vector detection means for dividing a field) into a plurality of blocks and detecting a motion vector representing a motion of a television image for each block;
means for generating a prediction signal that compensates for the motion of the television image based on the motion vector; means for predictively encoding the input television signal using the prediction signal; and encoding the motion vector. In the interframe encoding device, the motion vector detection means includes at least (a) motion vector storage means for storing motion vectors detected at least one frame before; (b) motion vector storage means for storing motion vectors detected at least one frame before; The value of the evaluation function indicating the degree of similarity between the television signal of the previous frame, which is located at a position shifted by the shift vector from the block of the input television signal, and the block of the input television signal is calculated, and the value of the evaluation function indicating the maximum degree of similarity is calculated. (c) creating a first shift vector group using a motion vector of a block for which motion vector detection has been performed at least one frame before output from the motion vector storage means as an initial vector; and supplies this first shift vector group to the evaluation function value calculation means, and the evaluation function value calculation means
The (n+1)-th A shift vector group is determined, the (n+1)th shift vector group is supplied to the evaluation function value calculation means, and the evaluation function value calculation means calculates the evaluation function value group calculated based on the Nth shift vector group. An interframe encoding device comprising: means for generating the predicted signal by using a shift vector showing a maximum degree of similarity as the motion vector; and means for supplying the predicted signal to the motion vector storage means.