JPH0133994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television signal encoding apparatus.

In the digital transmission of television signals, the number of transmission bits is significantly reduced compared to when using normal PCM by using interframe coding, which encodes and transmits the differential signal of adjacent frames (bandwidth compression and This allows for a large compression ratio (ratio in which the number of transmitted bits is reduced compared to PCM), especially for pictures with small movements.
can be obtained. However, for pictures with large movements, there is a drawback that the compression ratio described above decreases because the difference signal between adjacent frames becomes large.

As a countermeasure to this problem, something called "adaptive predictive coding" is being considered. This method divides the input television signal into blocks, and selects one optimal prediction signal with the highest similarity to the block from among multiple prediction signals generated for each block to predict the input television signal. It is something that is encoded. One type of adaptive predictive coding is "motion compensated interframe coding." This method detects the motion (motion vector) of the television image, shifts the previous frame signal by the motion vector (the signal shifted by this motion vector corresponds to the optimal predicted signal), and then The difference signal and the motion vector are encoded and transmitted.

The present invention will be explained in detail below by taking this "motion compensated interframe coding" as an example.

In motion compensated interframe coding, image motion (motion vector) is detected as follows.
In other words, the TV image is divided into small blocks,
For each block, the previous frame signal is shifted based on the same position on the TV screen (this amount of shift is called a shift vector, and this shifted frame signal corresponds to the predicted signal), and the current frame is The difference from the signal of the block is taken, and the value of the evaluation function is determined from this difference signal, and the shift vector with which the evaluation function value (hereinafter abbreviated as evaluation value) is the minimum is taken as the motion vector of that block.

In this case, the following two evaluation functions have conventionally been used.

To explain with reference to Figure 1, in the figure x→ _i
is a position vector indicating the pixel position on the TV screen, v→ _j
is a shift vector, Y(x→ _i ) is the brightness value of the current frame at pixel x _i , and Y′(x→ _i ) is the brightness value of the previous frame at pixel x→ _i .

Evaluation function 1 (D ₁ (v→ _j )) D ₁ (v→ _j ) = 〓 ⁱ d _i , _j (1) Evaluation function 2 (D ₂ (v→ _j )) D ₂ (v→ _j ) = 〓 ⁱ TH(d _i , _j ) (2) However, d _i , _j = [Y(x→ _i )−Y′(x→ _i +v→ _j )
] TH (d _i , _j )=1 (when d _i , _j ≧T (threshold)) 0 (when d _i , _j <T) Also, in equations (1) and (2), 〓 ⁱ is within the block This shows the integration for pixels.

Here, to explain the meaning of equations (1) and (2), equation (1) calculates the value obtained by integrating the absolute values d _i , _i of the difference signal for the pixels in the block, and calculates the value for the shift vector v→ _j . It indicates that it is a value. Also, equation (2) is
The number of pixels for which d _i , _j exceeds the threshold T (that is, it can be considered as the ratio of pixels that exceed the threshold T by performing the shift v → _j ) is the evaluation value for the shift vector v → _j . It is shown that.

Using equation (1), the motion vector detection accuracy is high;
Although the effect of reducing the amount of generated information is large, the disadvantage is that the scale of the apparatus becomes large because calculation of evaluation values and comparison of evaluation values require high calculation precision. For example, if the block size is 4 lines x 8 pixels,
Assuming that the precision of the absolute difference values d _i and _j is 8 bits, the integration result of equation (1) requires a precision of 13 bits,
The 13-bit signals for various shift vectors will be compared.

Equation (2) is a simplified version of Equation (1) in order to solve this problem, but compared to Equation (1), it is easier to detect motion vectors especially in pictures with large movements or when the block size is small. It has the disadvantage of reduced accuracy. More generally, there is a possibility that a non-optimal prediction signal may be mistakenly selected from among a plurality of prediction signals.

The purpose of the present invention is to solve the above problems (f)
It is an object of the present invention to provide a television signal encoding device using an evaluation function that is simpler than the equation (2) and has a better detection accuracy for optimal prediction than the equation (2).

Again, the features of the present invention will be explained by taking the motion compensated interframe coding method as an example. In this case, in detecting a motion vector, the level of a pixel of the previous frame at a position shifted by the shift vector from the same position as the pixel of the current frame on the TV screen and the pixel of the current frame is compared, and the level of the pixel of the current frame is compared. Quantify the degree of (for example, d _i , _j ) as described below,
A motion vector is detected by integrating the digitized values for pixels within a block to obtain an evaluation value, and motion-compensated interframe coding is performed. The method of digitization will be explained. In the present invention, the degree of difference d _ij
That is, by converting the value corresponding to the prediction error signal power when this shift vector is a motion vector into a value that can be expressed with a smaller number of bits than the number of bits required to express the input TV signal, ( While obtaining the same effect as formula 1), the calculation accuracy is reduced and the device configuration is simplified.

According to the present invention, the apparatus scale is smaller than when the above equation (1) is used as the evaluation function, and the motion vector detection accuracy equivalent to that of the equation (1), generally speaking, the optimum prediction signal detection accuracy can be obtained. In other words, there is an advantage that encoding efficiency equivalent to that of equation (1) can be obtained.

Next, the principle of the present invention will be explained. First, the reason why the detection accuracy of equation (2) is inferior to equation 1 will be explained.

As the evaluation function for motion vector detection, it is necessary to use one that has a relationship such that the smaller the evaluation value, the smaller the amount of information to be transmitted.
From this point of view, equation (1) is said to be the most logical evaluation function. However, in equation (2), only consideration is given to whether or not the absolute difference value d _i , _j exceeds a threshold, and the magnitude of d _i , _j , that is, the magnitude of the error power, is almost ignored. This is the reason why the detection accuracy is not as high as that of equation (1). Therefore
If an evaluation function (equation (1) corresponds to this) that also takes into account the magnitudes of d _i and _j is used, the motion vector detection accuracy will be improved compared to the expression (2).

In the present invention, the absolute difference value _di , _j expressed by No bits is converted into a signal e _i , _j that can be expressed by N (1<N<No) bits, and the signals are integrated for the pixels in the block. The accumulated value is the evaluation value.

Here, the conversion of d _i and _j will be explained in more detail. In the present invention, the conversion is performed taking into consideration the sizes of d _i and _j . In other words, d _i , _j is converted as described below to convert it into a signal e _i , _j that can be expressed with a smaller number of bits than d _i , _j . In other words, the values of d _i , _j are divided into at least three groups (the sizes are not necessarily the same) according to the size of the values, and small d _i , _j are grouped into small groups, and large d _i , _j are grouped into small groups. They are made to belong to large groups, and each group is given one value depending on its size. In other words, a small value is given to a small group, and a large value is given to a large group. An example of this conversion is shown in FIG. In FIG. 2, the horizontal axis is d _i , _and the vertical axis is conversion output e _i , _j . FIG. 2 shows an example of converting an 8-bit di, _j signal into a 3-bit _{e i , j} signal.

Here, the reason why the number of groups is limited to three or more will be explained.

If the number of groups is 2, the result in this case is the same method as the above-mentioned equation (2), but as mentioned above, this method has a higher motion vector detection accuracy than the above-mentioned equation (1) and the method according to the present invention. It depends on the circumstances of being inferior. The reason for performing such a conversion is that when large d _i , _j occurs, the evaluation value is calculated for a shift vector that is significantly different from the motion vector of the TV image, so the accuracy of motion vector detection In addition, small values of d i and _j occur frequently for shift vectors close to the motion vector, so unless the small values of d _{i and j} are faithfully reflected in the evaluation value, it will not be accurate. The motion vector cannot be detected. By performing such conversion, while maintaining the same motion vector detection accuracy as in equation (1), it is possible to reduce the equipment size (specifically, the accumulator required for integration) to be smaller than when using equation (1). Since the number of input signal lines is reduced, the capacity of the accumulator and the number of operation bits of the comparator required for comparing the magnitude of the evaluation value are reduced.)
Can perform motion vector detection.

In the above explanation, the degree of difference was described as being evaluated by the above-mentioned d _i , _{j ,} but the same effect can be obtained using other scales such as (d _i , _j ) ² . I would like to add a comment here: If you want to simply simplify the device, it is easy to think of a method of cutting off the lower bits of d _i and _j and integrating only the higher bits to obtain the evaluation value. However, this method only reduces the calculation accuracy, and it cannot be said that the values of d _i and _j are faithfully reflected in the evaluation value, and the motion vector detection accuracy is lower than the method of the present invention.

As described above, according to the present invention, the scale of the device is smaller than when formula (1) is used as the evaluation function, and (2)
The motion vector detection accuracy is improved compared to the formula.

Next, examples of the present invention will be described.

FIG. 3 is a block diagram showing an embodiment in which the present invention is applied to a motion compensated interframe coding device. In FIG. 3, the prediction signal generator 11, the second
If the output of the frame memory 14 is connected to the signal line 16 except for the encoder 18 and the multiplexer 20, the configuration becomes exactly the same as the conventional interframe encoding device. Therefore, in the following description, components specific to the present invention will be described in detail.

In FIG. 3, it is assumed that an A/D (analog-digital) converted television signal (hereinafter abbreviated as TV signal for simplicity) is input from terminal 1. A TV signal input from terminal 1 is given to delay circuit 3 and predictive signal generator 11 . The delay circuit 3 is used to synchronize the timing of the prediction signal output from the prediction signal generator 11 via the signal line 16 and the TV signal input from the terminal 1. The delayed TV signal output from the delay circuit 3 through the signal line 4 is subtracted by a subtracter 5 from the prediction signal output from the prediction signal generator 11 through the signal line 16, and this difference signal (prediction error signal ) is input to a quantizer 7 via a signal line 6, quantized, and input via a signal line 8 to a first encoder 9 and an adder 17.
Here, the first encoder 9 performs unequal length encoding on the quantized prediction error signal, similar to that used in a conventional interframe encoding device. The quantized prediction error signal input to the signal line 8 is encoded and output to the signal line 10. On the other hand, the quantized prediction error signal is given to the adder 17 via the signal line 8, added to the prediction signal output from the prediction signal generator 11 to the signal line 16, locally decoded, and sent via the signal line 13. The predicted signal generator 11 is used to generate a predicted signal in the next frame.
The predicted signal generator 11 performs the above-mentioned motion vector detection from the input television signal inputted via the signal line 2 and the signal of one frame before inputted via the signal line 15, and converts the predicted signal into a signal. Output on line 16. Further, the predicted signal generating section 11 supplies a signal indicating the detected motion vector to the second encoder 18 via the signal line 19. The second encoder 18 encodes the input signal, for example, performs unequal length encoding, and outputs the encoded signal to the signal line 12 .

The encoded motion vector outputted to the signal line 12 is multiplexed with the encoded prediction error signal outputted to the signal line 10 in the multiplexer 20 and sent to the signal line 21. The multiplexed signal on the signal line 21 is written to a transmitting side buffer memory 22 for speed matching with the transmission speed of the transmission line, and the signal written to the transmitting side buffer memory 22 is read out at the transmission speed of the transmission line. Transmission line 2
Sent on 3rd.

Next, the predicted signal generating section 11 will be explained with reference to FIG. Note that an example in which a plurality of horizontal scanning lines of a TV signal are processed in parallel will be described below. The unit of this parallel processing matches the vertical size of the block (in this example, the block size is explained as 4 horizontal scanning lines x 8 pixels, so it is 4), but in particular, it is divided into scanning line units. Unless it is necessary to explain otherwise, for example, a single thick line such as the signal line 45 in FIG. 4 will be used as a representative.

The input TV signal input from terminal 1 in FIG. 45
is output to.

A signal from one frame before is inputted from the frame memory 14 to the memory unit 41 via the signal line 15, and every time a motion vector is detected, the control circuit 42
A shift control signal corresponding to the above-mentioned shift vector given via signal lines 53 to 55 is input from. The memory section 41 extracts the signal of the previous frame at a position shifted according to the shift control signal with reference to the position on the TV screen corresponding to the block of the current frame, and outputs it to signal lines 46-48.
That is, the previous frame signal shifted in response to the shift control signal on the signal line 53 is output to the signal line 46, and the previous frame signal shifted in response to the shift control signal on the signal line 54 is output to the signal line 47. signal line 55
The same applies to the signal line 48.

The detector 43 calculates the aforementioned evaluation value from the signal of the current frame sent via the signal line 45 and the signal group shifted by an amount corresponding to the shift vector given via the signal lines 46 to 48. The shift vectors input via the signal lines 53 to 55 are calculated to find the shift vector with the minimum evaluation value, and the shift vector is provided to the control circuit 42 via the signal line 51.

Further, at the time when the motion detection is completed, the control circuit 42 sends the shift vector (motion vector) with the minimum evaluation function value given from the detector 43 via the signal line 51 to the signal line 19 as it is. Further, an address is supplied to the memory section 41 via a signal line 49. The memory section 41 is connected to the signal line 57
A signal obtained by shifting the signal of the previous frame according to the motion vector signal given by is outputted and inputted to the second memory 44. Further, the control circuit 42 supplies the address to the second memory 44 via the signal line 52, and the prediction signal is written into the second memory 44. A prediction signal is read out from the second memory 44 and provided to the subtracter 5 and adder 17 in FIG. 3 via the signal line 16. After the above operations are completed, the control circuit 42 outputs the shift control signal corresponding to the shift vector to the signal lines 53 to 55 again, and also outputs the shift control signal corresponding to the shift vector to the first memory 40 and the memory section 42 via the signal lines 49 and 50. provides the address of the next block, and motion detection and prediction signal generation for the next block is performed.

Next, the operation of the memory section 41 will be explained with reference to FIG. The previous frame signal applied from the frame memory 14 in FIG. 3 via the signal line 15 is the third
, and is output to the signal line 64 every time an address signal and a read signal are input from the control circuit 42 via the signal line 49. Here, the number of signals output in parallel through the signal line 64 is based on the assumption that the vertical size of the block is 4 lines, and that motion detection is performed up to 4 lines above and below in the vertical direction on the TV screen. Then it becomes 12.

The signal on the signal line 64 is transmitted to variable delay circuits 61 to 6.
given to 3. Here, the number M of variable delay circuits
If all shift vectors (M') are to be detected within a range of 4 lines vertically up and down and 4 lines left and right horizontally on the TV screen, then 8
If the calculation of the evaluation value for item 1) is performed in parallel in one operation, M=M'. Although detection can be performed in multiple steps, this case will be described later.

The variable delay circuits 61 to 63, 164 are connected to the signal line 64.
from the signal input via the signal line 53.
The frame signals shifted in accordance with the shift control signals inputted through lines 46 to 48 and 57 are extracted and applied to signal lines 46 to 48 and 57, respectively.

The variable delay circuits 61-63, 164 will be explained with reference to FIG. However, variable delay circuit 6
Since the operations of circuits 1 to 63 and 164 are completely similar to each other, only the variable delay circuit 61 will be described.
Furthermore, in the above explanation, the signal line 64 is represented by one line in the drawing, but here, the data of 12 horizontal scanning lines is input to the variable delay circuit 61 in parallel (for example, when the data of 12 horizontal scanning lines is input to the variable delay circuit 61 in parallel) A case where the vertical size is 4 horizontal scanning lines and motion detection is performed up to 4 horizontal scanning lines vertically will be described. Therefore, the signal lines 64 are divided and indicated as 64 ₁ to 64 ₁₂ from the top of the drawing. In addition, in the above explanation, each of the signal lines 53 to 55 requires a number of lines corresponding to the number of bits necessary to express the maximum shift amount in each of the vertical and horizontal directions on the television screen. However, to simplify the explanation, I have used one line to represent it. Here, the line to which the horizontal shift control signal is sent is shown as 53 ₁ , and the line to which the vertical shift control signal is sent is shown as 53 ₂ .

In FIG. 6, it is assumed that signal lines 64 ₅ to 64 ₈ correspond to blocks of the current frame (i.e., when the vertical movement is 0, signal lines 64 5 to 64 8
The signal above ₅ to 64 ₈ is selected as the predicted signal).
Also, for convenience, it is defined that the smaller the subscript _N of 64N is, the higher it is on the TV screen.

When a control circuit is sent that shifts the signal line ₅₃₂ up one line in the vertical direction and outputs it, the multiplexer 70 outputs the signal on the signal line ₆₄₄ to the signal line 82, and the multiplexer 71 outputs the signal on the signal line 644.
_Similarly , the multiplexers 72 and 73 output the signals 64 6 and 64 7 to the signal lines 64 ₆ and 64 ₇ respectively.
The signals are output to signal lines 84 and 85. Similarly, when a vertical shift control signal with another value is input, the signal on the signal line at a position shifted by that value with respect to the signal lines 64 ₅ - 64 ₈ is transferred to the signal lines 82 - 8 .
5 is output.

The rotation operation made up of the multiplexers 70 to 73 explained above is basically
POSITIONSCALER (e.g. “SIGNETICS” published in 1976 by Signetex)
DATA MANUAL” page 267-page 270-8-
BIT POSITION SCALER N8245), so if the number of parallel output lines of the third memory 60 in FIG. 5 is small, the above-mentioned integrated circuit can also be used.

In Figure 6 reference numerals 86, 87, 88
Since the operations of the parts indicated by reference numeral 86 and 89 are exactly the same, the operation of the part indicated by reference numeral 86 will be explained.

The signal output to the signal line 82 is input to the shift register 74 with taps. Here, the number of taps of this shift register is determined by the maximum range of velocity detection in the lateral direction. For example, when detecting lateral movement up to 4 samples on the left and right, the number of taps is 9. The signals output from each tap of shift register 74 are applied in parallel to multiplexer 78. The multiplexer 78 outputs one of each input to the signal line 46 ₁ in response to a horizontal shift control signal input via the signal line 53 ₁ . In this way, it is possible to obtain the previous frame signal shifted in response to the shift control signals on the signal lines 53 ₁ and 53 ₂ with respect to the current frame signal block.

Next, the operation of the detector 43 will be explained with reference to FIG. As described in relation to the memory unit 41, in the present invention, two configurations can be considered, depending on whether the motion vector detection is performed in one parallel operation or in several parallel operations. First, a case will be described in which a single parallel operation is performed (in this case, the registers 102 and 103 are unnecessary. Also, the signal lines 98 and 99 are also unnecessary.

The signals on the signal lines 46 to 48 are respectively sent to the calculation unit 9.
2 to 94 are input. On the other hand, calculation units 92 to 94
A block signal of the current frame is inputted to the block through the signal line 45, and the above-mentioned evaluation value is calculated. The calculation results are provided to the comparator 100 via signal lines 95 to 97, respectively. In addition, shift control signals (corresponding to the shift amount of the shifted previous frame input via signal lines 46 to 48, respectively) are input to the comparison unit 100 via signal lines 53 to 55, and The unit 100 compares the evaluation values input via the signal lines 95 to 97 and transmits a shift control signal corresponding to the one with the smallest evaluation value to the signal line 51.
(For example, if the evaluation value given via the signal line 95 is the minimum, the shift control signal of the signal line 53 is output to the signal line 51).

Next, a case will be described in which motion vector detection is performed in several steps. However, since the operations of the calculation units 92 to 94 are exactly the same, a description thereof will be omitted. In this case, in the first time, the signal line 95
The minimum value of the evaluation values input through 97 is given to the register 102 through the signal line 101.
Further, a shift control signal outputted via the signal line 51 is given to the register 103. At the second time, a shift control signal corresponding to a shift vector for which an evaluation value is to be obtained next is applied, and the corresponding evaluation value is obtained by calculation units 92 to 94 and applied to comparison unit 100. The comparison section 100 is connected to the signal line 9
5 to 97 (that is, the result of the operation for the shift control signal input the second time) and the minimum value from the first detection input from the register 102 through the signal line 98. (The shift vector indicating the first minimum value is also input from the register 103 via the signal line 99). Therefore, from the second time onward, the evaluation functions inputted via the signal lines 95 to 97 and 98 are compared, and this is continued until evaluation values are calculated for all shift vectors. Note that at the first time, there is no signal input from the signal line 98;
If the register 102 is forcibly set to the maximum value that the evaluation function can take at the first time, the value input via the signal line 98 at the first time will not be the minimum value.

This configuration has the advantage that the number of variable delay circuits in the memory section of FIG. 5 and the number of arithmetic sections connected thereto can be reduced.

Next, the operation of the arithmetic unit will be explained with reference to FIG. However, since the operations of the calculation units 92 to 94 are exactly the same, only the calculation unit 92 will be described. In addition, in the arithmetic unit 92, parallel processing is performed by the number of lines corresponding to the block size in the vertical direction (here, 4 lines are shown), so the signal line ₄₆₁ in FIG.
Only the system leading to No. 3 will be explained.

The current frame signal input from the signal line 45 ₁ and the shifted previous frame signal input via the signal line 46 ₁ are subtracted in the subtracter 110 ₁ , and the difference signal is given to the conversion circuit 111 ₁ . .
As already explained, the conversion circuit converts the absolute value of the input difference signal (the above di _{, j} ) into a signal with a smaller number of bits, that is, the above e _i , _j , which is accumulated in the accumulator 112 ₁ . However, the accumulator is used at the start of motion vector detection (if the configuration is to perform detection in multiple steps, at the start of each detection)
shall be cleared. When the above calculations are completed for all pixels in the block, the values of the accumulators 112 ₁ to 112 ₄ are read out and input to the adder 113, and the values are input to the signal lines 46 ₁ to 112 4 .
46 The calculation results of the four systems starting with ₄ are summed,
It is output to the signal line 95.

Next, the comparing section 100 will be explained with reference to FIG. Although FIG. 9 shows a case where the output signals of four arithmetic units and the shift control signals corresponding to each are input, the configuration can be made in the same manner even when the number of input signals is other.

First, the calculation results of the arithmetic unit input via signal lines 95 and 96 are sent to the comparator 120 and the multiplexer (hereinafter abbreviated as "MPX"), respectively.
122. The comparison section 120 is connected to the signal line 95
and the signal value on the signal line 96, and if the signal value on the signal line 95 is smaller, the MPX122
output the value of the signal line 95 to the signal line 135 through the signal line 125; otherwise, the value of the signal line 95 is output to the signal line 135.
Output the value of 6. On the other hand, the signal on signal line 125 is also connected to MPX132, and signal line 95
If the value of is smaller, connect signal line 9 to MPX132.
The shift control signal of the signal line 53 corresponding to the value of 5 is output to the signal line 137, otherwise the shift control signal of the signal line 53 is output to the signal line 9.
A shift control signal of the signal line 54 corresponding to the value of 6 is output.

Comparison section 121, MPX123 and MPX133
Exactly the same thing is done on the same day depending on the magnitude relationship of the values of signal lines 97 and 98.
The smaller value of 7 and 98 is output to signal line 136, and the shift control signal corresponding to the smaller value is output to signal line 138.

Further, the values output to the signal lines 135 and 136 are input to the comparator 124 and MPX 127,
If the value of signal line 135 is smaller, MPX1
34 to the shift control signal of signal line 137 to signal line 5
1, otherwise the signal line 138
output the shift control signal. Also, MPX1
27 outputs the smaller value of signal lines 135 and 136 to signal line 101.

As explained above, according to the present invention, a motion compensated interframe coding device is provided which is simpler than equation (1) and more efficient than equation (2), which has been conventionally used as an evaluation function for motion vector detection. It can be realized.

Although the present invention has been described in detail above when applied to "motion-compensated interframe coding," the input used in the present invention
The method of quantifying the degree of difference in level between the TV signal and the predicted signal and integrating it for pixels within a block to obtain an evaluation value is the already detailed "motion compensated interframe coding" (this method uses interframe adaptive prediction). 1
) as well as inter-field adaptive prediction, inter-frame/inter-field adaptive prediction, and inter-frame/inter-field adaptive prediction.
Of course, it is also possible to use it for intra-field adaptive prediction, etc., and it can be widely used as a means for selecting the optimal prediction signal in various adaptive predictive coding systems.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the motion vector detection method, FIG. 2 is a diagram showing an example of the characteristics of the conversion circuit necessary for the motion vector detection method in the present invention, and FIG. 3 is a diagram for explaining the motion vector detection method.
4 is a block diagram of an interframe encoding device showing an embodiment of the present invention, FIG. 4 is a block diagram showing an embodiment of the predicted signal generating section 11, and FIG. Block diagram showing one embodiment, No. 6
The figure is a block diagram showing an embodiment of the variable delay circuit 61 in FIG. 5, FIG. 7 is a block diagram showing an embodiment of the detector 43 in FIG. 4, and FIG. FIG. 9 is a block diagram showing one embodiment of the calculation section 92, and FIG. 9 is a block diagram showing one embodiment of the comparison section 100 in FIG. In the figure, 3...Delay circuit, 5...Subtractor, 7
... Quantizer, 9, 18 ... Encoder, 11 ... Prediction signal generation section, 14 ... Frame memory, 17 ...
. . . adder, 20 . . . multiplexer, 22 . . . buffer memory, respectively.

Claims (1)

[Claims] 1. A television that collects pixels obtained by sampling an input television signal to form a block, and predictively encodes the input television signal using one of a plurality of prediction signals generated for each block. means for converting the power of a difference signal between a pixel of the input television signal and a predicted signal into a numerical value using a number of bits smaller than the number of bits representing the input TV signal in the prediction encoding device;
means for integrating the numerical values for each of the plurality of prediction signals for the pixels in the block and outputting an evaluation value; and a prediction signal whose value is the smallest among the evaluation values obtained for the plurality of prediction signals. What is claimed is: 1. A television signal encoding apparatus, comprising: means for determining an optimal prediction signal; and adaptively selecting an optimal prediction signal to predictively encode the input television signal.