JPH01217268A - Measuring circuit - Google Patents

Abstract

PURPOSE:To automatically and efficiently measure the capacity of digital machinery such as a use ratio, by providing counter means for counting the generation number of the significant levels of an input digital signal, the max. time length, the min. time length and the total time length. CONSTITUTION:An input signal is inputted to a significant level time length counter 7, a significant level integrating time length counter 8 and a significant level number-of-generation counter 9 through a synchronous flip-flop 1 and count value generating AND gates 4-6. The output terminal of the counter 7 is connected to max. and min. value registers 12, 15 through comparators 10, 13. The outputs of said registers and the outputs of the counters 8, 9 are connected to a CPU 16, and a average value and a use ratio are calculated to be displayed on a display device 17. By this method, the capacity of digital machinery can be measured and observed with good accuracy.

Description

TECHNICAL FIELD The present invention relates to a measuring circuit, and more particularly to a measuring circuit for measuring the performance of a memory bus, a transfer bus, a CPU, etc. of a digital device.

Prior Art In conventional performance measurement circuits of this type, it is necessary to measure the waveform of a serial digital input signal at a significant level of 1" or "0". In this case, an oscilloscope or a digital logic analyzer with memory is used. This is used to observe the significant level time and find its maximum value, minimum value, average value, etc.This serial digital signal may be, for example, a transfer request signal in the transfer of input/output equipment, and this transfer The maximum, minimum, average value, etc. of the time length of the request signal are observed.

In the conventional observation method described above, in order to find the minimum value, maximum value, and average value, "'0'" and "'1" on the cathode ray tube are
In addition to requiring visual confirmation of the level signal and performing desk calculations, this method requires observation over a long period of time and has the drawbacks of poor observation accuracy.

OBJECTS OF THE INVENTION An object of the present invention is to provide a measuring circuit that can accurately, automatically, and efficiently measure the performance of digital equipment.

Structure of the Invention The measuring circuit according to the present invention detects two input serial digital signals.
a timer means for setting a time for observing a significant level among the value levels; a number counting means for counting the number of occurrences of the significant level within the observation time; and a maximum time of the significant level within the observation time. time length counting means for counting the maximum and minimum time lengths, respectively; total time length counting means for cumulatively counting the total time length of the significance level within the observation time; and an operation for dividing the total time length by the number of occurrences. means, and the calculation result of the calculation means and the maximum and minimum time lengths are visually displayed.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 (a,
) to (i) are waveforms of signals a to i of the circuit shown in FIG. In both countries, a serial digital signal to be observed becomes the data input of a D-type FF (flip-flop) 1, and a clock b from a clock signal generator 2 becomes a digital signal a synchronized with the clock b.

The timer circuit 3 generates a signal C that determines the measurement time, and the AND gate 5 is opened for a predetermined time (1), during which time the clock b is allowed to pass and is supplied to the AND gate 4. In the AND gate 4, the Q output hole of the FFI is sampled by the clock b, and the sampling result d is applied to the counters 7 and 8, respectively.

Counter 7 counts the sampling result d, and counts the Q of FF1.
The counting contents of the counter 7 are reset every time the output hole transitions from the "1" level to the "'0" level, so the counting contents of this counter 7 correspond to the time of the "1'° level of the digital input signal a. This means that the latest value e of the length is always shown. The counter 8 integrates the sampling result d to make a count of 4, and therefore indicates the total time length f of the digital input signal a at the ``1'' level within the measurement time (1).

On the other hand, the Q output hole of the FFI is ANDed with the output C of the timer circuit 3 by an AND gate 6, and this AND output is counted by a counter 9. That is, the counter 9 counts the number g of occurrences of the input signal a at the '1' degree level within the measurement time (1,).

The output e of the counter 7 is sent to the comparator 10 and the AND gate 11
The value is inputted to a maximum value counting circuit consisting of a register 12 and a register 12, and is compared with the contents of the register 12 by a comparator 10, and the larger value remains in the register 12. Therefore, register 12
The maximum time length of the "1'" level within the measurement time (1) is held.

The output e of the counter 7 is input to a minimum value counting circuit consisting of a comparator 13, an AND gate 14, and a register 15, and is compared with the contents of the register 15 by the comparator 13, and the smaller value is stored in the register 15. remain. Therefore, the minimum time length i of the "1" level within the measurement time (1) is held in the register 15.

The CPU 16 is an arithmetic circuit, and the above-mentioned components h.

i, f, and g are input, and the following calculation process is performed based on these measured values.

Average value of "1" level within measurement time (1) - "t'" level total time length (f > ÷ "1" level occurrence number (g)) In the specific numerical example in Figure 2, the above equation The value is 16/34=;
5.3, so the significance of the input digital signal is 1.
The average length of the level corresponds to the length of 5.3 clocks b. That is, if clock b is 100ns,
100 X5.3 = 530 TIIS, and if the measurement time is t = 10 sec, then ζ530/10,0
00) xlOO=5.3%, and the usage rate of 5.3% (the usage rate of the "1'" level of the serial digital signal) can be determined by the CPU 16, and this is displayed on the display 17. It is.

It is also obvious that the maximum time length 11 of the "1'' level, 7 and the minimum time length i=4 can be visually displayed on the display 17, respectively.

Effects of the Invention Like soft soil, according to the present invention, the number of occurrences, occurrence time, occurrence average value, maximum time length, minimum time length, usage rate, etc. of a significant level of an input digital signal can be automatically and accurately measured. This has the effect of making it possible to accurately measure the performance of digital equipment.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing signal waveforms at various parts of the circuit of FIG. 1. Explanation of symbols of main parts 2...Clock generator 3...Timer circuit 7...Significance level time length counter 8...
...Significance level cumulative time length counter 9...
Significant level occurrence count counter 10... Comparator 12... Maximum value register 13... Comparator 15... Minimum value register 16...・CPU

Claims (1)

[Claims] (1) a timer means for setting an observation time for a significant level among the binary levels of an input serial digital signal; a number counting means for counting the number of occurrences of the significant level within the observation time; time length counting means for counting the maximum time length and minimum time length of the significance level, respectively; total time length counting means for cumulatively counting the total time length of the significance level within the observation time; 1. A measuring circuit comprising: arithmetic means for dividing by the number of occurrences, and wherein the arithmetic results of the arithmetic means and the maximum and minimum time lengths are visually displayed.