JPH01215056A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the time of a design by a method wherein field-effect type transistors having different conductivity type are provided to two active layers, a CMOS circuit is constituted, blocks are assigned to the circuit by one functions, functional blocks are laminated, one functional blocks composed of the two active layers being a unit, so that a large functional block is organized. CONSTITUTION:An n channel MOSFET 2 is manufactured into an Si substrate, employing the Si substrate, etc., as an active layer 1, and a p channel MOSFET 4 is prepared into an active layer 3. These n channel MOSFET and p channel MOSFET are connected by a wiring 5, thus manufacturing a CMOS circuit. A CMOS.SRAM is constructed to the active layer 1 and an active layer 2 as functional blocks at that time. An n channel MOSFET 7 is prepared into an active layer 6 on the active layer 3, and a p channel MOSFET 9 is manufactured into an active layer 8 on the active layer 6. These both channel MOSFETs are connected by a wiring 10 and a CMOS circuit is constituted, and an arithmetic operation unit(ALU) is produced. Since the CMOS.SRAM and the CMOS ALU are connected by a wiring 11 at that time, a small-sized microprocessor is organized.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to semiconductor integrated circuits.

(Prior Art) Recently, in semiconductor circuits, semiconductor elements in which active layers including semiconductor elements are laminated, so-called three-dimensional circuit elements, have been proposed and prototyped. A typical example is the 1986 International Electron Devices Meeting Technical Digest (Int.
ernational Electron Device
esMeeting Technical Diges
t) There are papers published on pages 435 to 438. In this example, a 0MO8-SRAM is fabricated in one active layer, and a semiconductor circuit is fabricated in which two layers are laminated.

(Problem to be solved by the invention) In this circuit configuration, each of the two active layers has 0 MO8-
Since 8 RAM is arranged, 1 layer CMO 8-8 RAM
This requires about twice the period of the manufacturing process required in the previous example, and the process period becomes longer. Furthermore, there are other problems such as the number of masks being doubled.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for configuring a semiconductor circuit, which makes it possible to shorten the manufacturing process period and design time for a multilayered or stacked semiconductor element.

(Means for Solving the Problems) The present invention provides a semiconductor integrated circuit in which a plurality of active layers including semiconductor elements are laminated, in which a field effect transistor of a first conductivity is placed in a first semiconductor element active layer and a second One functional block is configured in a complementary semiconductor integrated circuit in which a conduction type field effect transistor is arranged on a second semiconductor element active layer laminated on the first semiconductor element active layer, and these This is a semiconductor integrated circuit characterized by sequentially stacking stacked functional blocks as units.

(Function) A p-channel transistor (or n-channel transistor) is placed in one active layer, an n-channel transistor (or p-channel transistor) is placed in the active layer above it, and these two active layers 0 using
When configuring the M08 circuit, masks for well formation ion implantation and channel doping ion implantation are not required, so the number of masks can be reduced compared to the example shown in the above-mentioned literature, and the period of the manufacturing process can also be shortened. Furthermore, if you construct one functional block within the same layer using the 0M08 circuit composed of two active layers, and then stack them to construct a larger functional block, it is possible to create a single functional block across multiple active layers. It is possible to reduce the time required for design compared to designing with one function.

(Example) Hereinafter, a detailed explanation will be given with reference to the example shown in FIG.

In FIG. 1, a Si substrate or the like is used as a first active layer 1, and an n-channel MO8FET 2 is fabricated therein. After that, using laser annealing technology and EB annealing technology, S
OI (8i1icon on In5ulator)
Using technology, p-channel MO8F in the second active layer 3
Create ET4. By connecting these n-channel MO8FET and P-channel MO8FET with wiring 5 made using selective tungsten CVD method, 0
Create the M08 circuit. At this time, the first active layer 1 and the second active layer 2 are provided with 0MO8- as the first functional block.
Configure SRAM. Next, an n-channel MO8FET 7 is fabricated in the third active layer 6 on the second active layer 3,
Further, a p-channel MO8FET 9 is fabricated in the fourth active layer 8 on the third active layer 6. Both these channels MO
0M0 by connecting 8FETs with wiring 10
Eight circuits are constructed, and an arithmetic operation unit (ALU) is created as the second functional block. , At this time, the first functional block CMO8/SRAM and the second functional block CM
Since the O8-ALU is connected by the wiring 11, two functional blocks, such as a small microprocessor, are configured.

In the embodiment of the present invention, the ALU and SRAM are designed to be formed in two active layers, so the ALU
Compared to designing an SRAM across four active layers, the complexity is reduced and the design can be completed in half or less time.

In the above embodiment, n-channel MO8FETs are used in the first and third active layers, and p-channel MO8FETs are used in the second and fourth active layers.
Although an O8FET has been placed, this may be reversed. Further, the field effect transistor may be other than MO8FET. Further, the material of the active layer may be a semiconductor other than Si.

(Effects of the Invention) As described above, by using the present invention, field effect transistors of different conductivity types are arranged in two active layers, a 0M08 circuit is configured by them, and a block is assigned to this circuit with one function. . After that, one functional block composed of two active layers is sequentially stacked,
Constitutes a large functional block. Using this method,
It is possible to shorten the manufacturing process period and design time of semiconductor elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...first active layer 2.7-n channel MO8FET 3...Second active layer 4.9...p channel MO8FET 5, 10.11...Wiring 6...Third active layer 8...Fourth active layer Kozo Iizuka, Director of the Institute of Industrial Science and Technology

Claims (1)

[Claims] (1) In a semiconductor integrated circuit in which a plurality of active layers including semiconductor elements are laminated, a field effect transistor of a first conductivity type is used as the first semiconductor element active layer, and a field effect transistor of the second conductivity type is used as the active layer of the first semiconductor element. Complementary semiconductor integrated circuits arranged on a second semiconductor element active layer stacked on a first semiconductor element active layer constitute one functional block, and these stacked functional blocks are used as a unit, A semiconductor integrated circuit characterized by successive stacking.