JPH02305471A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a ratio-type latch to be constituted at a gate array by a method wherein a resistive element is provided between the output terminal of a second inverter and the input terminal of a first inverter. CONSTITUTION:A resistive element 9 is provided between the input terminal of one of inverters 7a connected to an input transistor 6b and the output terminal of the other inverter 7a, and an inverter of small drive capacity is artificially formed in a part surrounded by a broken line. A resistor such as a resistor which makes both the ends of a transistor gate serve as their terminals, ON-resistance of the transistor, the resistance of the diffusion region of the transistor, or the like can be used as the resistive element 9. By this setup, an inverter small in drive capacity can be artificially constituted and a ratio- type latch can be formed in a semiconductor integrated circuit device provided with a gate array.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device having a CMOS gate array, and more particularly to a semiconductor integrated circuit device that can constitute a ratio type latch.

[Conventional technology]

FIG. 13 is a configuration diagram of a semiconductor integrated circuit device equipped with a gate array, and numeral 1 in the figure indicates a semiconductor chip. Input/output pads 2 are arranged on the periphery of the semiconductor chip 1.
A plurality of basic cell stages 3 are provided in the central part.

Figure 14 shows one basic cell stage 3 in Figure 13.
FIG. 15 is also an equivalent circuit diagram of the basic cell stage 3, and here, as an example of the basic cell stage 3, one of the gate separation type is shown. In the figure 6
a and 6b are a P-channel transistor and an N-channel transistor, respectively.

Each P-channel transistor 6a (N-channel transistor 6b) has a gate 5a (gate 5b), and a source and drain consisting of a P-type diffusion region 4a (N-type diffusion region 4b). The plurality of P-channel transistors and N-channel transistors are each connected in series.

In the basic cell stage 3 having such a configuration, the series connection of transistors is severed by turning off the transistor at the position to be separated, and a desired circuit is formed using the separated transistors.

By the way, when configuring a ratio type launch in a semiconductor integrated circuit device, a circuit as shown in FIG. 16 is generally used. In the figure, 6b is an N-channel transistor connected to the input terminal 8 of the ratio type latch, and 5b is its gate. The output terminal of the transistor 6b is connected to the input terminal of the inverter 7a, the input terminal of another inverter 7b is connected to the output terminal of the inverter 7a, and the output terminal of the inverter 7b and the input terminal of the inverter 7a are not connected. ing. Here, the inverter 7b is composed of a transistor whose driving ability is smaller than that of the inverter 7a.

The operation of the ratio type latch having such a configuration will be explained.

If transistor 6b is off, the inverter?
A and 7b form a loop circuit, and data is held by this loop circuit. For example, when the input of inverter 7a is O(1), the output of inverter 7a is 1 (0), and the input of inverter 7b is 1 (0).
(0), and the output of the inverter 7b becomes O(1). Here, since the output of the inverter 7b is the human power of the inverter 7a, the data is accurately held in this loop circuit.

When transistor 6b is on, the data applied to input terminal 8 overcomes the output of inverter 7b and is input to inverter 7a. As a result, the data applied to this input terminal 8 is held within the loop circuit using the same operating procedure. Once held, this data continues to be held even if transistor 6b is turned off.

As described above, in a typical semiconductor integrated circuit device, a ratio type latch is constructed using two types of transistors having different driving capacities.

[Problem to be solved by the invention]

In the gate array, N-channel transistors,
Since the size of each P-channel transistor is constant, it is not possible to obtain multiple types of transistors with different driving capabilities, and in a semiconductor integrated circuit device equipped with a gate array, it is not possible to configure a ratio type launch as described above. The problem is that it is not possible.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device that can configure a ratio type latch in a gate array.

[Means to solve the problem]

A semiconductor integrated circuit device of the present invention includes an input terminal of a first inverter connected to an input transistor;
A resistive element is provided between the second inverter and the output terminal of the second inverter connected in series.

[Effect]

In the semiconductor integrated circuit device of the present invention, a resistance element is connected to the output terminal of the second inverter. In this way, the second inverter has a pseudo driving capacity smaller than that of the first inverter.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 1 is a circuit diagram of a ratio type latch of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a circuit diagram representing the circuit shown in FIG. 1 at a transistor level. In the figures, the parts with the same numbers as in the conventional example (Figs. 13, 14, and 15) indicate the same parts. In FIG. 1, 6b is an input N-channel transistor, 5b is its gate, and 8 is an input terminal of a ratio type latch. 7a and 7a are inverters made up of transistors having the same driving ability, and between the input terminal of one inverter 7a connected to the transistor 6b and the output terminal of the other inverter 7a, A resistive element 9 is provided, and an inverter having a pseudo-low driving capacity is configured in the portion surrounded by the broken line. As the resistance element 9, a resistance whose terminals are both ends of the gate of a transistor, an on-resistance of a transistor, a resistance of a diffusion region of a transistor, or the like can be used.

FIG. 3 is a block diagram of an embodiment using a resistor at the gate of a transistor as a resistance element, and FIG. 4 is an equivalent circuit diagram of the configuration shown in FIG. 3. In the figure, 5 is a resistor formed by connecting six gate resistors in series, and is the same as the resistor element 9 in Figure 1.
is equivalent to In addition, 10.11 in the figure is a VDD wiring and a GND wiring, respectively, and these VDD wiring 10. G
ND wiring 11. Gates 5a, 5b.

Connection between the P-type diffusion region 4a and the N-type diffusion region 4b is made by a wiring 12 passing through a contact hole 13 formed in the gate 5a+ 5b+ diffusion region 4a, 4b.

In this example, six gate resistors are connected in series to constitute a resistor with a large resistance value, but the number of series connections may be adjusted depending on the required resistance value.

FIG. 5 is a block diagram of an embodiment using an on-resistance of a transistor as a resistance element, and FIG. 6 is an equivalent circuit diagram of the configuration shown in FIG. 5. In the example shown here, a resistor is formed by connecting in parallel three P-channel transistors 6a in the on state connected in series and three N-channel transistors 6b in the on state connected in series. is used as the resistance element 9. Note that the number of connected transistors used in the configuration of such a resistance element may be determined depending on the required resistance value.

FIG. 7 is a block diagram of another embodiment using the on-resistance of a transistor as a resistance element, and FIG. 8 is an equivalent circuit diagram of the configuration shown in FIG. 7. In the example shown here, a resistor formed by connecting three P-channel transistors 6a in series and three N-channel transistors 6b in series, connected in parallel, is used as the resistance element 9. ing. The gates of these six transistors are connected in common and are controlled by the output of the first stage inverter connected to the input transistor 6b.
Either the three P-channel transistors 6a or the three N-channel transistors 6b are turned on,
Acts as a resistive element. Note that the number of connected transistors constituting this resistance element may be determined depending on the required resistance value.

FIG. 9 is a block diagram of another embodiment using the on-resistance of a transistor as a resistance element, and FIG. 10 is an equivalent circuit diagram of the configuration shown in FIG. 9. In the example shown here, there are four P-channel transistors connected in series and four P-channel transistors connected in series.
An inverter with a small driving capacity is constructed using N-channel transistors. Either the three P-channel transistors or the three N-channel transistors in the output portion of this inverter are turned on, and constitute a resistance element based on the on-resistance of the transistor. Note that the number of connected transistors constituting this resistance element may be determined depending on the required resistance value.

FIG. 11 is a block diagram of an embodiment using a resistor in a diffusion region of a transistor as a resistance element, and FIG. 12 is an equivalent circuit diagram of the configuration shown in FIG. 11. In the figure, 4 is a resistor formed by connecting resistors in six diffusion regions 4a and 4b in series, and corresponds to the resistor element 9 in FIG. In this example, resistors in six diffusion regions are connected in series to form a resistor with a large resistance value, but the number of series connections may be adjusted depending on the required resistance value.

In all the embodiments described above, the N-channel transistor 6b is used as the input transistor connected to the input terminal 8 of the ratio latch, but the P-channel transistor 6a may also be used.

Also, when configuring a ratio-type lunch with multiple inputs,
It is sufficient to adopt a configuration in which a plurality of input transistors are provided as in the conventional case.

Furthermore, although a gate isolation type basic cell stage is used in this embodiment, an oxide film isolation type basic cell stage may be used instead.

〔Effect of the invention〕

As detailed above, in the present invention, since a resistance element is connected to the output terminal of one of the inverters, an inverter with a small driving capacity can be constructed in a condensed manner, and a ratio type latch can be used in a semiconductor integrated circuit device equipped with a gate array. Can be configured.

As a result, a circuit using a ratio type latch can also be mounted on the gate array.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a circuit diagram representing FIG. 1 at a transistor level, and FIGS. 3, 5, 7, and 9. FIG. 11 is a block diagram showing an embodiment of a semiconductor integrated circuit device of the present invention, and FIGS. 4, 6, 8, and 10. Fig. 12 is Fig. 3, Fig. 5, Fig. 7, and Fig. 9, respectively. Fig. 11 is an equivalent circuit diagram, Fig. 13 is a block diagram of a semiconductor integrated circuit device equipped with a gate array, Fig. 14 is a block diagram of a basic cell stage, and Fig. 15 is an equivalent circuit diagram of the basic cell stage shown in Fig. 14. Circuit diagram: FIG. 16 is a circuit diagram showing a conventional ratio type latch. l...Semiconductor knob 2...I/O pad 3...
・Basic cell stage 4a...P type diffusion region 4b・
...N-type diffusion region 4...Resistance 5a, 5b...
Gate 5...Resistor 6a...P channel transistor 6b...N channel transistor 7a...
・Inverter 8...Input terminal 9...Resistance element 1
0...VDD wiring 11...GND wiring 12...
Wiring 13: Contact hole In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device including a gate array, an input transistor, a first inverter having an input terminal connected to the source or drain of the transistor, and an input terminal connected to the output terminal of the first inverter. A semiconductor integrated circuit device comprising: a second inverter connected to the second inverter; and a resistance element provided between an output terminal of the second inverter and an input terminal of the first inverter.