JP3082772B2 - CMOS static memory cell - Google Patents

Description

The present invention relates to a CMOS static memory cell, and more particularly to a CMOS static memory cell.
The present invention relates to a CMOS static memory cell having a layered structure.

FIG. 4 is a circuit diagram of a CMOS static memory cell. As shown, the CMOS static memory cell is configured by a flip-flop circuit formed by load-type P-channel MOS transistors P1 and P2, driving N-channel MOS transistors N1 and N2, and transmission N-channel MOS transistors N3 and N4. ing. In order to form such a memory cell with a multi-layered structure, for example, as shown in FIG. 5, two N-channel MOS transistors N1 and N3 and one P-channel MOS transistor per memory cell are provided in the first layer. P1 is formed, and the digit line D1 and the word line W are arranged so as to be orthogonal. Next, in the second layer, two N-channel MOS transistors N2 and N4 and one P-channel
Conventionally, a method of forming the MOS transistor P2 and connecting the first and second layers with the contacts C9, C10 and C11 has been adopted (Japanese Patent Laid-Open No. 63-308372, "CMOS Static RA").
M "). Note that V in FIG. 4 represents a power supply level, G represents a ground level, and V1 and V2 in FIG. 5 represent power supply lines, and G1 and G2 represent ground lines.

[Problems to be Solved by the Invention] Since the conventional CMOS static RAM is configured as described above, MOs having the same function in each of the first layer and the second layer
S transistors (driving N-channel MOS transistors N1, N2, load-type P-channel MOS transistors P1, P2,
The transmission N-channel MOS transistors N3 and N4) are arranged, and there is a problem that a difference in transistor performance occurs due to manufacturing variations between the first layer and the second layer, and a desired function as a memory cell cannot be performed. . Further, since a P-channel MOS transistor and an N-channel MOS transistor are mixed in the first layer and the second layer, an extra area for PN separation is required, and a memory cell having a multilayer structure is used to reduce the cell area. There was a problem that the effect was not so large.

[Means for Solving the Problems] The CMOS static memory cell of the present invention improves the above disadvantage and arranges the same number of the same channel type MOS transistors on the first, second and third layers, respectively. It is composed of a group of MOS transistors having the same function.

The gist of the present invention is that a first inverter in which a first load type P-channel MOS transistor and a first driving N-channel MOS transistor are connected in series between a first power supply line and a second power supply line, and a second load type P-channel MOS transistor and second
A flip-flop in which a driving N-channel MOS transistor is cross-connected with a second inverter connected in series between the first power supply line and the second power supply line, and a common drain of the first inverter. And a second transmission N-channel MOS transistor connected to a common drain of the second inverter. The CMOS static memory cell comprising: a first transmission N-channel MOS transistor connected to a common drain of the second inverter; A first N-channel MOS transistor group including the first and second transmission N-channel MOS transistors is provided on a first layer which is a lower layer from the substrate side. The first and second driving N-channel MOS transistors are included in a second layer serving as an intermediate layer in the channel MOS transistor group. The second N-channel MOS transistor group is characterized in that the second N-channel MOS transistor group is formed by being sequentially stacked on a third layer which is an upper layer.

Further, the word line is formed in the first layer and connected to the first and second transmission N-channel MOS transistors, and the digit line is formed in the first layer through a contact hole. N-channel MOS for transmission 1
A first digit line is connected to the transistor, and a second digit line is connected to the second transmitting N-channel MOS transistor.

Further, in the above invention, two MOS transistors of the same conductivity type arranged in each layer are provided for the same purpose.

[Operation] In the CMOS static RAM of the present invention, the same number of the same channel type MOS transistors are arranged in the first layer, the second layer, and the third layer, respectively. it can. Do the same for each layer
By using the MOS transistor group, variations in MOS transistor performance can be minimized and desired memory cell performance can be exhibited.

Embodiment FIG. 1 is a three-dimensional schematic view of a CMOS static memory cell according to one embodiment of the present invention. In this embodiment, two driving N-channel MOS transistors N1 and N2 are formed for each memory cell in the first layer, and the entire first layer is covered with an insulating film.
The contacts C1 and C2 are formed.

Next, a second silicon single crystal layer is laminated, two load-type P-channel MOS transistors P1 and P2 are formed for each memory cell, and the entire second layer is covered with an insulating film. , C7 and C8 are formed.

Next, a third silicon single crystal layer is laminated and formed.
Two transmission N-channel MOS transistors N3 and N4 are formed for each memory cell. At this time, a word line W is arranged, the entire third layer is covered with an insulating film, contacts C5 and C6 are formed, and a digit line D1 is formed. , D2, and contacts for external electrode connection are formed to obtain a desired CMOS static RAM. In the figure, G is a ground level, and V is a power supply level.

FIG. 2 is a plan view of the CMOS static memory cell according to the present embodiment. In the figure, reference numeral 1 denotes a first driving diffusion layer, 2 denotes a gate for a load type P-channel MOS transistor and a driving N-channel MOS transistor, and 1 and 2 denote a first driving N-channel MOS transistor. Is formed. Reference numeral 3 denotes a second-layer silicon single crystal layer, and the second and third layers form a second-layer load-type P-channel MOS transistor. Reference numeral 4 denotes a third silicon single crystal layer, 5 denotes a word line, and 4 and 5 form a third transmission N-channel MOS transistor. C1 and C2 connect the driving diffusion layer 1 to the second silicon single crystal layer 3, and C3 and C4 denote the gates 2 and 3 for the load type P-channel MOS transistor and the driving N-channel MOS transistor. C5, 56 connects the third silicon single crystal layer 4 to the digit lines D1, D2, and C7, C8 connects the second silicon single crystal layer. The third and third silicon single crystal layers 4 are connected to each other.

FIG. 3 is a schematic perspective view of a CMOS static memory cell according to another embodiment of the present invention. In this embodiment, 1
Two transmission N-channel MOSs per memory cell on the layer
After forming the transistors N3 and N4 and forming the contacts C5 and C6, the word lines W and the digit lines D1 and D2 are formed.
And cover the entire first layer with an insulating film, and contact C3, C
Form 4.

Next, a second silicon single crystal layer is laminated, two load-type P-channel MOS transistors P1 and P2 are formed for each memory cell, and the entire second layer is covered with an insulating film. , C7 and C8 are formed.

Next, a third silicon single crystal layer is laminated and formed.
Two driving N-channel MOS transistors N1 and N2 are formed for each memory cell, the entire third layer is covered with an insulating film, and external electrode connection contacts are formed to obtain a desired CMOS static memory cell. In this embodiment, since the word lines W and the digit lines D1 and D2 are formed in the first layer, the word lines W and the digit lines D1 and D2 having a long wiring length can be formed in a substantially flat area where the steps are not severe. It is easy to manufacture and advantageous.

[Effects of the Invention] As described above, according to the present invention, the MOS transistors constituting one memory cell are equally arranged in the first, second and third layers, so that the cell area per memory cell is reduced. Thus, the degree of integration of the entire circuit can be increased. further,
By forming a MOS transistor group having the same function in each layer, variations in MOS transistor performance can be minimized, and desired memory cell performance can be exhibited. Of course, the above invention may use a polycrystalline silicon layer.

[Brief description of the drawings]

FIG. 1 is a three-dimensional schematic diagram of a CMOS static memory cell according to one embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a three-dimensional schematic diagram of a CMOS static memory cell according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a CMOS static memory cell, and FIG. 5 is a three-dimensional schematic diagram of a conventional example. N1, N2: N-channel MOS transistor for driving, N3, N4: N-channel MOS transistor for transmission, P1, P2: P-channel MOS transistor for load, D1, D2: digit line, W: word line, V: Power supply level, G: Ground level, C1 to C11: Contact, 1 ... Diffusion layer for driving, 2 ... Gate for load type PMOS transistor / NMOS transistor for driving, 3 ... Second layer silicon unit Crystal layer, 4... Third silicon single crystal layer, 5... Word line.

Claims (2)

(57) [Claims] A first load type P-channel MOS transistor and a first driving N-channel MOS transistor connected in series between a first power supply line and a second power supply line; A flip-flop in which a second inverter in which a channel MOS transistor and a second driving N-channel MOS transistor are connected in series between the first power supply line and the second power supply line is cross-connected; CMOS static memory cell, comprising: a first transmission N-channel MOS transistor connected to a common drain of the second inverter; and a second transmission N-channel MOS transistor connected to a common drain of the second inverter. A first N-channel MOS transistor group including the first and second transmission N-channel MOS transistors on a semiconductor substrate, The first layer of the layer, P including the first and second load type P-channel MOS transistor
A channel MOS transistor group is formed on a second layer serving as an intermediate layer, and a second N-channel MOS transistor group including the first and second driving N-channel MOS transistors is formed on a third layer serving as an upper layer, which is sequentially laminated. A CMOS static memory cell. 2. A first inverter having a first load type P-channel MOS transistor and a first driving N-channel MOS transistor connected in series between a first power supply line and a second power supply line, and a second load type P-channel MOS transistor. A flip-flop in which a second inverter in which a channel MOS transistor and a second driving N-channel MOS transistor are connected in series between the first power supply line and the second power supply line is cross-connected; Transmission N-channel MOS connected between the common drain and the first digit line
A CMOS static memory cell comprising: a transistor; and a second transmission N-channel MOS transistor connected between a common drain of the second inverter and a second digit line, wherein the first and second The transmission N-channel MOS transistor is formed in a lower first layer on a semiconductor substrate, and the first and second load-type P-channel MOS transistors are formed in a second layer above the first layer. The first and second driving N-channel MOS transistors are connected to the second
A word line formed in a third layer above the layer and gate-controlling the first and second transmission N-channel MOS transistors is formed in the first layer, and the first digit line and the second digit line are A CMOS static memory cell, wherein a first and a second are connected to the first and second transmitting N-channel MOS transistors formed in the first layer via a contact hole.