JPH01214145A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH01214145A
JPH01214145A JP63041179A JP4117988A JPH01214145A JP H01214145 A JPH01214145 A JP H01214145A JP 63041179 A JP63041179 A JP 63041179A JP 4117988 A JP4117988 A JP 4117988A JP H01214145 A JPH01214145 A JP H01214145A
Authority
JP
Japan
Prior art keywords
chip
eprom
integrated circuit
substrate
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63041179A
Other languages
Japanese (ja)
Inventor
Nobuo Fukuda
福田 信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63041179A priority Critical patent/JPH01214145A/en
Publication of JPH01214145A publication Critical patent/JPH01214145A/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To package in high density various chips of multiple function including an EPROM by coating and mounting the EPROM and a flip-chip with a soldering bump with a water-vaporproof insulating resin into an integrated structure. CONSTITUTION:The title hybrid integrated circuit device includes a laminate ceramic substrate 1 having therein a connecting conductor pattern, an EPROM chip 2 mounted on a principal surface thereof adjoining to said substrate, a flip-chip 3 with a soldering bump, a water-vaporproof insulating resin film 4 for coating the chip 2 excepting the top surface of a ultraviolet erasing window 4, a thin film resistor 6 placed on the other principal surface of the substrate 1, and an external connecting lead terminal 7. The EPROM 2 shares the substrate 1 between it and other chip parts (except for the window 4), and is coated with the film 5, thereby achieving high density and high function.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装でに関し、特にプログラムの書
き込み可能なE’FROMチップを搭載する混成集積回
路装置に関する′。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device equipped with a programmable E'FROM chip.

〔従来の技術〕[Conventional technology]

従来、混成集積回路装置は、プリント基板またはセラミ
ック基板上にパッケージ化された半導体チップと受動チ
ップ部品をそれぞれ搭載し接続して成るものであるが、
プログラム書込み用のROMチップを搭載する場合は、
プログラム変更の必要の無いときは書込み操作が1回の
み可能なワンタイムFROMチップを使い、また、プロ
グラム変更の必要が有るときは、紫外線による消去が可
能なEPROMチップが使われる。この際、電気的消去
可能なEEFROMは記憶容量がE P、ROMより小
さく高密度実装に不利なので一般には使われない、この
ようにプログラム書込み用のROMチップを搭載する場
合は、通常、ROMチップと他のチップとはそれぞれ別
基板に一旦搭載された後、改めて一つの共通基板上に集
められ載置される。
Conventionally, hybrid integrated circuit devices are made by mounting and connecting packaged semiconductor chips and passive chip components on printed circuit boards or ceramic substrates, respectively.
When installing a ROM chip for writing programs,
When there is no need to change the program, a one-time FROM chip that can be written to only once is used, and when it is necessary to change the program, an EPROM chip that can be erased by ultraviolet light is used. In this case, electrically erasable EEFROM is not generally used because it has a smaller storage capacity than EPROM and is disadvantageous for high-density packaging. The chips and other chips are once mounted on separate boards, and then collected and mounted on a single common board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、かかる手段で組立てられた従来の混成集
積回路装置は、組立作業が繁雑であるばかりでなく高密
度、高機能の回路装置を得ることが困難であり、また、
デバイス全体の大形化を避けることができない、従って
、電子機器の低価格化、小形化の要求に充分な対応がで
きないという欠点がある。
However, conventional hybrid integrated circuit devices assembled by such means not only require complicated assembly work, but also have difficulty in obtaining high-density, high-performance circuit devices.
This method has the disadvantage that it is impossible to avoid increasing the size of the entire device, and therefore, it is not possible to sufficiently meet the demands for lower cost and smaller size of electronic equipment.

本発明の目的は、上記の情況に鑑み、プログラムの書き
換え可能なEFROMを含む多機能の各種チップを高密
度に実装し得る混成集積回路装置を提供することである
SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a hybrid integrated circuit device in which various multifunctional chips including a programmable EFROM can be mounted at high density.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、混成集積回路装置は、紫外線により消
去されるプログラムの書き込み可能なEPROMチップ
と半田バンプを有するフリップ・チップとを少なくとも
搭載し、前記EPROMチップの紫外線消去用窓の上面
を除く全ての部分を耐湿性絶縁樹脂膜で被覆することを
含んで構成される。
According to the present invention, a hybrid integrated circuit device includes at least a programmable EPROM chip erased by ultraviolet rays and a flip chip having solder bumps, except for the upper surface of the ultraviolet ray erasing window of the EPROM chip. The structure includes covering all parts with a moisture-resistant insulating resin film.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示す混成集櫃回路装πの断
面図である0本実施例によれば、本発明の混成集積回路
装置は、内部に接続層導体パターンを有する一つの積層
セラミック基板1と、接層セラミック基板1の一つの主
面上に隣接して搭載されるプログラムの書き換え可能な
EPROMチ、ツブ2および半田バンプを有するフリッ
プ・チップ3と、E P ROMチップ2の紫外線消去
用窓4の上面を除く全ての部分を被覆する耐湿性絶縁樹
脂(例えばエポキシ樹脂)膜5と、積層セラミック基板
1の他の一つの主面上に載置され内部の接続導体パター
ンを介しプログラムの書き換え可能なEPROMチップ
2または半田バンプを有するフリップ・チップ3と電気
接続される薄膜抵抗6と、外部接続リード端子7とを含
む、ここで、8はフリップ・チップ3を保護するシリコ
ーン・プリコート材である0本実施例から明らかなよう
に、本発明の混成集積回路装置は、プログラムの書き換
え可能なEPROMチップ2はその紫外線消去用窓4の
上面を除き、他のチップ部分と共に一つの積層セラミッ
ク基板1を共用して耐湿性絶縁樹脂膜5で被覆され梧截
されるので、高密度。
FIG. 1 is a sectional view of a hybrid integrated circuit device according to an embodiment of the invention. A multilayer ceramic substrate 1, a flip chip 3 having a rewritable programmable EPROM chip, a knob 2 and a solder bump mounted adjacently on one main surface of the contact layer ceramic substrate 1, and an EPROM chip 2. A moisture-resistant insulating resin (e.g., epoxy resin) film 5 covering all parts except the top surface of the ultraviolet erasing window 4, and an internal connecting conductor pattern placed on the other main surface of the laminated ceramic substrate 1. a thin film resistor 6 electrically connected to the programmable EPROM chip 2 or a flip chip 3 having solder bumps through the wafer and an external connection lead terminal 7, where 8 protects the flip chip 3; As is clear from this embodiment, in the hybrid integrated circuit device of the present invention, the programmable EPROM chip 2 is made of silicone pre-coated material, and the programmable EPROM chip 2 is made of silicone pre-coated material. Since a single laminated ceramic substrate 1 is shared and coated with a moisture-resistant insulating resin film 5, the density is high.

高機能を容易に実現することができる。上記実施例の構
造はつぎの手法によって容易に製造される。
High functionality can be easily achieved. The structure of the above embodiment can be easily manufactured by the following method.

第2図(a)〜(b)は上記実施例の製造方法を示す一
工程順序図である。まず、第2図(a)に示すように、
裏面に薄膜抵抗体を形成し、また、接続導体用パターン
9を内部に有する積層セラミック基板1の一生面上に第
1の怒光性ポリイミド材を塗布し乾燥する9次に、所定
のパターンに露光、エツチングして不要なポリイミド材
を除去する。ついで、このポリイミド材を乾燥硬化して
10μm厚の第1のポリイミド膜10を得、更に薄膜導
体を第1の、ポリイミド膜10上にスパッタリング法で
成膜する。同様に、これを所定のパターンに露光、エツ
チングして、例えば、フリップ・チップ3の搭載用の薄
膜導体パターン11を形成し、これを第2のポリイミド
膜12で選択的に被覆してフリップ・チップ3F載用の
電極13のみを露出せしめる。この作業はEPROMチ
ップ2の搭載面についても同様に行われる9次に第2図
(b)に示すように、裏面の薄膜抵抗体を所定値までレ
ーザートリミングして薄膜抵抗6を形成した後、搭載す
べきチップ2および3の搭載面上のそれぞれの所定位置
に半田クリームをそれぞれ塗布し、紫外線消去用窓4を
有するリードレスチップキャリアに納められたEPRO
M2および半田バンプ14を形成したフリップチップ3
をそれぞれのf5g1面上の所定位置に載置する。ここ
で基板1を温度150℃のホット・プレートで予備加熱
した後、更に温度230℃のホット・プレートで半田を
加熱し溶融して各チップ部分をそれぞれ半田接続する。
FIGS. 2(a) to 2(b) are one-step flowcharts showing the manufacturing method of the above embodiment. First, as shown in Figure 2(a),
A first photosensitive polyimide material is coated on the first surface of the multilayer ceramic substrate 1, which has a thin film resistor formed on the back surface and a connection conductor pattern 9 inside, and is dried.Next, a predetermined pattern is formed Remove unnecessary polyimide material by exposure and etching. Next, this polyimide material is dried and cured to obtain a first polyimide film 10 having a thickness of 10 μm, and a thin film conductor is further formed on the first polyimide film 10 by a sputtering method. Similarly, this is exposed and etched into a predetermined pattern to form, for example, a thin film conductor pattern 11 for mounting the flip chip 3, and this is selectively covered with a second polyimide film 12 to form a flip chip. Only the electrode 13 for mounting the chip 3F is exposed. This work is similarly performed on the mounting surface of the EPROM chip 2.Next, as shown in FIG. 2(b), after laser trimming the thin film resistor on the back surface to a predetermined value to form the thin film resistor 6 Solder cream is applied to each predetermined position on the mounting surface of the chips 2 and 3 to be mounted, and the EPRO is housed in a leadless chip carrier having an ultraviolet erasing window 4.
Flip chip 3 with M2 and solder bumps 14 formed thereon
is placed at a predetermined position on each f5g1 surface. Here, after the substrate 1 is preheated on a hot plate at a temperature of 150° C., the solder is further heated and melted on a hot plate at a temperature of 230° C., and each chip portion is connected by soldering.

ついで、基板周辺の端子にリード・フレームをレーザー
半田付法で接続し、フリップ・チップ3を応力緩和用の
シリコーン・プリコート材8で被覆した後、EPROM
チップ2の紫外線消去用窓4の部分のみを遮蔽したうえ
、例えばエポキシ樹脂5で成形外装する。i&後にリー
ド・フレームを成形して外部接続リード端子7を形成す
れば、紫外線消去用窓のみを露出した本発明の高密度、
高機能混成集積回路装置を得ることができる。
Next, the lead frame is connected to the terminals around the board by laser soldering, and the flip chip 3 is coated with a silicone precoat material 8 for stress relaxation, and then the EPROM is
Only the ultraviolet ray erasing window 4 of the chip 2 is shielded and then molded and exteriorized with, for example, epoxy resin 5. i & After forming the lead frame and forming the external connection lead terminal 7, the high density of the present invention with only the ultraviolet erasing window exposed;
A highly functional hybrid integrated circuit device can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、一つの基
板を共用して紫外線消去用窓を有するパッケージに納め
られたEPROMと半田バンプを有するフリップ・チッ
プその他のチップ部品とを耐湿性絶縁樹脂膜で一体化構
造に被覆搭載することができるので、書き換え可能なE
FROMを搭載した高密度・高機能の混成集積回路装置
を容易に提供することができる。
As described in detail above, according to the present invention, an EPROM housed in a package having an ultraviolet erasing window and a flip chip and other chip components having solder bumps are insulated with moisture resistance and shared on one substrate. Since it can be coated and mounted on an integrated structure with a resin film, rewritable E
A high-density, high-performance hybrid integrated circuit device equipped with FROM can be easily provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す混成集積回路装置の断
面図、第2図(a)〜(b)は上記、実施例の製造方法
を示す一工程順序図である。 1・・・頂層セラミック基板、2・・・プログラムの書
き換え可能なEPROMチップ、3・・・半田バンプを
有するフリップ・チップ、4・・・紫外線消去用窓、5
・・・耐湿性絶縁樹脂膜(エポキシ樹脂)、6・・・薄
膜抵抗、7・・・外部接・続リード端子、8・・°シリ
コーン・プリコート材、9・・・f8統用導体パターン
、10・・・第1のポリイミド膜、11・・・薄膜導体
パターン、12・・・第2のポリイミド膜、13・・・
フリップ・チップ搭載用の電極、14・・・半田バンプ
FIG. 1 is a cross-sectional view of a hybrid integrated circuit device showing one embodiment of the present invention, and FIGS. 2(a) to 2(b) are one-step sequential diagrams showing the manufacturing method of the above-mentioned embodiment. DESCRIPTION OF SYMBOLS 1... Top layer ceramic substrate, 2... Programmable EPROM chip, 3... Flip chip having solder bumps, 4... Window for ultraviolet erasure, 5
...Moisture-resistant insulating resin film (epoxy resin), 6...Thin film resistor, 7...External connection/connection lead terminal, 8...° silicone precoat material, 9...F8 common conductor pattern, DESCRIPTION OF SYMBOLS 10... First polyimide film, 11... Thin film conductor pattern, 12... Second polyimide film, 13...
Electrode for flip chip mounting, 14...Solder bump.

Claims (1)

【特許請求の範囲】[Claims] 紫外線により消去されるプログラムの書き込み可能なE
PROMチップと半田バンプを有するフリップ・チップ
とを少なくとも搭載し、前記EPROMチップの紫外線
消去用窓の上面を除く全ての部分を耐湿性絶縁樹脂膜で
被覆することを特徴とする混成集積回路装置。
Program-writable E that is erased by ultraviolet light
1. A hybrid integrated circuit device comprising at least a PROM chip and a flip chip having solder bumps, and wherein all parts of the EPROM chip except for the top surface of an ultraviolet erasing window are covered with a moisture-resistant insulating resin film.
JP63041179A 1988-02-23 1988-02-23 Hybrid integrated circuit device Pending JPH01214145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63041179A JPH01214145A (en) 1988-02-23 1988-02-23 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63041179A JPH01214145A (en) 1988-02-23 1988-02-23 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH01214145A true JPH01214145A (en) 1989-08-28

Family

ID=12601204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63041179A Pending JPH01214145A (en) 1988-02-23 1988-02-23 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH01214145A (en)

Similar Documents

Publication Publication Date Title
JP2790122B2 (en) Laminated circuit board
US7198984B2 (en) Semiconductor device and method of manufacture thereof, circuit board and electronic instrument
US7266888B2 (en) Method for fabricating a warpage-preventive circuit board
JPH08111433A (en) Semiconductor device and tape for producing semiconductor device
US8302277B2 (en) Module and manufacturing method thereof
JP2001156246A (en) Mounting structure and mounting method for integrated circuit chip
US6576998B1 (en) Thin semiconductor package with semiconductor chip and electronic discrete device
US9613894B2 (en) Electronic package
JPS6139741B2 (en)
JPH08274575A (en) Composite element mount circuit board
JP2004165193A (en) Semiconductor device and its manufacturing method
JP2002134662A (en) Chip type semiconductor device and its manufacturing method
JPH01214145A (en) Hybrid integrated circuit device
JPH05211256A (en) Semiconductor device
JP3423174B2 (en) Chip-on-board mounting structure and method of manufacturing the same
JP3841135B2 (en) Semiconductor device, circuit board and electronic equipment
JPH09148482A (en) Semiconductor device
JP2841825B2 (en) Hybrid integrated circuit
KR100417854B1 (en) chip scale package and method of fabricating the same
JPS63244631A (en) Manufacture of hybrid integrated circuit device
JP2989271B2 (en) Bare chip mounting board, method of manufacturing bare chip mounting board, and method of forming electrodes of bare chip
JP2841822B2 (en) Manufacturing method of hybrid integrated circuit
JPH1012810A (en) Semiconductor device
JP2589358B2 (en) Double-sided mounting TAB tape carrier
KR20030086192A (en) An improved wire-bonded chip on board package