JPH01209494A - Xy matrix display device - Google Patents

Abstract

PURPOSE:To easily and automatically select and output an external clock in different modes, an internal clock which is adapted to an external synchronizing signal, and an internal synchronizing signal by selecting a pair of the internal clock and internal synchronizing signal generated by a timing signal generating circuit according to the decision outputs of polarity deciding circuits. CONSTITUTION:The timing signal generating circuit is so constituted as to generate internal clocks and internal synchronizing signals. Then polarity deciding circuits 57 and 58 are provided which decide the polarities of horizontal and vertical synchronizing signals constituting an external synchronizing signal. A pair of an internal clock and an internal synchronizing signal generated by the timing signal generating circuit are selected according to the decision outputs of the polarity deciding circuits 57 and 58. Consequently, internal clocks and internal synchronizing signals adapted to the external clock and external synchronizing signal in different modes are selected and outputted easily and automatically without alternating the timing signal generating circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an XY matrix display device suitable for use in plasma display devices, electroluminescence display devices, electrochemical display devices, liquid crystal display devices, and the like.

[Summary of the invention]

A first aspect of the present invention is an XY matrix display device and its XY matrix display device.
It has a drive circuit that drives the matrix display, and a timing signal generation circuit that receives external display data, an external clock, and a four-head synchronization signal, and generates internal display data, an internal clock, and an internal synchronization signal to be supplied to the drive circuit. In the XY matrix display device, the timing signal generation circuit is configured to generate multiple sets of internal clocks and internal synchronization signals, and a polarity determination circuit is configured to determine the polarity of the horizontal and vertical synchronization signals that constitute the external synchronization signal. By selecting the set of the internal clock and internal synchronization signal generated from the timing signal generation circuit based on the discrimination output of the polarity discrimination circuit, the timing signal generation circuit can be configured without changing the circuit of the timing signal generation circuit. It is possible to easily automatically select and output internal clocks and internal synchronization signals that are adapted to different external clocks and external synchronization signals, respectively.

The second invention is an XY matrix display device and its XY matrix display device.
X having a drive circuit that drives a matrix display, and a timing signal generation circuit that receives external display data, an external clock, and an external synchronization signal and generates internal display data, an internal clock, and an internal synchronization signal to be supplied to the drive circuit.
On the Y matrix display device, the timing signal generation circuit includes a memory storing a plurality of sets of internal clocks and internal synchronization signals, and an external clock that is re-centered by an external synchronization signal and has a frequency higher than that of the external synchronization signal. It has an address counter that generates an address signal that is counted and supplied to the memory, and a polarity discrimination circuit that discriminates the polarity of the horizontal and vertical synchronization signals that constitute the external synchronization signal, and based on the discrimination output of the polarity discrimination circuit. By selecting a set of internal clocks and internal synchronization signals to be read from the memory, the circuit can be simplified and the mounting area can be reduced. Furthermore, it is possible to automatically select and output internal clocks and internal synchronization signals that are adapted to different external clocks and external synchronization signals, respectively.

[Conventional technology]

A conventional plasma display device that is suitable for the present invention will be described below.

First, a plasma display panel used in a plasma display device will be described with reference to FIG.

There are two types of plasma display panels: AC type and DC type.
The plasma display panel shown in FIG. 3 is of a DC type.

In Figure 3, FGP is a transparent rectangular front glass plate,
RGP is a rectangular rear glass plate, each having a thickness of several mm, facing each other at a predetermined interval, and the periphery thereof is hermetically sealed. The airtight space formed by the front glass plate FGP and the rear glass plate RGP is filled with a mixed gas of Ne gas and Ar gas at a pressure of several hundred or 200 to 450 Torr.

On the front glass plate FGP, thin strip-shaped anodes (X electrodes) A are deposited in parallel at predetermined intervals, and barrier ribs BR are deposited between adjacent anodes A in parallel thereto. There is. This barrier rib BR has a thickness that is sufficiently larger than the thickness of the anode A.

Further, on the rear glass plate RGP, several sheet-like trigger electrodes TG are attached, each corresponding to a predetermined number of cathodes, which will be described later. An insulating layer (dielectric layer) IL is deposited on the trigger electrode TG.

Then, on this insulating layer IL, a strip-shaped cathode (Y electrode) K is perpendicular to the anode 8, and is arranged at a predetermined interval (barrier rib B).
They are deposited in parallel with each other at a predetermined interval, facing each other with a distance equal to the thickness of R (100 to 200 μm).

Trigger electrode TG is connected to this, cathode K and anode A.
This is provided to cause a trigger discharge (a kind of AC type discharge) between the anode A and the cathode, and use this as a pilot flame to quickly start the discharge between the anode A and the cathode, thereby improving the contrast of the display. .

Next, a conventional 16-gradation type plasma display device using a plasma display panel as described with reference to FIG. 3 will be described with reference to FIG. 4. (1) shows the plasma display panel explained in FIG. 3, and illustration of the trigger electrode is omitted here. This plasma display panel (
1), 400 cathodes K(1) to K(400)
and 640 anodes A(1) to A(640) are arranged so as to be orthogonal to each other, and a discharge cell (2) is formed at each intersection. Note that the number of cathodes may be 480 in some cases.

First, the timing signal generation circuit (22) will be explained. This timing signal generation circuit (22) is composed of a logic IC. This timing signal generation circuit (22) receives display data DT from the microcomputer to which this plasma display device is connected as a CRT control signal to an input terminal (23) as shown in FIGS. 5 and 6. A 21 MHz dot clock DCK is input to the input terminal (24), a 25 kHz horizontal synchronizing signal plane is input to the input terminal (25), and a 60 Hz vertical synchronizing signal ■ is input to the input terminal (26). Based on these input signals, various output signals (timing signals) as shown in FIGS. 5 and 6 are formed and output, and supplied to a drive circuit (20) to be described later.

Next, various output signals outputted from this timing signal generation circuit (22) -h- will be explained. In Fig. 5, as input signals, horizontal synchronization signal plane, dot clock D
CK and display data DT are shown, and an output signal created based on these horizontal synchronization signal planes and dot clock DCK, that is, a horizontal frequency latch clock LCK.
, horizontal frequency clear signal CLh and horizontal frequency 15
A double frequency gray scale clock GCK is shown.

FIG. 6 also shows a vertical synchronizing signal (2), a horizontal synchronizing signal plane, and display data DT as input signals, as well as an output signal created based on this vertical synchronizing signal (2) and a horizontal synchronizing signal plane, That is, a clear signal CLV of a vertical frequency, a shift data plane and a trigger pulse clock of a vertical frequency, a cathode clock having a frequency of 1/2 of the horizontal frequency, and an output enable signal OE are shown, respectively. Although not shown in FIG. 6, the timing signal generation circuit (
22).

Next, returning to FIG. 4, the drive circuit (20) will be explained. This drive circuit (20) is composed of an IC. First, a cathode example circuit will be described. (3) is a serial-in/parallel-out shift register, which is composed of first and second serial-in/parallel-out shift registers of 200 bits for odd-numbered and even-numbered cathodes, respectively. The first and second shift registers of this shift register (3) are supplied with a group of shift data from the input terminal (4) and shift data having a (1/2) horizontal period phase different from this group, respectively. At the same time, the cathode clock π and its inverted clock are separately supplied from the input terminal (5), and the shifted data plane and its (1/2) horizontal period phase are changed by this clock and its inverted clock. The shift data for each are shifted respectively.

(6) is a cathode driver, which is composed of first and 20th cathode drivers for odd-numbered and even-numbered cathodes. Then, 200 cathode scanning pulses per vertical period, each sequentially shifted by a predetermined phase, from the first and second shift registers of the shift register (3) are sent as switching control signals to the high-withstand pressure sword driver ( 6) each of the first and second cathode drivers 2
00 on/off switches. Then, by this cathode driver (6), cathodes K(1) to
K (400) is sequentially and cyclically grounded. Further, the output enable signal OE from the output terminal (27) and its inverted signal are supplied to the first and second cathode drivers of the cathode driver (6), respectively.

Next, the anode side circuit will be explained.

(7) is a 640-byte (=640x4 bits) serial-in/parallel-out shift register.

From the input terminal (8) to this shift register (7),
Display data DT of 4 bits, that is, 16 gradations is supplied, and a 21 MHz dot clock DCK is supplied as a data shift clock SCK from the input terminal (9), and the display data DT is shifted by this clock SCK. .

The 640x4 bit parallel data from the shift register (7) is supplied to the latch circuit (10) and input terminal (
It is latched every horizontal period by the launch clock LCK from 11).

In this way, the 640 x 4 bit parallel data from the child circuit (10) is transferred to the pulse width modulation circuit (17) consisting of the pulse width counter (15) and the pulse width comparison circuit (14).
is supplied to its pulse width comparison circuit (14). This pulse width comparison circuit (14) includes 640 pulse generators. A gray scale clock GCK is supplied to the pulse width counter (15) from an input terminal (16).

Pulse width counter (15) and pulse width comparison circuit (14)
) is supplied with a clear pulse CLh from an input terminal (21). Then, the pulse width counter (15) is cleared by this clear pulse CLh, and each pulse generator of the pulse width comparison circuit (14) is cleared by the clear pulse CLh.
Set by h.

The anode driver (12) is supplied with the clear pulse CLV from the input terminal (21), and during its high level period, each switch of the anode driver (12) is is selectively turned on.

Then, the 4-bit pulse width code signal (gray scale data) output from the pulse width counter (15) is supplied to the pulse width comparison circuit (14), and the 640 4-bit pulse width code signals from the launch circuit (10) are is compared with the displayed data. And 640 of the pulse width comparison circuit (14)
Pulses are obtained from selected ones of the 1[1i1 pulse generators, which are selectively supplied as switching control signals to corresponding ones of the 640 on-off switches of the high voltage anode driver (12). . and,
Approximately O1, 2, ..., 15 times the unit time equal to the gray clock GCK period according to the data of 16 gradations (including O) of the 640-dot pulse within the horizontal period. Anode A (1) for a time corresponding to the pulse width
A voltage of 200 μ is selectively supplied to ~A (640).

(18) is a trigger electrode drive circuit, which has an input terminal (
19), a trigger pulse 7 is supplied, a trigger electrode control signal is generated here, and this trigger electrode control signal is supplied to a trigger electrode TG (not shown).

Next, referring to FIG. 7, the timing signal generation circuit (22) of the conventional plasma display device described in FIG. 4 will be described. First, the signal generating section (37) will be explained. (33) is a counter which is counted by the clock CK and is reset by the horizontal synchronization signal plane supplied to the input terminal (25) of the timing signal generation circuit (22) in FIG. Clock CK is the fourth
The input terminal of the timing signal side tan circuit (22) in the figure (
24) The dot clock DCK (its frequency is fck) (Fig. 5) itself or the dot clock DCK supplied to
...) is the clock obtained by frequency division.

The count output (parallel data of predetermined bits) of this counter (33) is, for example, the latch clock LCK, clear signal CLh, and gray scale clock G shown in FIG.
A signal generator (34A) with the same configuration that generates CK etc.
34B), .

Next, there is a signal generator (3) that generates the rough clock LCK.
4A), its configuration will be explained as a representative.

The count output from the counter (33) is sent to the data comparator (4).
1a), (4l b).

(43a) and (43b> are reference value data generators, respectively;
Generates a plurality of reference value data according to differences in frequency, phase, etc. of the clock CK1 supplied to the counter (33), the horizontal synchronization signal port, and the latch clock LCK output from the signal generator (34A). , each selector (42
After being selected by a) and (42b), it is supplied to data comparators (41a) and (4lb).

Then, the data comparators (41a) and (4lb) output the count output of the counter (33) and the selector (42a), respectively.
, (42b) are compared with the reference value data from the reference value data generators (43a), (43b), and each matching signal is sent to the launch circuits (44a), (44b).
) are supplied to the set input terminal and reset input terminal of the RS flip-flop circuit (45), respectively. Then, the flip-flop circuit (45) outputs a rough clock LCK.

Similarly, a clear signal CLh, gray scale clock GCK, etc. are output from the signal generator (34B) and the like.

Next, the signal generator (38) will be explained.

(35) is a counter, which is counted by the clock CK2 and also by the timing signal generation circuit (
22) Vertical synchronization signal supplied to the input terminal (26)
is reset by Clock CK2 is a horizontal synchronization signal plane (its frequency is rh) supplied to the input terminal (25) of the timing signal control circuit (22) in FIG.
(FIGS. 5 and 6) This is a clock obtained by multiplying the clock itself or its horizontal synchronization signal plane by a multiplication ratio M (M=2.3.4, . . . ).

The count output (parallel data of predetermined bits) of this counter (35) is, for example, the clear signal CL in FIG.
v A signal generator (36A) having the same configuration as the signal generator (34), which generates a 1-shift data clock, a cathode clock, its inverted clock, an output enable signal OB, its inverted signal, a trigger pulse clock, etc. ,...
・Supplied to etc.

Furthermore, the display data DT input to the input terminal (23) of the timing signal generation circuit (22) in FIG.
M (31), and it is also written to the signal generator (
After being read out in timing with each clock and each synchronization signal output from (37) and (38), these display data, each clock, and each synchronization signal are sent to the drive circuit (20) in Fig. 4. Supplied. Note that writing and reading of the RAM (31) are controlled by a memory control circuit, and an address signal is supplied thereto. Then, the drive circuit (20) drives the plasma display (1) shown in FIG.
is driven to perform display based on the above-mentioned display data DT.

[Problem to be solved by the invention]

In the conventional plasma display device described above, when the external clock and the external synchronization signal are different, the signal generation section (37) that constitutes the timing signal generation circuit (22) is adjusted accordingly.
, (38) reference data generators (43a), (43b)
A plurality of reference data from the data selector (42
A) and (42b) require manual switching, which is cumbersome to operate.

Further, in the conventional plasma display device described above, the signal generating sections (37) and (38) of the timing signal generating circuit (22) are
) is composed of logic rc, the timing signal generation circuit (22) becomes complex and its mounting area becomes large.

In view of the above, the first aspect of the present invention is to easily automatically generate an internal clock and an internal synchronization signal that are adapted to an external clock and an external synchronization signal of different types without changing the timing signal generation circuit. This paper attempts to propose an XY matrix display device that can selectively output images.

Further, the second invention aims at simplifying the circuit and reducing the mounting area, and also easily adapts to different types of external clocks and external synchronization signals without changing the timing signal generation circuit. This paper attempts to propose an XY matrix display device that can automatically select and output an internal clock and an internal synchronization signal.

[Means to solve the problem]

A first aspect of the present invention is an XY matrix display (1) and a drive circuit (1) for driving the XY matrix display (1).
20) and a timing signal generation circuit (22) that receives external display data, an external clock, and an external synchronization signal and generates external display data, an internal clock, and an internal synchronization signal to be supplied to the drive circuit (20). In the matrix display device, the timing signal generation circuit (22) is configured to generate a plurality of sets of internal clocks and internal synchronization signals, and also has a polarity that determines the polarity of the horizontal and vertical synchronization signals that form the base of the external synchronization signal. Discrimination circuit (57),
(58) is provided, and its polarity discrimination circuit (57), (58)
Based on the discrimination output of the timing signal generation circuit (22
), a set of internal clocks and internal synchronization signals generated from the internal clock signal is selected.

The second invention provides an XY matrix display (1) and a drive circuit (1) for driving the XY matrix display (1).
20) and a timing signal generation circuit (22) that receives external display data, an external clock, and an external synchronization signal and generates external display data, an internal clock, and an internal synchronization signal to be supplied to the drive circuit (20). In a matrix display device, a timing signal generation circuit (22) is reset by a memory (51), (52) in which a plurality of sets of internal clocks and internal synchronization signals are stored, and an external synchronization signal, and is reset by an external synchronization signal. The horizontal and It has polarity discrimination circuits (57) and (58) for discriminating the polarity of the vertical synchronization signal, and based on the discrimination output of the polarity discrimination circuits (57) and (58), data from the memories (51) and (52) is provided. The set of internal clock and internal synchronization signal to be read is selected.

[Effect]

According to the first invention, the timing signal generation circuit (22
) outputs an internal clock and internal synchronization signal. Furthermore, a set of internal clock and internal synchronization signal generated from the timing signal generation circuit (22) is selected based on the discrimination outputs of the polarity discrimination circuits (57) and (58). and,
This internal clock and internal synchronization signal are supplied to the drive circuit (20) together with the internal display data.
0), the XY matrix display (1) is driven to perform display based on this internal display data.

Further, according to the second invention, the address counter (33)
, (35) are reset by an external synchronization signal and counted by an external clock having a higher frequency than the frequency of the external synchronization signal, and the address signals from the address counters (33), (35) are counted by the memory (5).
1), (52), and based on that, the memory
An internal clock and an internal synchronization signal are output from (51) and (52). Also, based on the discrimination outputs of the polarity discrimination circuits (57) and (58), the set of internal clock and internal synchronization signal read out from the memories (51) and (52) is selected. Then, the internal clock and internal synchronization signal of q are supplied to the drive circuit (20) together with the internal display data,
The drive circuit (2o) drives the XY matrix display (1) to perform display based on this internal display data.

〔Example〕

An embodiment in which the present invention is applied to a plasma display device will be described below with reference to FIG. This embodiment differs from the conventional example shown in FIG. 7 only in the configuration of the timing signal generation circuit (22), and the other configurations are the same as those in FIGS. 3 and 4, so a description thereof will be omitted. do.

The configuration of the timing signal generation circuit of this embodiment will be explained below with reference to FIG. First, the signal generating section (37) will be explained.

(33) is a counter similar to that shown in FIG. 7 (here, it functions as an address counter), which is a clock CK,
and is reset by the horizontal synchronization signal plane supplied to the input terminal (25) of the timing signal generation circuit (22) in FIG. Clock CK,
The input terminal (
24) The dot clock DCK (its frequency is fck) (Fig. 5) supplied to
,...). In this case, the frequency fck/N needs to be higher than the frequency of the horizontal synchronization signal plane.

The count output (parallel data of predetermined bits) of this counter (33) is, for example, the latch clock LCK, clear signal CLh, and gray scale clock G shown in FIG.
ROM (RAM is also possible) in which CK etc. are stored (51
) as an address signal. This ROM (
51), its reading is controlled by a memory control circuit (56).

In addition, the clock CK supplied to the counter (33),
The latch clock LCK, clear signal CLh, etc. output from the horizontal synchronization signal surface and signal generator (37), depending on the difference in frequency, phase, etc. of the latch clock LCK, clear signal CLh, clay scale clock GCK, etc.
, grayscale clock GCK, etc., with different frequencies, phases, etc., are stored in the ROM (51), and are supplied to the memory control circuit (56) as manually adjusted control signals CTL, and horizontal signals as described later. The address counter (33) of the ROM (51)
The address from which data is read is changed based on the address signal from.

Lunch clock LCK, clear signal CLh, gray scale clock G read from this ROM (51)
CK and the like are supplied to a drive circuit (20) similar to that shown in FIG. 4 via a latch circuit (54).

Next, the signal generator (38) will be explained.

(35) is a counter similar to that shown in FIG. 7 (here it functions as an address counter), which is counted by the clock CK2 and is connected to the input terminal (26) of the timing signal generation circuit (22) in FIG. It is reset by the supplied vertical synchronization signal ■. The clock CK2 is connected to the input terminal (2) of the timing signal control circuit (22) in FIG.
5) The horizontal synchronization signal plane (its frequency is fh) (Figs. 5 and 6) itself or the horizontal synchronization signal plane supplied to the multiplication ratio M (however, M = 2.3.4, ...)
This is the clock obtained by multiplying by . This clock CK
2 may be obtained from the outside, but here it is obtained from the ROM (51) as will be described later.

The count output (parallel data of predetermined bits) of this counter (35) is, for example, the clear signal CL in FIG.
The ROM (RAM
(52) as an address signal. Reading from this ROM (52) is controlled by the above-mentioned memory control circuit (56).

In addition, with the clock CK2 supplied to the counter (35), the vertical synchronizing signal ■, the clear signal pressure ■ output from the signal generator (38), the shift data surface, and the cathode clock,
its inverted clock, output enable signal OE,
Depending on the difference in frequency, phase, etc. of the inverted signal, trigger pulse, etc., the clear signal CLV, shift data plane, cathode clock, the inverted clock, the output enable signal OE, the inverted signal, the trigger Multiple types of pulses with different frequencies, phases, etc.
It is stored in the ROM (52) and the memory control circuit (5
6), a manually adjusted control signal CTL, and a polarity determination circuit (57) for horizontal and vertical synchronization signals, which will be described later.
, (58), ROM (52
) The address from which data is read is changed based on the address signal from the address counter (35).

Clear signal CLV read from this ROM (52)
% Shift data plane, cathode clock, its inverted clock, output enable signal OE, its inverted signal, trigger pulse reservation, etc. are supplied to a drive circuit (20) similar to that shown in FIG. 4 through a launch circuit (55). .

The polarity discrimination circuits (57) and (58) for discriminating the polarity of the horizontal and vertical synchronization signals described above have the same configuration, and include an inverter (59), an integrator circuit at the subsequent stage [resistor (61), and capacitor (62)]. (60) and an inverter (63) at the subsequent stage.

From these polarity discrimination circuits (57) and (58),
A discrimination output of "1" or "0" is obtained depending on the polarity of the horizontal and vertical synchronization signals, and these discrimination outputs are sent to the memory control circuit (
56).

An example of the relationship between the number of pixels in one frame of display data supplied from the microcomputer to the timing signal generation circuit and the polarities of the horizontal and vertical synchronization signals is as follows.
As shown in the figure, if the polarities of the horizontal and vertical synchronizing signals are determined by the polarity determining circuits (57) and (58), the number of pixels in one frame at that time is uniquely determined. Therefore, the memory (51),
By changing the addresses addressed by the address counters (33) and (35) of (52), memory (51)
), the latch clock LCK, clear signal CLh, gray scale clock GCK, etc. with different frequencies and phases are automatically selected and read out, and the clear signal CLV stored in the memory (52) is automatically selected and read out. , the shift data plane, the cathode clock C1, its inverted clock, the output enable signal OE, its inverted signal, the trigger pulse clock, etc., which have different frequencies, phases, etc. can be automatically selected and read out.

Furthermore, a plurality of types of signals multiplied by M (M=1.2.3, . . . ) of the horizontal synchronization signal plane (FIGS. 5 and 6) are stored in the ROM (51). Then, the switching control signal is stored in the RQM (52). ROM(
The switching control signal CTL2 read from the memory control circuit (52) and obtained through the launch circuit (55) is sent to the memory control circuit (56).
), and based on this, the address of the memory (51) addressed by the counter (33) is changed, and the M (however, M=1.2.3...) A multiplied signal is selected. Then, a signal multiplied by M of the horizontal synchronizing signal surface read from the ROM (51) and output from the latch circuit (54) is supplied to the counter (35) as the clock CK2. The timing of switching M is when the shift data surface of the vertical period supplied to the shift register (3) arrives or after a predetermined time delay, and the switching is performed once or multiple times in one vertical period. is possible.

For example, 640 x 350 display data from a microcomputer (the number of horizontal synchronization signals within one vertical period is 4)
00 pieces) as shown in Figure 6.
When displaying on a plasma display panel (1) having 00 cells (2), if you want to display the display screen based on the display data at the top and bottom center of the plasma display panel (1), please refer to Figure 1. Using the embodiment, the frequency of the cathode clock signal supplied to the shift register (3) of the cathode example is multiplied by the horizontal frequency for a predetermined time (20 cathodes) after the arrival of the shift register data surface of the vertical frequency. , for example, by 4 to 5 times as much as the so-called blank feed), after which the horizontal frequency is set for a predetermined time (350 cathodes), and then the horizontal frequency is set for a predetermined time (20 cathodes) before the next vertical frequency shift register data arrives. Main purpose) Multiply the horizontal frequency, for example, by 4 to 5 times.

Note that the display data DT is output as is as internal display data DT through the transmission line LN.

In the timing signal generation circuit of the embodiment shown in FIG. 1, a counter (
33) and (35) and two ROMs (51) and (52), but one counter and one
It can also be configured with several ROMs.

In that case, the counter is counted by the clock CK, and the timing signal generation circuit (2) shown in FIG.
2) is reset by the vertical synchronizing signal (2) supplied to the input terminal (26). The synchronization signal and clock to be stored in the above-mentioned memories (51) and (52) are stored in this memory.

In the above embodiment, the timing signal generation circuit (2
2) includes memories (51), (52), address counters (33), (35), and polarity determination circuit (57), (
58), but the following configuration is also possible.

That is, the polarity discrimination circuits (57) and (58) similar to that shown in FIG. 1 are added to the conventional timing signal generation circuit shown in FIG.
The polarity determining circuits (57) and (58) determine the polarity of the horizontal and vertical synchronizing signals constituting the external synchronizing signal, and the signal generating section (37)
) of the signal generators (34A), (34B), . . . and the signal generators (36A), . A plurality of reference value data from the data generators (43a), (43b) are selected, and thereby the signal generators (34A), (34B), . . . of the signal generator (37) are selected.
- and the signal generator (36A) of the signal generator (38), -
・Select the set of internal clock and internal synchronization signal output from . For other configurations and operation descriptions, the description of the embodiment shown in FIG. 1 is referred to.

〔Effect of the invention〕

According to the first aspect of the present invention described above, it is possible to automatically generate an internal clock and an internal synchronization signal that are adapted to external clocks and external synchronization signals of different types easily without changing the timing signal generation circuit. An XY matrix display device capable of selectively outputting can be obtained.

Further, according to the second aspect of the present invention, the circuit is simplified and the mounting area is reduced, and the external clock and external synchronization signal of different formats can be easily used without changing the timing signal generation circuit. An XY matrix display device capable of automatically selecting and outputting an appropriate internal clock and internal synchronization signal can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, particularly the timing signal generation circuit, FIG. 2 is a table showing the characteristics of the synchronization signal, and FIG. 3 is a plasma display device used in a conventional plasma display device. FIG. 4 is a block diagram showing a conventional plasma display device, FIG. 5 and FIG. 6 are timing charts for explaining the operation of the conventional plasma display device, and FIG. 7 is a diagram showing the conventional plasma display device. FIG. 2 is a block diagram showing a timing signal generation circuit of a plasma display device. (1) is a plasma display panel, (20) is a drive circuit, (
22) is a timing signal generation circuit, (33), (35)
, (57) are address counters, (50), (5
1) and (52) are ROMs, respectively, and 57) and (58) are polarity discrimination circuits, respectively.

Claims (1)

[Claims] 1. An XY matrix display, a drive circuit that drives the XY matrix display, and internal display data that receives external display data, an external clock, and an external synchronization signal and supplies the drive circuit; In an XY matrix display device having an internal clock and a timing signal generation circuit that generates an internal synchronization signal, the timing signal generation circuit is configured to generate a plurality of sets of the internal clock and the internal synchronization signal, and the A polarity discrimination circuit is provided for discriminating the polarity of the horizontal and vertical synchronization signals constituting the external synchronization signal, and based on the discrimination output of the polarity discrimination circuit, the internal clock and the internal synchronization signal generated from the timing signal generation circuit are An XY matrix display device characterized in that a group can be selected. 2. An XY matrix display, a drive circuit that drives the XY matrix display, and internal display data, an internal clock, and an internal synchronization signal that receive external display data, an external clock, and an external synchronization signal and supply them to the drive circuit. In the XY matrix display device, the timing signal generation circuit includes a memory storing a plurality of sets of the internal clock and the internal synchronization signal, and is reset by the external synchronization signal. an address counter that generates an address signal counted by the external clock having a frequency higher than the frequency of the external synchronization signal and supplied to the memory; and a polarity that determines the polarity of the horizontal and vertical synchronization signals that constitute the external synchronization signal. An XY matrix display device comprising: a discrimination circuit, and a set of the internal clock and the internal synchronization signal to be read from the memory is selected based on the discrimination output of the polarity discrimination circuit.