JPH03163586A - Circuit for generating picture element clock signal of matrix display device - Google Patents

Abstract

PURPOSE:To eliminate the dissidence of the timing of picture element clock signals by specifying a supplied computer graphics signal and generating the clock signals of the repetitive frequencies of the picture element clock signals. CONSTITUTION:The mode of the supplied computer graphics signal is decided in a decision circuit 2 by the polarities, etc., of the horizontal scanning period and horizontal synchronizing signals in the computer graphics signal having no picture element clock signals to specify the supplied computer graphics signal. The clock signals of the repetitive frequencies of the picture element clock signals which the computer graphics signal corresponding to the specified mode is ought to have are generated in clock generating circuits 3, 9 and the phases of the generated clock signals are adjusted. The signals are then supplied to a signal driver 21 of a matrix display device 23. The dissidence of the timing of the picture element signal and the timing of the picture element clock signals is eliminated in this way and the images having the good image quality are obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pixel clock signal generation circuit for a matrix display device. (Prior Art) Cathode ray tubes have been commonly used as display devices for displaying images, including television receivers, but in recent years, liquid crystals have been used as display devices. Devices using the same matrix display elements have come into widespread use, and matrix display devices have also come to be used to display images on television receivers and personal computers. (Problem to be Solved by the Invention) By the way, there is no unified standard for personal computer display devices, and therefore, for example, when looking at the horizontal deflection frequency (horizontal scanning frequency), some types of personal computer display devices have a ．．
While a frequency value of 75 KHz is adopted, other models of personal computer display devices use a frequency value of 21.85 KHz, or 3
Various companies have adopted various frequency values such as 1.47 KHz, and this point is due to the vertical deflection frequency (vertical scanning frequency).
, signal polarity, and others. In a display device using a cathode ray tube, horizontal deflection and vertical deflection of the electron beam are performed in accordance with the horizontal scanning standard and vertical scanning standard of the image signal being displayed. Since images can be displayed using discrete image signals on the time axis or continuous image signals on the time axis, it has traditionally been possible to vary the horizontal and vertical deflection frequencies over a wide frequency range. By using a deflection circuit with
It is well known that display devices that could be shared by many types of personal computer display devices were provided and commonly used. However, in a display device configured using a matrix display element, the two-dimensional pixel array of the matrix display element is The scan start timing in the row direction and the scan start timing in the column direction are determined correctly, and pixel signals that exist discretely on the time axis in the image signal are correctly determined by successive pixels in the matrix display element. Images cannot be displayed correctly unless a pixel clock capable of displaying them is used. Therefore, when trying to display an image using a matrix display device using a computer graphics signal that does not have a pixel clock signal, Also, the timing of sequential pixel signals in a computer graphics signal,
The problem is that it is difficult to obtain images of good quality due to the discrepancy between the timing of the pixel clock signal in the matrix display device, which is set completely unrelated to the timing of the sequential pixel signals in the computer graphics signal mentioned above. (Means for Solving the Problems) The present invention is a pixel clock signal generation circuit for a matrix display device that displays an image using a computer graphics signal that does not have a pixel clock signal,
A signal mode determining means for determining the mode of the supplied computer graphics signal, and a pixel clock defined in correspondence with the computer graphics signal in the signal mode specified by the signal mode determining means. A matrix comprising a clock signal generating means for generating a clock signal having a repetition frequency of the signal, and a means for adjusting the phase of the clock signal generated from the clock signal generating means and supplying it to a signal driver of a matrix display device. A pixel clock signal generation circuit for a display device, and a pixel clock signal generation circuit for a matrix display device that displays an image using a computer graphics signal that does not have a pixel clock signal, the supplied computer graphics a signal mode determining means for determining the mode of a pixel clock signal; A first clock signal generation circuit including a phase-locked groove operating in synchronization with a pixel signal in an input computer graphics signal, which is to be provided to generate the first clock signal, and the input computer・
A second clock signal generation circuit includes a phase-locked loop that operates in synchronization with a horizontal synchronization signal in the graphics signal, and detects a no-signal state of a pixel signal in the input computer graphics signal. The output signal from the second clock signal generation circuit is outputted when the pixel signal in the input computer graphics signal is in a no-signal state using the no-signal detection means and the output signal of the no-signal detection means described above. The output signal from the first clock signal generation circuit and the second clock signal generation circuit are
and means for adjusting the phase of the clock signal output from the clock signal switching means and supplying it to the signal driver of the matrix display device. This paper provides a pixel clock signal generation circuit for a matrix display device. (Function) The mode of the supplied computer graphics signal is determined based on the horizontal scanning period of the computer graphics signal that does not have a pixel clock signal, the polarity of the horizontal synchronization signal, etc. Identify the graphics signal. A clock signal having a repetition frequency of a pixel clock signal that a computer graphics signal corresponding to the specified mode should have is generated, and the phase of the generated clock signal is adjusted to provide a signal driver of a matrix display device. Supply. Further, in order to generate a clock signal having the repetition frequency of the pixel clock signal described above, a clock signal including a phase-locked loop operating in synchronization with the pixel signal in the input computer graphics signal is used. A second clock signal generation circuit includes a first clock signal generation circuit and a phase-locked loop that operates in synchronization with a horizontal synchronization signal in an input computer graphics signal. A circuit is provided to detect the no-signal state of pixel signals in the input computer graphics signal and detect the input computer graphics signal.
The output signal from the first clock signal generation circuit and the second clock signal generation circuit are arranged in such a manner that the output signal from the second clock signal generation circuit is output when the pixel signal in the graphics signal is in a no-signal state. The output clock signal is switched and outputted, and the phase of the output clock signal is adjusted and supplied to the signal driver of the matrix display device. (Example) Hereinafter, specific contents of the pixel clock signal generation circuit of the matrix display device of the present invention will be explained in detail with reference to the attached drawings. FIG. 1 is a block diagram showing a schematic structure of a pixel clock signal generation circuit of a matrix display device of the present invention, and FIG. 2 explains the difference in modes of computer graphics signals that do not have a pixel clock signal. This is a diagram for In FIG. 1, 1 is a connector to which a signal from a personal computer is supplied, 2 is a mode determination circuit, 3 and 9 are clock signal generation circuits having the repetition frequency of the pixel clock signal, and 4.10 is a circuit for generating a clock signal at the repetition frequency of the pixel clock signal. 15 is a changeover switch; 16 is a no-signal detection circuit; 17.
20 is a monostable multivibrator, 21 is a signal driver, 22 is a horizontal scanning circuit, and 23 is a matrix display device. The matrix display device 23 may be any kind of matrix display device, for example, a matrix display device using a matrix display element using liquid crystal, and the image signal supplied to the signal driver. Sequential pixel signals are given in the column direction of the matrix display device 23 by pixel clock signals, and sequential horizontal synchronizing signals S are given by the horizontal scanning circuit 22.
Matrix display l for every h! By selecting the sequential construction operations in 23, images corresponding to the image signals supplied to the signal driver 21 are displayed on the matrix display device 23.
It has a well-known structure as shown in . The image signal among the output signals of the personal computer supplied to the connector 1 is supplied to the signal driver 21, the no-signal detection circuit 16, and the clock signal generation circuit 3 having the repetition frequency of the pixel clock signal. , the horizontal synchronizing signal sh, the vertical synchronizing signal Sv, etc. are applied to a computer graphics signal mode determining circuit 2, a clock signal generating circuit 9 having the repetition frequency of the pixel clock signal, and a horizontal scanning circuit 22. The above-described no-signal detection circuit 16 generates an output signal corresponding to the presence or absence of a pixel signal in the image signal, and supplies it to the changeover switch 15 as a changeover control signal. The output signal outputted from the no-signal detection circuit 16 corresponding to the state where there is no pixel signal in the image signal is sent to the changeover switch 15.
Switching the movable contact a to the fixed contact C side, the clock signal generated by the clock signal generation circuit 9 having the repetition frequency of the pixel clock signal is monostable via the fixed contact C and the movable contact a of the changeover switch l5. The output signal output from the no-signal detection circuit 16 is supplied to the multi-vibrator 17, and the output signal corresponding to the presence of a pixel signal in the copying signal is supplied to the movable contact a of the changeover switch 15. By switching to the fixed contact b side, the clock signal generated by the clock signal generation circuit 3 having the repetition frequency of the pixel clock signal is transferred to the monostable multipibrator 17 via the fixed contact b and the movable contact a of the changeover switch l5. Make sure that it is supplied. The computer graphics signal mode determination circuit 2 determines the mode of the computer graphics signal based on the horizontal scanning frequency fh, vertical scanning period, polarity of the synchronization signal, etc. in the computer graphics signal, and operates according to the determination result. The generated signal is supplied as a switching control signal to the changeover switches 5 and 11 provided in the frequency determining circuits 4 and 10 in the clock signal generation circuits 3 and 9 at the repetition frequency of the pixel clock signal. That is, the horizontal scanning frequency value, vertical scanning frequency value, polarity of the synchronizing signal, etc. in the computer graphics signal vary depending on the mode of the computer graphics signal, as illustrated in FIG. For example, focusing on the horizontal scanning frequency value in the input computer graphics signal, if it is 15.75 KHz, the mode determination circuit 2 determines that the input computer graphics signal If the signal is determined to be in CGA mode, and the horizontal scanning frequency value in the input computer graphics signal is, for example, 31.47 KHz, the mode determination circuit 2 determines that the input computer graphics signal is in VGA mode. It can be determined that there is. If the mode determination circuit 2 determines that the input computer graphics signal is in the CGA mode, for example, the signal generated according to the determination result is transmitted to the pixel clock signal by repeating the pixel clock signal. Changeover switches 5 and 1 provided in the frequency determination circuit 4 and 10 in the frequency clock signal generation circuits 3 and 9
A clock signal with a repetition frequency corresponding to the repetition frequency of the pixel clock of the image signal in the computer graphics mode of the CGA mode is supplied as a switching control signal of the pixel clock signal. , 9, the selector switch 5 provided in the frequency determining circuit 4, 10 thereof.
. The generated signal is supplied as a switching control signal to a changeover switch 5.11 provided in a frequency determination circuit 4, 10 in a clock signal generation circuit 3.9 having a repetition frequency of a pixel clock signal. A clock signal generating circuit 3 whose repetition frequency corresponds to the repetition frequency of the pixel clock of the image signal in the VGA mode computer graphics signal is a clock signal having the repetition frequency of the pixel clock signal;
9, its frequency determining circuit 4, 10
This allows the changeover switches 5 and 11 provided inside to be changed over. In the mode determination circuit 2 illustrated in FIG.
2a is a horizontal scanning frequency identification circuit. 2b is a synchronization signal polarity determination circuit. The clock signal generation circuits 3 and 9 having the repetition frequency of the pixel clock signal described above each include a phase-locked loop, and the frequency determination circuits 4 and 10 are provided in the phase-locked loop. This determines the center oscillation frequency of the voltage controlled oscillator. 6 to 8 in the frequency determining circuit 4 and the frequency determining circuit 10
12 to 14 inside are capacitors. The clock signal generating circuit 3 having the repetition frequency of the pixel clock signal synchronizes the phase-locked loop with the rising edge (or falling edge) of the pixel signal of the image signal in the computer graphics signal. A clock signal having a repetition frequency of the pixel clock signal synchronized with the pixel signal of the image signal is outputted and supplied to the fixed contact b of the changeover switch 15. The clock signal generating circuit 9 having the repetition frequency of the pixel clock signal described above synchronizes the phase-locked loop according to the rising edge (or falling edge) of the horizontal synchronizing signal in the computer graphics signal. A clock signal with a repetition frequency of the pixel clock signal synchronized with the horizontal synchronization signal in the horizontal synchronization signal is output and supplied to the fixed contact C of the changeover switch 15.By the way, the above-mentioned circuit for generating a clock signal with the repetition frequency of the pixel clock signal 3 and 9 each output a clock signal with the repetition frequency of the pixel clock signal, and as is clear from the above, they are synchronized with the pixel signal in the computer graphics signal. The clock signal generated from the clock signal generation circuit 3 having the repetition frequency of the pixel clock signal is synchronized with the horizontal synchronization signal in the computer graphics signal. It can be said that it is more suitable as a clock signal for the i1 element than the clock signal generated from the false generation circuit 9. However, the computer
A pixel signal is not always present in the graphics signal, and there are periods in which there is no pixel signal, but naturally the repetition frequency of the pixel clock signal is The clock signal having the repetition frequency of the pixel clock signal output from the clock signal generation circuit 3 has a poor synchronization relationship with the pixel signal. So, depending on whether there is a pixel signal in the computer graphics signal, the no-signal detection circuit l6
The movable contact a of the changeover switch 15 is switched to the fixed contacts b and c by the signal output from the switch 15, and when a pixel signal is present in the computer graphics signal, The clock signal at the repetition frequency of the pixel clock signal supplied from the clock signal generation circuit 3 at the repetition frequency of the pixel clock signal is transferred from the changeover switch 15 to the monostable multipiper l.
7, and when there is no pixel signal in the computer graphics signal, the clock signal is supplied to the fixed contact C from the clock signal generating circuit 9 at the repetition frequency of the pixel clock signal. The clock signal of the repetition frequency of the pixel clock signal is selected by the changeover switch 15.
is applied to the monostable multiviprator 17. The monostable multivibrator 17 described above closes the capacitor 1 every time the clock signal supplied to it from the changeover switch 15 is given as a trigger pulse.
8 and a variable resistor 19, and outputs an output pulse whose pulse width is determined by a time constant determined by a variable resistor 19. After the pulse, a monostable multivibrator 20 is triggered with a green signal. The monostable multiviprator 20 then outputs an output pulse with a constant pulse width and supplies it to the signal driver 21 as a pixel clock signal. Therefore, the variable resistor 19 in the monostable multivibrator 17 described above
By adjusting , the phase of the pixel clock signal supplied to the signal driver 21 can be adjusted. (
Effects of the Invention) As is clear from the above detailed explanation, the pixel clock signal generation circuit of the matrix display device of the present invention can control the horizontal scanning period and horizontal The mode of the supplied computer graphics signal is determined based on the polarity of the synchronization signal, etc., the supplied computer graphics signal is specified, and the computer graphics signal corresponding to the specified mode is determined. generate a clock signal with the repetition frequency of the pixel clock signal that should be the same, adjust the phase of the generated clock signal, and supply it to the signal driver of the matrix display device; A first clock signal generation circuit configured to include a phase-locked loop that operates in synchronization with a pixel signal in the input computer graphics signal to generate the signal, and the input computer graphics signal. Two clock signal generation circuits are provided, including a second clock signal generation circuit that includes a phase-locked groove that operates in synchronization with a horizontal synchronization signal in the signal, and input computer graphics. A second clock signal generating circuit is configured to detect a no-signal state of a pixel signal in the input computer graphics signal, and output an output signal from the second clock signal generation circuit when the pixel signal in the input computer graphics signal is in a no-signal state. The output signal from the first clock signal generation circuit and the output signal from the second clock signal generation circuit are switched and outputted, and the phase of the output clock signal is adjusted to the signal driver of the matrix display device. Since the pixel clock signal generation circuit of the matrix display device of the present invention has the same repetition frequency as the pixel clock repetition frequency of the image signal in the input computer graphics signal, and A clock signal adjusted to have the same phase as the pixel clock of an image signal in a computer graphics signal can be easily supplied to the signal driver. This eliminates the possibility of deterioration in image quality, such as thinner or darker lines in the reproduced image, due to interference due to a phase shift of the pixel clock of the image signal in the input computer graphics signal. According to the present invention, the clock signal generation circuit is switched according to the content of the image signal in the computer graphics signal, and an operation can be performed to always obtain an appropriate reproduced image.According to the present invention, the pixel When trying to display an image using a matrix display device using a computer graphics signal that does not have a clock signal, the timing of sequential pixel signals in the computer graphics signal and the computer
This solves the conventional problem that it was difficult to obtain images of good quality due to the mismatch with the timing of pixel clock signals in matrix display devices, which are set completely unrelated to the timing of sequential pixel signals in graphics signals. Solvable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a pixel clock signal generation circuit of a matrix display device of the present invention, and FIG. 2 is a block diagram for explaining the difference in mode of a computer graphics signal that does not have a pixel clock signal. This is a diagram.

Claims (1)

[Claims] 1. A pixel clock signal generation circuit for a matrix display device that displays an image using a computer graphics signal that does not have a pixel clock signal, the circuit comprising: A signal mode determining means for determining the mode, and generating a clock signal having a repetition frequency of a pixel clock signal determined in correspondence with the computer graphics signal of the signal mode specified by the signal mode determining means. A pixel clock signal generation circuit for a matrix display device, comprising a clock signal generation means for generating a clock signal, and a means for adjusting the phase of a clock signal generated from the clock signal generation means and supplying the adjusted clock signal to a signal driver of the matrix display device. 2. An input computer signal as a clock signal generating means for generating a clock signal having a repetition frequency of a pixel clock signal determined in correspondence with a computer graphics signal in a signal mode specified by the signal mode determining means. 2. The pixel clock signal generating circuit 3 of a matrix display device according to claim 1, which includes a phase-locked loop that operates in synchronization with a pixel signal in a graphics signal. As a clock signal generating means for generating a clock signal having a repetition frequency of a pixel clock signal determined in correspondence with a computer graphics signal of a specified signal mode, the horizontal synchronization signal in the input computer graphics signal is A pixel clock signal generation circuit 4 for a matrix display device according to claim 1, which uses a circuit including a phase-locked loop that operates synchronously, and a computer graphics signal having no pixel clock signal. A pixel clock signal generation circuit for a matrix display device that displays an image by means of a signal mode determination means for determining the mode of a supplied computer graphics signal, and to be provided for generating a clock signal with a repetition frequency of a pixel clock signal defined in correspondence with a computer graphics signal in a signal mode;
A first clock signal generation circuit configured to include a phase-locked loop that operates in synchronization with a pixel signal in the input computer graphics signal and a horizontal synchronization signal in the input computer graphics signal. a second clock signal generation circuit configured to include a phase-locked loop that operates as a clock signal; a no-signal detection means for detecting a no-signal state of a pixel signal in an input computer graphics signal; The first clock signal generation circuit uses the output signal of the signal detection means so that the output signal from the second clock signal generation circuit is output when the pixel signal in the input computer graphics signal is in a no-signal state. A clock signal switching means for switching between an output signal from the circuit and an output signal from a second clock signal generation circuit, and a signal driver for a matrix display device by adjusting the phase of the clock signal output from the clock signal switching means. A pixel clock signal generation circuit for a matrix display device, comprising means for supplying a pixel clock signal to a matrix display device.