JPH01206693A - Wiring of printed board - Google Patents

Wiring of printed board

Info

Publication number
JPH01206693A
JPH01206693A JP3204288A JP3204288A JPH01206693A JP H01206693 A JPH01206693 A JP H01206693A JP 3204288 A JP3204288 A JP 3204288A JP 3204288 A JP3204288 A JP 3204288A JP H01206693 A JPH01206693 A JP H01206693A
Authority
JP
Japan
Prior art keywords
wiring
channel
channels
width
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3204288A
Other languages
Japanese (ja)
Inventor
Shoji Ueda
正二 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3204288A priority Critical patent/JPH01206693A/en
Publication of JPH01206693A publication Critical patent/JPH01206693A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits

Abstract

PURPOSE:To enable required wirings even if channels differ remarkably from each other in a wiring density by a method wherein channels are varied in width and a wiring density inside a channel is partially changed. CONSTITUTION:Channels 1, 2, 3... are changed in width, the number of tracks of each channel is set on a table, and the number of useful empty tracks of each channel is also set on the table, whereby it is judged if the wiring is possible or not for a channel. And, when a wiring is done for a channel, the number of the empty tracks of the channel is subtracted by one, whereby a wiring channel density inside the channels is partially changed to enable an automatic wiring. As mentioned above, even if the channels differ remarkably from each other in a wiring density, a required automatic wiring can be performed by varying the width of the channel which compose a wiring region of a wiring board. By these processes, an automatic wiring of a high density printed board that surface mounting components such as a chip component, a flat pack, a mini flat pack, and others are mounted can be realized.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、両面プリント板や多層プリント板等のチャネ
ル自動配線等に適用されるプリント板の配線方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a printed board wiring method applied to automatic channel wiring of double-sided printed boards, multilayer printed boards, and the like.

(従来の技術) 第5図は、両面プリント板51の従来のチャネル自動配
線方法を説明するための図でちる。従来のチャネル自動
配線方法においては、両面シリンド板51のフロント面
(バック面)を水平(垂直)方向に複数6細長い短冊状
のチャネル1〜5に分割して配線領域を形成し、これら
のチャネル1〜5を介して自動配線するようになされて
いる。例えば、第5図のA点とB点とを接続する場合、
A点と0点との間は水平方向のチャネル5を介して接続
し、0点とD点との間は、フロント面とバック面とを接
続するスルーホールと垂直方向のチャネル4を介して接
続し、D点において接続線をスルーホールを介して再び
フロント面に導出し、D点とB点との間は水平方向のチ
ャネル1を介して接続するようになされて込る。上記の
従来のチャネル自動配線方法においては、予め通過する
チャネルを決め、これらのチャネル内の詳細トラック5
2を後で決めるようになされている。
(Prior Art) FIG. 5 is a diagram for explaining a conventional automatic channel wiring method for a double-sided printed board 51. In the conventional channel automatic wiring method, the front surface (back surface) of the double-sided cylinder plate 51 is divided horizontally (vertically) into a plurality of 6 elongated strip-shaped channels 1 to 5 to form wiring regions, and these channels are 1 to 5 are automatically wired. For example, when connecting point A and point B in Fig. 5,
Point A and point 0 are connected via a horizontal channel 5, and point 0 and D are connected via a through hole connecting the front surface and the back surface and a vertical channel 4. The connection line is then led out to the front surface again through the through hole at point D, and the connection between point D and point B is made through the horizontal channel 1. In the conventional channel automatic routing method described above, channels to be passed are determined in advance, and detailed tracks 5 within these channels are
2 will be decided later.

さらにこれらの各チャネル1〜50幅は、それぞれ同一
の幅例えばIC(集積回路)のビン間隔の0.1インチ
(2,54111711)に決められていた。
Further, the widths of each of these channels 1 to 50 were determined to be the same width, for example, 0.1 inch (2,54111711), which is the interval between IC (integrated circuit) bins.

上記のように、各チャネル1〜5の幅をそれぞれ同一の
幅に決めることによシ、例えば、各チャネル1〜5内の
トラック52の空トラツク数の管理が簡単となる利点が
あ名が、例えば、各チャネル毎の配線密度を部分的に大
幅に変更する必要がある場合には、配線効率が著しく低
下する等の問題点があった。
As mentioned above, by determining the width of each channel 1 to 5 to be the same width, for example, there is an advantage that the number of empty tracks 52 in each channel 1 to 5 can be easily managed. For example, when it is necessary to locally significantly change the wiring density for each channel, there are problems such as a significant drop in wiring efficiency.

(発明が解決しようとする課題) 第6図は自動配線の対象となる111WB61の一例を
示す部分正面図で、図示の如く、0.1インチのピッチ
間隔で複数のピン63が配列されて込る。第6図におい
て、0,1インチピッチの間隔に3本の配線パターン6
2を配線する場合には、その配線領域を第7図に示す如
く、0.1インチ幅の均等な幅を有する複数のチャネル
に分割して形成し、これらの各チャネルを介して前記の
配線方法で配線することができる。しかしながら、例え
ば、チャネルの中の1チャネル分を拡大表示して示す第
8図に図示されているように、チャネルNの中には、さ
らに小さな障害物81等の配線禁止帯が配設されている
ことがある。このような場合には、そのチャネルの配線
可能領域は、トラックに配線されたパターン82および
83で示すように、配線禁止帯の上方および下方部分に
それぞれ分割されてしまうので、チャネルNの空トラツ
ク容量として表現できなくなシ、従ってそのま\では自
動配線ができなくなる。
(Problem to be Solved by the Invention) FIG. 6 is a partial front view showing an example of 111WB61 to be automatically wired. As shown in the figure, a plurality of pins 63 are arranged at a pitch interval of 0.1 inch. Ru. In Fig. 6, three wiring patterns 6 are arranged at a pitch of 0.1 inch.
2, the wiring area is divided into a plurality of channels having an equal width of 0.1 inch as shown in FIG. Can be wired in any way. However, as shown in FIG. 8, which shows an enlarged view of one of the channels, a wiring prohibition zone such as a smaller obstacle 81 is arranged in channel N. Sometimes there are. In such a case, the routeable area of the channel is divided into upper and lower parts of the prohibited wiring zone, respectively, as shown by patterns 82 and 83 routed on the track, so that the empty track of channel N is It cannot be expressed as a capacitance, so automatic wiring cannot be done as is.

前記の如く、チャネル内に配線禁止帯がある場合、チャ
ネル自動配線を可能とするためには、例えば、そのチャ
ネルを配線禁止帯を境として上下にトラック容量の異な
るチャネルとして表現する必要がある。
As described above, when there is a wiring prohibition zone within a channel, in order to enable channel automatic routing, it is necessary to represent the channel as a channel with different track capacities above and below the wiring prohibition zone, for example.

しかしながら、前記の如く、従来のチャネル自動配線方
法においては、各チャネルの幅がそれぞれ同一の幅に決
められているので、チャネル内に配線禁止帯が設けられ
たシ、または、各チャネル内の配線密度が大幅に変化す
る場合には、チャネル自動配線が得られない等の欠点が
あった。
However, as mentioned above, in the conventional channel automatic wiring method, the width of each channel is determined to be the same width, so there are cases where a wiring prohibited zone is provided within the channel, or wiring within each channel is set to the same width. If the density changes significantly, there are drawbacks such as the inability to achieve channel automatic wiring.

また、特に、プリント板に対する高密度実装が進み、多
くのチップ部品やフラン)ノfツク等が使用されると、
全チャネルをすべて均等の幅例えば、0、1インチの幅
に決めると、そのモデル化ができなくなる等の問題点が
生ずる。
In addition, especially as high-density mounting on printed circuit boards progresses and many chip parts and chips are used,
If all channels are set to have the same width, for example, 0.1 inch, problems will arise, such as the inability to model them.

本発明の課題は、上記従来の問題点を解消し、従来のチ
ャネル配線の利点を保ちながら、各チャネルの配線密度
が大幅に変化する場合でも所望の配線を行なうことがで
きるプリント板の配線方法を提供することである。
An object of the present invention is to solve the above-mentioned conventional problems, and to maintain the advantages of conventional channel wiring, while also making it possible to conduct desired wiring even when the wiring density of each channel changes significantly. The goal is to provide the following.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明によるプリント板の配線方法は、プリント板の板
面を複数のチャネルに分割して配線領域を形成し、前記
チャネルを介して配線するプリント板の配線方法におい
て、前記チャネルの幅を変え、前記チャネル内の配線密
度を部分的に変えて配線することを特徴とする。
(Means for Solving the Problems) A printed board wiring method according to the present invention is a printed board wiring method in which a board surface of a printed board is divided into a plurality of channels to form a wiring area, and wiring is routed through the channels. The method is characterized in that the width of the channel is changed and the wiring density within the channel is partially changed.

(作用) 本発明によれば、プリント板のチャネル配線方法におい
て、各チャネル毎に異なる幅をもたせたシ、または同一
チャネル内においても場所によシ幅を変えることによシ
、各チャネル内の配線トラック容量を変えてチャネル内
の配線密度を部分的に変化させて配線することができる
。これによシ、各チャネル毎および同一チャネル内にお
いても場所によシ配線トラック容量が異なるようなモデ
ルに対しても効率よく自動配線を行なうことができる。
(Function) According to the present invention, in a channel wiring method for a printed board, each channel has a different width, or even within the same channel, the width can be changed depending on the location. By changing the wiring track capacitance, wiring can be performed by partially changing the wiring density within the channel. As a result, automatic wiring can be efficiently performed even for models in which the wiring track capacity differs for each channel and for different locations within the same channel.

(実施例) 第1図は本発明の一実施例のプリント板の配線方法を説
明するための図で、100はプリント板を示し、このプ
リント板100の板面に形成される複数のチャネル1〜
4は、その水平方向には各チャネル内で幅(トラック数
)が均等であるが、各チャネル間ではそれぞれ幅が異な
るように形成されている。
(Embodiment) FIG. 1 is a diagram for explaining a printed board wiring method according to an embodiment of the present invention, in which 100 indicates a printed board, and a plurality of channels 1 formed on the board surface of this printed board 100 are shown. ~
4, each channel has the same width (number of tracks) in the horizontal direction, but each channel is formed to have a different width.

第2図は本発明の他の実施例を説明するための図で、2
00はプリント板を示し、このプリント板200の板面
に形成される複数のチャネル1〜4は、各チャネル間で
幅が異なるほかに、各チャネルはそれぞれその水平方向
においてもそれぞれ異なる幅を有するように形成されて
いる。
FIG. 2 is a diagram for explaining another embodiment of the present invention.
00 indicates a printed board, and the plurality of channels 1 to 4 formed on the board surface of this printed board 200 not only have different widths among the channels, but also have different widths in the horizontal direction. It is formed like this.

例えば、第2図々示のようなチャネル分割を行なうと、
各チャネルの水平方向位置■〜■におけるトラック容量
は、第3図々示のようなマトリクスで表わすことができ
る。なお、第3図において、縦軸はチャネル番号を示し
、横軸は水平方向の配線通過ポイントを表わしている。
For example, if you perform channel division as shown in Figure 2,
The track capacity of each channel at horizontal positions (1) to (2) can be represented by a matrix as shown in FIG. In FIG. 3, the vertical axis represents the channel number, and the horizontal axis represents the horizontal wiring passing points.

また各枠内の数字は、それぞれそのポイントにおいて配
線可能なトランクの数を示す。チャネル自動配線プログ
ラムにおりては、前記の枠内の数字が1より犬であれば
配線可能と判断し、その経路を用すて配線を行ない、こ
の配線が終ると、前記の数字から1を減することになる
。このようにして前記の数字が0になると、そのチャネ
ルにはもはや配線が通らないものと判断することになる
Furthermore, the numbers within each frame indicate the number of trunks that can be wired at that point. In the channel automatic wiring program, if the number in the box above is greater than 1, it is determined that wiring is possible, and the wiring is performed using that route, and when this wiring is completed, 1 is subtracted from the number above. It will decrease. When the number becomes 0 in this way, it is determined that no wiring can be routed through that channel anymore.

以上のようにして自動配線でチャネルをわシあてた後、
トラックわシあてのステップによシ各チャネル内の配線
につ−て固定的なトラックを決定する。このトラックわ
シあてのステップでは、第4図に示すように、各チャネ
ル内の配線をまず論理的なトラックにわ’)’;hて、
その後それらのチャネルと論理トラックを物理的なトラ
ックに変換するとb92段階のトラックわシあてが行な
われる。
After assigning the channels using automatic wiring as described above,
The track assignment step determines fixed tracks for the wiring within each channel. In this track assignment step, as shown in Figure 4, the wiring within each channel is first assigned to a logical track.
After that, those channels and logical tracks are converted into physical tracks, and the track assignment at step b92 is performed.

本発明によれば、第1図または第2図々示の如く、各チ
ャネルの幅を変え、各チャネルに対するトラック数をテ
ーブルにセットし、また各チャネル内の有効空トラツク
数をテーブルにセットすることによシ、各チャネルに配
線可能かどうかを判断し、さらに、配線された場合に、
そのチャネルの空トランク数を1つ減博することにょシ
、各チャイ・ル内の配線密度を部分的に変えて自動配線
することができる。
According to the present invention, as shown in FIG. 1 or 2, the width of each channel is changed, the number of tracks for each channel is set in a table, and the number of effective empty tracks in each channel is set in a table. In particular, determine whether each channel can be wired and, if wired,
By reducing the number of empty trunks in that channel by one, automatic wiring can be performed by partially changing the wiring density within each channel.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、プリント板の配線領域を形成するチャ
ネルの幅を変えることにょシ、各チャネルの配線密度が
大幅に変化する場合でも、所望の自動配線を行なうこと
ができる。これにょシ例えば、チップ部品、フラットパ
ック、およびミニフラット・ぐツク等の面実装部品を搭
載する高密度プリント板の自動配線も可能となる。
According to the present invention, desired automatic wiring can be performed even when the wiring density of each channel changes significantly by changing the width of the channels forming the wiring area of the printed board. This also enables automatic wiring of high-density printed circuit boards on which surface-mounted components such as chip components, flat packs, and mini-flat packs are mounted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法を実施するのに用Aられる一実施例
のプリント板のチャネルを示す図、第2図は本発明方法
を実施するのに用いられる他の実施例のプリント板のチ
ャネルを示す図、第3図は第2図におけるトラック容量
を示す図、第4図は本発明方法の一実施例のフローチャ
ート図、第5図〜第8図はそれぞれ従来のチャネル自動
配線を説明するための図である。 100.200・・・プリント板。  ゛出願人代理人
 弁理士 鈴 江 武 彦+1投士 、 C%4(y)ぐ・・・ +計相) 一 N  の  寸 1.。 キy世士 、−(N  (Y)  ぐ ・・・ キ?吹令
FIG. 1 is a diagram showing channels of a printed board according to one embodiment used to carry out the method of the present invention, and FIG. 2 is a diagram showing channels of a printed board according to another embodiment used to carry out the method of the present invention. FIG. 3 is a diagram showing the track capacity in FIG. 2, FIG. 4 is a flowchart of an embodiment of the method of the present invention, and FIGS. 5 to 8 respectively explain conventional channel automatic wiring. This is a diagram for 100.200...Printed board.゛Applicant's representative Patent attorney Takehiko Suzue + 1 pitcher, C%4(y)gu...+Measurement) 1 N size 1. . Kiy worldly, -(N (Y) gu... Ki? Ordinance?

Claims (1)

【特許請求の範囲】[Claims] プリント板の板面を複数のチャネルに分割して配線領域
を形成し、前記チャネルを介して配線するプリント板の
配線方法において、前記チャネルの幅を変え、前記チャ
ネル内の配線密度を部分的に変えて配線することを特徴
とするプリント板の配線方法。
In a printed board wiring method in which a board surface of a printed board is divided into a plurality of channels to form a wiring area, and wiring is routed through the channels, the width of the channel is changed to partially increase the wiring density within the channel. A printed circuit board wiring method characterized by changing the wiring.
JP3204288A 1988-02-15 1988-02-15 Wiring of printed board Pending JPH01206693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3204288A JPH01206693A (en) 1988-02-15 1988-02-15 Wiring of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3204288A JPH01206693A (en) 1988-02-15 1988-02-15 Wiring of printed board

Publications (1)

Publication Number Publication Date
JPH01206693A true JPH01206693A (en) 1989-08-18

Family

ID=12347810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3204288A Pending JPH01206693A (en) 1988-02-15 1988-02-15 Wiring of printed board

Country Status (1)

Country Link
JP (1) JPH01206693A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8893073B2 (en) * 2012-12-27 2014-11-18 Synopsys, Inc. Displaying a congestion indicator for a channel in a circuit design layout

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8893073B2 (en) * 2012-12-27 2014-11-18 Synopsys, Inc. Displaying a congestion indicator for a channel in a circuit design layout
US9064082B2 (en) 2012-12-27 2015-06-23 Synopsys, Inc. Updating pin locations in a graphical user interface of an electronic design automation tool
US10248751B2 (en) 2012-12-27 2019-04-02 Synopsys, Inc. Alternative hierarchical views of a circuit design

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