JPH01205557A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01205557A JPH01205557A JP8830388A JP3038888A JPH01205557A JP H01205557 A JPH01205557 A JP H01205557A JP 8830388 A JP8830388 A JP 8830388A JP 3038888 A JP3038888 A JP 3038888A JP H01205557 A JPH01205557 A JP H01205557A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- external
- package
- shape
- memory alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims abstract description 6
- 239000000956 alloy Substances 0.000 claims abstract description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、パッケージの外部リ
ード曲りを容易に回復することができる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which bent external leads of a package can be easily recovered.
従来、この種の半導体装置では、パッケージの外部リー
ドは内部リードもふくめで銅、ニッケル系合金、鉄等の
単一構造で出来ていた。Conventionally, in this type of semiconductor device, the external leads of the package, including the internal leads, were made of a single structure of copper, nickel alloy, iron, or the like.
」二連した従来の半導体装置は、パッケージの外部リー
ドは一般的な材料で製造されていたため、外部から力が
加わると塑性変形し、これを修正するには多大の工数が
必要であるという欠点があった。In conventional double-connected semiconductor devices, the external leads of the package were made of common materials, so they plastically deformed when external force was applied, which required a large amount of man-hours to correct. was there.
本発明の半導体装置はパッケージの外部リードが形状記
憶合金材料により作られ内部リードと接合されたリード
構造となっていることを特徴とする。The semiconductor device of the present invention is characterized in that the external lead of the package is made of a shape memory alloy material and has a lead structure joined to the internal lead.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の斜視図である。第２図は本
発明の一部断面図である。外部リード１は形状記憶合金
を材料とし、パッケージ３の外側で内部リード２と接合
されている。外部リード１は所定手段により所定温度条
件にて曲げ形成が行なわれＤ工Ｐ形に加工されている。FIG. 1 is a perspective view of an embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the present invention. The outer lead 1 is made of a shape memory alloy and is joined to the inner lead 2 on the outside of the package 3. The external lead 1 is bent by a predetermined means under a predetermined temperature condition, and is processed into a D-shape and a P-shape.
点線は形成前の状態である。第３図は、外部からの力に
より外部リード１が変形している状態であるが、本実施
例では第４図に示す様に外部リード１が曲げ形成された
ＡｊＪ記温度条件の雰囲気に戻すと矢印の様に変形して
いた外部リード１が元のリード曲がりのない状態に修正
される。The dotted line is the state before formation. Although FIG. 3 shows a state in which the external lead 1 is deformed by an external force, in this embodiment, the external lead 1 is returned to the atmosphere under the temperature conditions indicated by AjJ under which the external lead 1 was bent as shown in FIG. 4. The external lead 1, which had been deformed as shown by the arrow, is corrected to its original state without lead bending.
以上説明したように本発明は、外部リードが形状記憶合
金を素材としているため外部から力が加わって変形して
も短時間で元に修正できるという効果がある。As explained above, the present invention has the effect that even if the external lead is deformed by an external force, it can be restored to its original state in a short time because the external lead is made of a shape memory alloy.
第１図は本発明の一実施例の斜視図、第２図は該実施例
の一部断面図、第３図は該実施例の外部リードが変形し
た側面図、第４図は該実施例の外部リ−１’が修正され
た側面図である。
１−・・・外部リード、 ２・・・・・・内部リード、
３ ・・・パッケージ、４・・・・・・半導体素子、５
・・・・・・ワイヤ。
代理人 弁理士 内 原 晋
田
〈
軟Fig. 1 is a perspective view of an embodiment of the present invention, Fig. 2 is a partial sectional view of the embodiment, Fig. 3 is a side view of the embodiment with external leads deformed, and Fig. 4 is the embodiment. FIG. 2 is a side view of the modified external lead 1' of FIG. 1-...External lead, 2...Internal lead,
3...Package, 4...Semiconductor element, 5
...Wire. Agent Patent Attorney Shinda Uchihara
Claims (1)
れ内部リードと接合されたリード構造となっていること
を特徴とする半導体装置。A semiconductor device characterized in that the external lead of the package has a lead structure made of a shape memory alloy material and joined to the internal lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8830388A JPH01205557A (en) | 1988-02-12 | 1988-02-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8830388A JPH01205557A (en) | 1988-02-12 | 1988-02-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205557A true JPH01205557A (en) | 1989-08-17 |
Family
ID=12302524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8830388A Pending JPH01205557A (en) | 1988-02-12 | 1988-02-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205557A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341946U (en) * | 1989-08-31 | 1991-04-22 |
-
1988
- 1988-02-12 JP JP8830388A patent/JPH01205557A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341946U (en) * | 1989-08-31 | 1991-04-22 |
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