JPH01201965A - Manufacture of non-volatile storage device - Google Patents
Manufacture of non-volatile storage deviceInfo
- Publication number
- JPH01201965A JPH01201965A JP63025822A JP2582288A JPH01201965A JP H01201965 A JPH01201965 A JP H01201965A JP 63025822 A JP63025822 A JP 63025822A JP 2582288 A JP2582288 A JP 2582288A JP H01201965 A JPH01201965 A JP H01201965A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- film
- silicon nitride
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000003860 storage Methods 0.000 title abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 37
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000005641 tunneling Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000007789 gas Substances 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 230000006641 stabilisation Effects 0.000 abstract description 2
- 238000011105 stabilization Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＭＮＯＳ （金属−窒化シリコン膜−酸化シ
リコン膜−半導体）型の電界効果トランジスタからなる
不揮発性記憶装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a nonvolatile memory device comprising an MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) field effect transistor. .
（従来の技術）
従来、不揮発性記憶装置の代表的なものとして、ＭＮＯ
８構造の半導体記憶装置がよく知られている。ＭＮＯ５
型不揮発性記憶装置は、窒化シリコン膜と薄い酸化シリ
コン膜の界面または、その近傍の窒化シリコン膜中に生
じたトラップ準位に、半導体基板側から電荷の１−ンネ
リング注入、蓄積を行い、トランジスタのしきい値電圧
（Ｖｔｈ）を変化させて情報を記憶させることを原理と
するものである。(Prior art) Conventionally, MNO is a typical non-volatile storage device.
8-structure semiconductor memory devices are well known. MNO5
A type nonvolatile memory device performs one-channel injection and accumulation of charge from the semiconductor substrate side into a trap level generated in the silicon nitride film at or near the interface between a silicon nitride film and a thin silicon oxide film, and then The principle is to store information by changing the threshold voltage (Vth) of the memory.
第２図に従来の製造方法によって得られたＭＮＯ８型半
導体記憶装置の断面構造を示す。同図において、１１は
Ｐ型シリコン基板、１２および１３はＮ型の選択拡散領
域であり、ソース領域およびドレイン領域と呼ばれる。FIG. 2 shows a cross-sectional structure of an MNO8 type semiconductor memory device obtained by a conventional manufacturing method. In the figure, 11 is a P-type silicon substrate, and 12 and 13 are N-type selective diffusion regions, which are called a source region and a drain region.
１４は厚い酸化シリコン膜、１５はトンネリング媒体と
なりうる薄い酸化シリコン膜、１６は窒化シリコン膜、
１７はアルミニウム膜からなるゲート電極である。14 is a thick silicon oxide film, 15 is a thin silicon oxide film that can serve as a tunneling medium, 16 is a silicon nitride film,
17 is a gate electrode made of an aluminum film.
第２図に示すようなＭＮＯ３型不揮発性記憶装置におい
て、薄い酸化シリコン膜１５と窒化シリコン膜１６の界
面の形成が非常に重要であるが、従来の製造方法では、
トンネリング媒体となりうる薄い（２０人程度）酸化シ
リコン膜１５を熱酸化により形成したのち、直ちに酸化
シリコン膜１５上に、気相成長法により箪化シリコン膜
１６を形成して、酸化シリコン−窒化シリコン界面を形
成する方法が通常であった。In the MNO3 type nonvolatile memory device shown in FIG. 2, the formation of the interface between the thin silicon oxide film 15 and the silicon nitride film 16 is very important, but in the conventional manufacturing method,
After forming a thin (approximately 20 layers) silicon oxide film 15, which can serve as a tunneling medium, by thermal oxidation, a silicon oxide film 16 is immediately formed on the silicon oxide film 15 by vapor phase growth to form a silicon oxide-silicon nitride film. The usual method was to form an interface.
（発明が解決しようとする課題）
上記、従来のＭＮＯ８型不揮発性記憶装置の電気的特性
として、（ａ）酸化シリコン膜と窒化シリコン膜の界面
もしくは、その近傍の窒化シリコン膜中の電＃ｆ蓄積と
非蓄積状態に対応するヒステリシス曲線の上下の幅ΔＶ
ｔｈ（Ｌ、きい値電圧の窓の大きさ）。（ｂ）蓄積、非
蓄積状態の電荷の記憶保持特性。（ｃ）繰返し書き込み
、消去を行ったのちの（ａ）、（ｂ）項の劣化特性。な
どの特性が、実用上極めて重要であり、さらに、これら
の特性が精度よく安疋して得られることが、ＭＮＯ８型
不揮発性記憶装置の製造上の最大の課題であり、また実
用上の重大な問題となっている。特に、従来の酸化シリ
コン膜１５の上に薫化シリコン膜１６を直接、気相成長
法により形成する方法では、酸化シリコン膜１５と窒化
シリコン膜１６との界面は、構造物性が異なる材料が機
械的に接した一種の不連続面であり、界面に歪や欠陥が
発生することが多い。このような歪や欠陥は、電荷のト
ラップの分布、酸化シリコン−半導体界面、および酸化
シリコン−窒化シリコン界面の状態などに強く影響を与
え、電気的特性のそろったＭＮＯ８型不揮発性記憶装置
を精度よく安定して製造することを困難にする欠点があ
った。(Problems to be Solved by the Invention) As the electrical characteristics of the conventional MNO8 type nonvolatile memory device described above, (a) electric current #f in the silicon nitride film at or near the interface between the silicon oxide film and the silicon nitride film; Upper and lower width ΔV of the hysteresis curve corresponding to accumulation and non-accumulation states
th(L, threshold voltage window size). (b) Memory retention characteristics of charge in accumulated and non-accumulated states. (c) Deterioration characteristics in terms (a) and (b) after repeated writing and erasing. Properties such as these are extremely important in practice, and obtaining these properties with precision and ease is the biggest challenge in manufacturing MNO8 type nonvolatile memory devices, and is also of great practical importance. This has become a serious problem. In particular, in the conventional method of forming the smoked silicon film 16 directly on the silicon oxide film 15 by vapor phase growth, the interface between the silicon oxide film 15 and the silicon nitride film 16 is made of materials with different structural properties. It is a type of discontinuous surface that is in contact with the surface, and distortions and defects often occur at the interface. Such distortions and defects strongly affect the distribution of charge traps, the state of the silicon oxide-semiconductor interface, and the silicon oxide-silicon nitride interface, making it difficult to maintain the accuracy of MNO8 nonvolatile memory devices with uniform electrical characteristics. There were drawbacks that made it difficult to produce well and stably.
本発明の目的は、従来の欠点を解消は、特に窒化シリコ
ンと酸化シリコン界面状態の安定化に関し制御性のよい
製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method with good controllability, particularly with regard to stabilization of the interface between silicon nitride and silicon oxide, which overcomes the drawbacks of the prior art.
（課題を゛解決するための手段）
本発明の不揮発性記憶装置の製造方法は、−導電型半導
体基板面に、正札または電子のトンネリング媒体となり
うる薄い酸化シリコン膜を選択形成する工程と、この酸
化シリコン膜上に窒化シリコン膜を形成する工程と、窒
化シリコン膜上にゲート電極を被着する工程とを有し、
薄い酸化シリコン膜表面上をアンモニアプラズマ処理す
るものである。(Means for Solving the Problems) The method for manufacturing a non-volatile memory device of the present invention includes the steps of: - selectively forming a thin silicon oxide film, which can be used as an identification tag or an electron tunneling medium, on the surface of a conductive type semiconductor substrate; The method includes a step of forming a silicon nitride film on the silicon oxide film, and a step of depositing a gate electrode on the silicon nitride film,
This involves ammonia plasma treatment on the surface of a thin silicon oxide film.
（作 用）
本発明の製造方法によれば、薄い酸化シリコン膜を形成
したのち、アンモニアガス雰囲気中でプラズマ処理を行
い、酸化シリコン膜表面を窒化させ、そののち、窒化シ
リコン膜を所定の厚さに気相成長法により形成させるた
め、酸化シリコン膜と窒化シリコン膜の界面の不連続性
が緩和され、界面の歪や欠陥を少なくすることができ、
これらの歪や欠陥に基づく電気的特性の不安定性を解消
することができる。(Function) According to the manufacturing method of the present invention, after forming a thin silicon oxide film, plasma treatment is performed in an ammonia gas atmosphere to nitride the surface of the silicon oxide film, and then the silicon nitride film is formed to a predetermined thickness. Since it is formed using a vapor phase growth method, the discontinuity at the interface between the silicon oxide film and the silicon nitride film is alleviated, and distortion and defects at the interface can be reduced.
The instability of electrical characteristics caused by these distortions and defects can be eliminated.
（実施例） 本発明の一実施例を第１図に基づいて説明する。(Example) An embodiment of the present invention will be described based on FIG.
第１図（Ａ）〜（Ｃ）は本発明の製造方法の一実施例を
ボす工程図である。FIGS. 1(A) to 1(C) are process diagrams showing one embodiment of the manufacturing method of the present invention.
第１図（Ａ）において、Ｐ型のシリコン基板１にＮ型の
拡散層からなるソース領域２、ドレイン領域３を公知の
選択拡散技術で形成し、選択拡散時に形成した厚い酸化
シリコン膜４の所定の部分をフカ１〜エツチング法によ
り開孔部を形成し、この開孔部に、電荷のトンネリング
が起りうるような厚さ（１０〜３０人程度）変成い酸化
シリコン膜５を通常の熱酸化により形成させる。本実施
例では８００°Ｃの酸素雰囲気中で酸化して形成させ、
膜厚は２５人とした。In FIG. 1(A), a source region 2 and a drain region 3 made of N-type diffusion layers are formed on a P-type silicon substrate 1 by a known selective diffusion technique, and a thick silicon oxide film 4 formed during selective diffusion is formed on a P-type silicon substrate 1. An opening is formed in a predetermined portion by an etching method, and a modified silicon oxide film 5 with a thickness (approximately 10 to 30 layers) that allows charge tunneling is placed in the opening using normal heat. Formed by oxidation. In this example, it is formed by oxidation in an oxygen atmosphere at 800°C,
The film thickness was set at 25 people.
第１図（Ｂ）において、酸化シリコン膜５の表面上を、
アンモニアガス雰囲気中でプラズマ処理を行う。本実施
例では、アンモニアプラズマ処理を、基板温度３００℃
、パワー５０Ｗ、ガス圧０．５Ｔｏｒｒの条件−トで実
施した。また、・この工程により、酸化シリコン膜５の
表面が窒化され、酸化シリコン膜５の厚さが薄くなるが
、本実施例では、アンモニアプラズマ処理をしたのちの
酸化シリコン膜５の厚さが約２０人となるように制御し
た。In FIG. 1(B), on the surface of the silicon oxide film 5,
Plasma treatment is performed in an ammonia gas atmosphere. In this example, the ammonia plasma treatment was performed at a substrate temperature of 300°C.
The experiment was carried out under the following conditions: , power 50 W, and gas pressure 0.5 Torr. In addition, through this step, the surface of the silicon oxide film 5 is nitrided and the thickness of the silicon oxide film 5 becomes thin; however, in this embodiment, the thickness of the silicon oxide film 5 after the ammonia plasma treatment is approximately The number of participants was controlled to 20.
第１図（Ｃ）において、アンモニアプラズマ処理した酸
化シリコン膜６の上に、シラン（ＳＨ，）とアンモニア
（ＮＨ３）の化学反応に基づく気相成長法によって、７
５０℃ｙ Ｎ Ｈ３／ Ｓ ｘ Ｈ４＝５０の条件下で
窒化シリコン膜７を約５００変成度形成させる。次にア
ルミニウム（ＡＱ）電極８を通常の真空蒸着法により被
着させ、ＡＩ２ゲートＭＮＯ８型不揮発性記憶装置を作
製することができる。In FIG. 1(C), 7 is deposited on a silicon oxide film 6 treated with ammonia plasma by a vapor phase growth method based on a chemical reaction between silane (SH, ) and ammonia (NH3).
The silicon nitride film 7 is formed to have a metamorphic degree of about 500 under the condition of 50° C.y N H3/S x H4=50. Next, an aluminum (AQ) electrode 8 is deposited by a normal vacuum evaporation method to produce an AI2 gate MNO8 type nonvolatile memory device.
本実施例では、ソース、ドレインを選択拡散で形成する
ＡＱゲート型のＭＮＯ８型不揮発性記憶装置を作製する
場合について説明を行なってきたが、ゲート電極として
、ポリシリコン等の高融点金属を用いて、本発明の製造
方法によりゲート絶縁膜を形成して、周知のセルファラ
イン技術により、ソース、ドレインを形成してもよい。In this example, we have explained the case of manufacturing an AQ gate type MNO8 type nonvolatile memory device in which the source and drain are formed by selective diffusion. A gate insulating film may be formed by the manufacturing method of the present invention, and a source and a drain may be formed by a well-known self-line technique.
（発明の効果）
本発明によれば、酸化シリコン膜と窒化シリコン膜の界
面の不連続性が緩和され、界面の歪や欠陥を少なくさせ
ることができる。その結果、界面の歪や欠陥に基づ＜Ｍ
ＮＯ８型不揮発性記憶装置の電気特性の不安定性を解消
することができ、特性のそろった精度の良いＭＮＯ８型
不揮発性記憶装置を製造することができ、その実用上の
効果は大である。(Effects of the Invention) According to the present invention, discontinuity at the interface between a silicon oxide film and a silicon nitride film can be alleviated, and strain and defects at the interface can be reduced. As a result, <M
The instability of the electrical characteristics of the NO8 type nonvolatile memory device can be eliminated, and a highly accurate MNO8 type nonvolatile memory device with uniform characteristics can be manufactured, which has great practical effects.
第１図（Ａ）〜（Ｃ）は本発明の一実施例における不揮
発性記憶装置の製造方法の工程順断面図、第２図は従来
のＭＮＯ８型不揮発性記憶装置の構造を示す断面図であ
る。
１ ・・シリコン基板、２・・・ソース領域、３ ・・
ドレイン領域、４ ・・ 厚い酸化シリコン膜、５
・・・薄い酸化シリコン膜、６−・・アンモニアプラズ
マ処理した酸化シリコン膜、７ 窒化シリコン膜、８
・・アルミニウム電極。
特許出願人 松ド電子工業株式会社FIGS. 1(A) to (C) are cross-sectional views in the order of steps of a method for manufacturing a non-volatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of a conventional MNO8 type non-volatile memory device. be. 1...Silicon substrate, 2...Source region, 3...
Drain region, 4... Thick silicon oxide film, 5
...Thin silicon oxide film, 6-...Silicon oxide film treated with ammonia plasma, 7 Silicon nitride film, 8
...Aluminum electrode. Patent applicant Matsudo Electronics Industry Co., Ltd.
Claims (1)
ング媒体となりうる薄い酸化シリコン膜を選択形成する
工程と、前記酸化シリコン膜上に窒化シリコン膜を形成
する工程と、前記窒化シリコン膜上にゲート電極を被着
する工程とを有する不揮発性記憶装置の製造方法におい
て、前記薄い酸化シリコン膜の表面上をアンモニアプラ
ズマ処理することを特徴とする不揮発性記憶装置の製造
方法。A step of selectively forming a thin silicon oxide film that can be used as a tag or an electron tunneling medium on the surface of a semiconductor substrate of one conductivity type, a step of forming a silicon nitride film on the silicon oxide film, and a step of forming a gate electrode on the silicon nitride film. A method of manufacturing a non-volatile memory device comprising the step of depositing a thin silicon oxide film on the surface of the thin silicon oxide film is subjected to ammonia plasma treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63025822A JPH01201965A (en) | 1988-02-08 | 1988-02-08 | Manufacture of non-volatile storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63025822A JPH01201965A (en) | 1988-02-08 | 1988-02-08 | Manufacture of non-volatile storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01201965A true JPH01201965A (en) | 1989-08-14 |
Family
ID=12176552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63025822A Pending JPH01201965A (en) | 1988-02-08 | 1988-02-08 | Manufacture of non-volatile storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01201965A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217317A (en) * | 2001-01-16 | 2002-08-02 | Sony Corp | Non-volatile semiconductor storage device and its manufacturing method |
| WO2004021449A1 (en) * | 2002-08-30 | 2004-03-11 | Fasl Llc | Semiconductor memory and method for manufacturing same |
| KR100666615B1 (en) * | 2004-04-14 | 2007-01-09 | 매그나칩 반도체 유한회사 | Flash Memory Device |
-
1988
- 1988-02-08 JP JP63025822A patent/JPH01201965A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217317A (en) * | 2001-01-16 | 2002-08-02 | Sony Corp | Non-volatile semiconductor storage device and its manufacturing method |
| JP4617574B2 (en) * | 2001-01-16 | 2011-01-26 | ソニー株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| WO2004021449A1 (en) * | 2002-08-30 | 2004-03-11 | Fasl Llc | Semiconductor memory and method for manufacturing same |
| US7253046B2 (en) | 2002-08-30 | 2007-08-07 | Spansion Llc. | Semiconductor memory device and manufacturing method thereof |
| US7410857B2 (en) | 2002-08-30 | 2008-08-12 | Spansion Llc. | Semiconductor memory device and manufacturing method thereof |
| KR100666615B1 (en) * | 2004-04-14 | 2007-01-09 | 매그나칩 반도체 유한회사 | Flash Memory Device |
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