JP2000332235A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold high mobility of conductive carriers by a method wherein at least a part of a gate insulation film is composed of a material capable of accumulating charges. SOLUTION: A silicon oxide film is used as a MOSFET gate insulation film and nitrogen is used as an electrostatic property material. After a silicon substrate is dipped in a solution containing ammonia and a hydrogen peroxide, a surface oxide film is removed with a fluoric acid solution, and after a field oxide film is formed, the silicon substrate is heated in a wet oxidation ambience to form the silicon oxide film. Immediately after formation of the oxide film, an oxynitriding processing is performed in an oxynitriding furnace. Introduced nitrogen atoms are easy to deposit on an interface between a silicon oxide film 1 and a silicon substrate 8 originally, but, since the oxidation advances simultaneously, a structure as if a silicon oxynitride film 2 is sandwiched between the silicon oxide films 1 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventional MOSFET (Metal-Oxide Sem)
For example, in the case of an n-type MOSFET, as shown in FIG. 10, the basic structure of an i-conductor field-effect transistor is a gate insulating film 11 (about 3 to 10 nm) on a p-type substrate.
And a gate electrode 3, and n-type diffusion layers (source 4 and drain 5) are arranged on both sides thereof. To operate the MOSFET, the gate electrode 3 is positively biased and the substrate 8
By bending and electrically inverting the energy band on the substrate side near the boundary between the gate insulating film 11 and the gate insulating film 11, a channel is formed, and carriers are conducted between the source 4 and drain 5 electrodes (not shown).

As the amount of data handled increases, MOSF
Higher speed ET is required, but MOSFET
In general, the speeding up is performed by shortening the gate length, making the gate oxide film thinner, and making the source / drain a shallow junction. However, when the gate length is reduced to about 0.3 μm or less, a leak current flows between the source / drain and the threshold voltage decreases even though the channel is not open. Therefore, usually, boron ions are implanted into the channel region so as to have a higher concentration than the substrate (the channel stopper 7 in FIG. 10). By doing so, the energy level inside the substrate is raised, and the leak path of the current flowing between the source and the drain can be closed (Japanese Patent Laid-Open No. 5-102477).

[0004] In such a situation, a p-type MO having a different conduction type is used.
The same is true for the SFET, only the conductivity type is changed.

[0005]

In the conventional MOSFET, in order to suppress punch-through, the concentration is set to 10 ¹⁶ / cm ³ to 10 ¹⁷ / cm ³ by ion implantation into the channel region.
Introduce some impurities. As a result, not only the energy level inside the substrate but also the energy level near the interface of the gate insulating film rises, and the threshold voltage increases. In this case, in order to adjust the threshold voltage, a channel region (1 in FIG.
It becomes necessary to perform ion implantation in 0).

[0006] Therefore, the probability of scattering of ionized impurities of the conductive carrier increases, and the carrier mobility decreases. This means that the operation speed of the device is reduced. That is, in the conventional MOSFET, in order to adjust the threshold voltage, the channel region 10 through which carriers pass is formed.
, The scattering probability of conduction carriers is increased, the mobility is reduced, and as a result, the operation speed of the semiconductor device is reduced.

[0007]

FIG. 1 is a sectional view of a MOSFET as an example of a semiconductor device according to the present invention which has solved the above-mentioned problems. In the figure, 2 is a silicon oxynitride film, 3 is a gate electrode, 4 is a source, 5 is a drain, 6 is a buried insulating film, 7 is a channel stopper, 8 is a silicon substrate, 9
Is an element isolation insulating film.

As described above, ion implantation into the channel region becomes a scattering source of carriers. At this time, the current decreases. In order to obtain an appropriate threshold voltage without lowering the current, a structure for controlling the threshold voltage without introducing impurities into the channel is required. Therefore, if a positive charge can be stored in the gate insulating film, for example, as shown in FIG. 2, the electrostatic energy of the gate insulating film as viewed from the electrons decreases (that is, the gate electrode 14 is effectively biased positively). The threshold voltage can be lowered). If a material charged to the opposite pole is used, the threshold voltage can be increased.

Therefore, it can be realized by forming at least a part of the gate insulating film from a material (2, 15 or 18) capable of storing electric charges. As such a combination of the insulating film and the charging material, for example, a silicon oxide film and nitrogen can be considered. That is, by nitriding the silicon oxide film under appropriate conditions, the MOSFE of the present invention can be formed.
T is obtained.

Further, for example, a gate insulating film can be provided with a charging function by adding a group V element such as arsenic to a titanium oxide film having a small band gap.
Such a structure can be achieved by a group V element other than arsenic. Further, the p-type MOSFET can be achieved by using a group III element such as gallium instead of arsenic.

The above gate insulating film is made of, for example, NM
In the case of OS, since a positively charged level of about several tens of meV to 1 eV is formed in the gate insulating film, the same state as a state where a positive voltage is applied can be formed without applying a positive voltage to the gate electrode. Therefore, the threshold voltage can be reduced accordingly.

[0012]

(Embodiment 1) One embodiment of the present invention will be described with reference to the sectional view of an n-type MOSFET shown in FIG. This embodiment shows a case where a silicon oxide film is used as a gate insulating film of a MOSFET and nitrogen is used as a chargeable material. In the portion of the insulating film in FIG. 9, the buried insulating film 6, the gate electrode 3, the silicon oxide film 1 (1 nm), and the silicon oxynitride film 2 extend from A to B along the section of the line segment AB.
(1.5 nm), a silicon oxide film 1 (0.5 nm), and a silicon substrate 8. The silicon substrate 8 has a channel stopper 7 for preventing leakage current between the source and the drain.
Is ion-implanted with boron.

A method for forming such an insulating film will be described below. After the silicon substrate is immersed in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed with a hydrofluoric acid aqueous solution, and then a field oxide film is formed. The substrate is heated to 850 ° C. in an oxidizing atmosphere to form a 3 nm-thick silicon oxide film (SiO ₂ film). Immediately after the oxide film is formed, an oxynitriding process is performed in an oxynitriding furnace. The processing method is a method in which the substrate is kept at 1000 ° C. for 10 minutes in an atmosphere in which nitrous oxide gas (N ₂ O gas) is flowing at a flow rate of 3 SLM (Standard Litter per Minute).

At this time, oxidation proceeds simultaneously with nitridation.
The thickness of the insulating film is slightly increased to 3.5 nm. Although the introduced nitrogen atoms originally tend to precipitate at the interface between the silicon oxide film 1 and the silicon substrate 8, the oxidation proceeds at the same time, so that a structure in which the silicon oxynitride film 2 is sandwiched by the silicon oxide film 1 is formed. Is done. The gate electrode is formed of polysilicon doped with phosphorus by a chemical vapor deposition method (CVD method).

FIG. 11 shows an energy band diagram when a gate voltage is not applied in a cross section along the line AB in FIG. Since the nitrogen atom is a group V element, its surroundings are 4
An extra electron 13 exists in the atomic structure having valence as a unit. In fact, when nitrogen is implanted into a silicon substrate, it becomes an n-type dopant. The surplus electrons 13 tunnel through the thin silicon oxide film 1 on the substrate side. Therefore, the silicon oxynitride film 2 is positively charged. MOSFE
The threshold voltage of T becomes lower by the amount of the charge. From another viewpoint, surplus electrons 13 enter the silicon oxide film 1-substrate interface.

FIG. 12 shows an energy band diagram corresponding to FIG. 11 when a positive voltage is applied to the gate. MOSFE
The conduction carriers in the channel region of T (in this case, electrons 1
In 3), since the gate insulating film 11 has the effect of being positively charged, the threshold voltage can be reduced.

To lower the increased threshold voltage, as shown in FIG. 10, a dopant (in this case, n-type, for example, arsenic) having a conductivity type different from the conductivity type of the substrate is made shallow in the channel region 10 (FIG. 10). There is a method of ion implantation (about 10 nm from the interface). However, in this method, conduction carriers are scattered by ionized impurities, and carrier mobility is reduced.

On the other hand, according to the method of the present invention, unlike the counter doping method, it is not necessary to implant impurities into the channel region. For this reason, the scattering probability of the conduction carriers for ionized impurities is relatively low, and the mean free path is large, so that the carrier mobility is high. Therefore, the operation speed of the MOSFET can be finally increased.

(Embodiment 2) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
The structure (FIG. 1) and energy band diagrams (FIGS. 11 and 12) of the MOSFET shown in this embodiment are qualitatively
Will be the same as The manufacturing process is the same except for the gate insulating film. This embodiment shows a case where a silicon oxide film is used as a gate insulating film of a MOSFET and a titanium oxide film is used as a charging material.

In the portion of the insulating film shown in FIG. 1, a buried insulating film 6, a gate electrode 3, a silicon oxide film 1 (0.5 nm), a titanium oxide film 1
8 (10 nm), a silicon oxide film 1 (0.5 nm), and a p-type silicon substrate 8. Boron is ion-implanted into the substrate as a channel stopper 7 to prevent a leak current between the source and the drain.

A method for forming such a gate insulating film will be described below. The silicon substrate is cleaned and subjected to element isolation as described in the first embodiment, and is subjected to metal organic chemical vapor deposition (MOCVD).
Method). Oxidizing atmosphere at reduced pressure (1 Torr) (oxygen flow rate 50 sccm (standard cc per
minute)), the substrate temperature is set to 850 ° C. By leaving this state for 500 seconds, a silicon thermal oxide film of 0.5 nm is formed.

Next, titanium tetraisopropoxide (Ti- (OC ₃ H ₇ ) ₄ ) is used as an organometallic gas and deposited at a flow rate of 5 sccm for 100 seconds to form a 10 nm titanium oxide film (TiO ₂ ). Next, arsenic is ion-implanted. Further, a monosilane (SiH ₄ ) gas and a nitrous oxide (N ₂ O) gas are introduced to form a 0.5 nm silicon oxide film. The formed titanium oxide film has a rutile crystal structure and is a dense high dielectric constant film. By this manufacturing method, a gate insulating film having a laminated structure of three layers having an effective film thickness of 2 nm by electrical measurement is formed.

FIG. 1 is a structural diagram of a MOSFET using this gate insulating film. FIG. 11 is an energy band diagram of a cross section taken along line AB in FIG. 1 when no gate voltage is applied. As shown. FIG. 12 shows an energy band diagram corresponding to FIG. 11 when a positive voltage is applied to the gate. Since the gate insulating film of the MOSFET itself is positively charged, the threshold voltage can be reduced.

According to the method of the present invention, it is not necessary to implant a threshold adjusting impurity into the channel region. For this reason, the scattering probability of the conductive carriers to the ionized impurities is suppressed low, and the carrier mobility can be kept high. Therefore,
The operating speed of the MOSFET can be kept high.

(Embodiment 3) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
In the structure of the insulating film shown in the first embodiment, the silicon oxide film 1 is provided also on the gate electrode 3 side. However, when the leakage current between the gate electrode 3 and the silicon substrate 8 can be ignored, The silicon oxide film 1 can be omitted. This makes it possible to reduce the thickness of the gate insulating film 11, and
Suitable for high-speed operation of T. FIG. 6 shows an energy band diagram of a cross section along the line AB in FIG. 5 when no gate voltage is applied. Since the electrons 13 escape from the insulating film to the interface of the gate insulating film 11, the gate insulating film 11 is positively charged, and accordingly, the threshold voltage decreases and the concentration of the conductive carriers increases.

The structure of the gate insulating film 11 as described above is as follows.
After a silicon oxide film having a thickness of 2 nm is formed in the same manner as in the first embodiment, the silicon oxide film can be formed by oxynitriding in an oxynitriding furnace. The processing method uses a substrate temperature of 10
This is a method in which nitrogen monoxide (NO) gas diluted to 5% with nitrogen at 00 ° C. is allowed to stand for 20 minutes in an atmosphere in which a flow rate of 3 SLM is flowing. At this time, oxidation proceeds simultaneously with nitridation, so that the thickness of the insulating film is slightly increased to 2.5 nm. Although the introduced nitrogen atoms originally tend to precipitate at the interface between the silicon oxide film 1 and the silicon substrate 8, the oxidation proceeds at the same time.
Along the section of line AB from A to B, the buried insulating film 6, the gate electrode 3, the silicon oxynitride film 2 (2n
m), silicon oxide film 1 (0.5 nm), silicon substrate 8
Is formed.

(Embodiment 4) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
The present invention is the same as the embodiment shown in Embodiment 3 except for the materials used for the gate insulating film 11 and the gate electrode 3. The silicon substrate is cleaned and element-separated as described in the first embodiment, and is introduced into a chamber where electron beam evaporation (EB evaporation) can be performed. High vacuum in chamber (10 ^-7 Torr)
In this state, the substrate temperature is set to 650 ° C. The silicon substrate is irradiated with an ozone (O ₃ ) jet, and left in this state for 30 minutes to form a silicon oxide film 1 having a thickness of 0.5 nm.

Next, a high-purity (99.99%) titanium oxide (TiO ₂ ) target is irradiated with an electron beam to deposit a titanium oxide film 18 on the silicon oxide film.
Electron beam emission current is 45 mA, deposition time is 8
In this case, a 10 nm-thick titanium oxide film 18 is formed.

After arsenic is ion-implanted, 200 nm-thick tungsten (W) is deposited on the gate electrode by sputtering in another chamber. The cross section of the MOSFET shown in FIG. 5 in which the gate insulating film and the gate electrode are formed as described above shows that the buried insulating film 6, the gate electrode 3, the titanium oxide film 18 (10 nm) The structure has a silicon oxide film 1 (0.5 nm) and a silicon substrate 8. The formed titanium oxide film has an anatase crystal structure and is a dense high dielectric constant film. According to this manufacturing method, a gate insulating film having a laminated structure of two layers with an effective film thickness of 1.5 nm by electrical measurement is formed.

FIG. 6 shows an energy band diagram of a cross section taken along line AB in FIG. 5 when no gate voltage is applied. Since the electrons 13 escape from the insulating film to the interface of the gate insulating film 11 and the gate electrode 3, the gate insulating film 11 is positively charged, and the threshold voltage can be reduced accordingly, as in the case of the first embodiment. .

(Embodiment 5) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
In the structure of the insulating film shown in the first embodiment, the silicon oxide film 1 is also provided on the substrate side. However, when the leakage current between the gate electrode 3 and the silicon substrate 8 may be slightly increased, The silicon oxide film 1 can be omitted.

FIG. 8 shows an energy band diagram of a cross section taken along line AB in FIG. 7 when no gate voltage is applied. This structure reduces the thickness of the gate insulating film 11 and reduces the thickness of the MOSFE.
It is suitable for operating T at high speed. Electron 1 from insulating film
Since 3 escapes to the gate insulating film 11 interface or the gate electrode 3 on the substrate side, the gate insulating film 11 is positively charged, and accordingly, the threshold voltage decreases and the conduction carrier concentration increases.

However, the introduced nitrogen is used for the gate insulating film 11.
If it protrudes from the interface between the silicon substrate 8 and the substrate 8 side, it becomes a scatterer of the conductive carriers (in this case, the electrons 13), and the mobility may be reduced.

The structure of the gate insulating film 11 as described above is as follows.
After a silicon oxide film having a thickness of 2 nm is formed in the same manner as in the first embodiment, the silicon oxide film can be formed by oxynitriding in an oxynitriding furnace. The processing method uses a substrate temperature of 95.
This is a method in which NO gas diluted to 5% with nitrogen at 0 ° C. is allowed to stand for 40 minutes in an atmosphere flowing at a flow rate of 3 SLM. At this time, since the substrate temperature is slightly lower than in the case of Example 1, the rates of nitridation and oxidation become almost simultaneous,
As described above, a structure in which nitrogen atoms do not protrude into the silicon substrate 8 can be formed. Thus, the buried insulating film 6, the gate electrode 3, the silicon oxide film 1 (2 nm), and the silicon oxynitride film 2 (0.5 nm) from A to B along the section of the line segment AB in FIG. , A silicon substrate 8 is formed.

(Embodiment 6) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
The structure (FIG. 7) and energy band diagram (FIG. 8) of the gate insulating film of the present invention are qualitatively the same as those shown in the fifth embodiment.

A method for manufacturing the gate insulating film 11 as described above will be described below. The silicon substrate was cleaned and subjected to element isolation as described in the first embodiment, and the metal organic chemical vapor deposition (MO) was performed.
(CVD method). Decompression (1 To
The substrate temperature is set to 350 ° C. in an oxidizing atmosphere (oxygen flow rate 50 sccm) of (rr). Next, titanium tetraisopropoxide (Ti- (OC ₃ H ₇ ) ₄ ) is used as an organic metal gas and deposited at a flow rate of 5 sccm for 100 seconds to form a 10 nm titanium oxide film (TiO ₂ ). After arsenic is further ion-implanted, monosilane (SiH ₄ ) gas and nitrous oxide (N ₂ O) gas are introduced to form a 0.5 nm silicon oxide film. The gate electrode 3 uses polysilicon. The formed titanium oxide film has an anatase crystal structure and is a dense high dielectric constant film. According to this manufacturing method, a gate insulating film having a laminated structure of two layers with an effective film thickness of 1.5 nm by electrical measurement is formed.

It is to be noted that tantalum ethylate (Ta- (OC ₂ H ₅ ) ₅ ) is used as an organometallic gas for forming the gate insulating film 11 of the present invention, and a tantalum oxide film (Ta ₂ O ₅ ) is used. A desired structure can also be obtained by a deposition method.

(Embodiment 7) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
This embodiment shows a case where a silicon oxide film is used as a gate insulating film of a MOSFET and nitrogen is used as a chargeable material.
The portion of the insulating film in FIG. 1 is from A to B along the section of line AB.
Toward the buried insulating film 6, the gate electrode 3, the silicon oxynitride film 2 (3 nm), and the silicon substrate 8.

In the structure of the insulating film shown in the first embodiment, the silicon oxide film is provided on both the gate electrode 3 side and the silicon substrate 8 side, but priority is given to lower cost over leakage current from the gate electrode. In this case, the method described in this embodiment is suitable.

FIG. 2 shows an energy band diagram of a section taken along line AB in FIG. 1 when no gate voltage is applied. The electrons 13 from the gate insulating film 11 are transferred from the gate insulating film 1 on the substrate side.
To escape to one interface, the gate insulating film 11 is positively charged,
As a result, the threshold voltage decreases and the concentration of the conductive carriers increases. However, if the introduced nitrogen protrudes from the insulating film-substrate interface to the substrate side, it becomes a scatterer of conductive carriers (electrons 13 in this case), and the mobility may be reduced.

The method for forming such an insulating film is described below. After immersing the silicon substrate in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed with a hydrofluoric acid aqueous solution, and immediately thereafter, a nitriding treatment is performed in a nitriding furnace. The processing condition is a method in which the substrate is left for 20 minutes in an atmosphere in which an ammonia (NH ₃ ) gas diluted to 5% with nitrogen is flowing at a flow rate of ₃ SLM at a substrate temperature of 800 ° C. By this method, a nitride film having a uniform nitrogen concentration (film thickness 2n)
m) is formed.

(Embodiment 8) One embodiment of the present invention is shown in FIG.
This will be described with reference to the cross-sectional view of the n-type MOSFET shown in FIG.
This embodiment shows a case where a silicon oxide film is used as a gate insulating film of a MOSFET and a titanium oxide film is used as a charging material. The buried insulating film 6, the gate electrode 3, the titanium oxide film 18 (10 nm), the silicon substrate 8 and the gate insulating film shown in FIG.
It has become. The structure of the gate insulating film 11 employed in this embodiment is the same as that shown in the seventh embodiment.

FIG. 2 shows an energy band diagram of a cross section taken along line AB in FIG. 1 when no gate voltage is applied.

A method for manufacturing the above gate insulating film 11 will be described below. The silicon substrate is cleaned and element-separated as described in the first embodiment, and is introduced into a chamber where electron beam evaporation (EB evaporation) can be performed. The inside of the chamber is in a high vacuum (10 ⁻⁷ Torr) state, and the substrate temperature is room temperature.
The silicon substrate is irradiated with an ozone (O ₃ ) jet, and left in this state for 30 minutes to form a silicon oxide film 1 having a thickness of 0.5 nm. Next, a high purity (99.99%) titanium oxide (TiO ₂ ) target is irradiated with an electron beam to deposit a titanium oxide film 18 on the silicon oxide film. Assuming that the electron beam emission current is 45 mA and the deposition time is 8 minutes, a 10 nm-thick titanium oxide film 18 is formed.

Next, the silicon substrate is transferred to a chamber of a rapid thermal annealing (RTA) apparatus, and an oxygen flow rate of 50
Annealing is performed at an annealing temperature of 950 ° C. and an annealing time of 240 seconds in an atmosphere of sccm. After ion implantation of arsenic, a 200 nm-thick molybdenum (Mo) film is deposited on the gate electrode by sputtering in another chamber. The formed titanium oxide film has an anatase crystal structure and is a dense high dielectric constant film. With this manufacturing method, a gate insulating film having a single-layer structure with an effective film thickness of 1.0 nm obtained by electrical measurement is formed.

In the present invention, molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN) or the like can be deposited as the gate electrode 3 in addition to molybdenum.

(Embodiment 9) An embodiment of the present invention will be described with reference to the cross-sectional view of the MOSFET shown in FIG.
A case where a silicon oxide film is used as a gate insulating film of a MOSFET and gallium is used as a chargeable material will be described. The insulating film portion in FIG. 3 includes a buried insulating film 6, a gate electrode 3, a gallium-implanted silicon oxide film 15, and a silicon substrate 8 from A to B along the cross section of the line segment AB. Arsenic is ion-implanted into the substrate as a channel stopper 7 to prevent a leak current between the source and the drain.

Since the gallium atom is a group III element, there is a shortage of electrons in the structure of the atom whose unit is tetravalent, and a hole is generated. In fact, when gallium is implanted into a silicon substrate, it becomes a p-type dopant.

FIG. 4 shows an energy band diagram of the cross section along the line AB in FIG. 3 when no gate voltage is applied. This hole 17 is excited to generate the gate insulating film 1.
1 Reach the interfaces on both sides. Therefore, the gallium-implanted silicon oxide film 15 is negatively charged. The threshold voltage of the MOSFET becomes higher (absolute value becomes smaller) by the charged amount.

The method for forming such an insulating film will be described below. After the n-type silicon substrate is immersed in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed with a hydrofluoric acid aqueous solution, and then a field oxide film is formed. The substrate temperature is heated to 850 ° C. in a wet oxidation atmosphere at a rate of / min. To form a silicon oxide film having a thickness of 14 nm. Next, gallium was added to a depth of 14
ion implantation, and then in a nitrogen atmosphere for 1
Anneal at 000 ° C. Then, the silicon oxide film 1 is removed by 10 nm using a fluorine-based etching gas. The remaining silicon oxide film is 4 nm thick, and gallium atoms are almost uniformly spread in the film.

(Embodiment 10) One embodiment of the present invention will be described with reference to the cross-sectional view of the MOSFET shown in FIG. A case where a silicon oxide film is used as a gate insulating film of a MOSFET and a titanium oxide film to which gallium is added as a charging material is shown. The portion of the insulating film in FIG. 3 extends from A to B along the cross section of the line segment AB from the buried insulating film 6,
The gate electrode 3, the gallium-implanted titanium oxide film 18, and the silicon substrate 8 are provided. Arsenic is ion-implanted into the substrate as a channel stopper 7 to prevent a leak current between the source and the drain. The structure of the MOSFET of the present invention is shown in the ninth embodiment.

A method for forming such an insulating film will be described below. After the n-type silicon substrate is immersed in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed with a hydrofluoric acid aqueous solution, and then a field oxide film is formed. To be introduced. The inside of the chamber is in a vacuum (1 Torr) state, and the substrate temperature is room temperature.
High purity (99.99%) titanium oxide (Ti
O ₂ ) The target is irradiated with oxygen radicals to deposit a titanium oxide film 18 on the silicon substrate. Next, gallium is ion-implanted.

Next, the silicon substrate is transferred to a chamber of a rapid thermal annealing (RTA) apparatus, and an oxygen flow rate of 50
Annealing is performed at an annealing temperature of 950 ° C. and an annealing time of 240 seconds in an atmosphere of sccm. For the gate electrode, molybdenum (Mo) having a thickness of 200 nm is deposited in the same chamber by a sputtering method. The formed titanium oxide film 18 has an anatase crystal structure and is a dense high dielectric constant film.
By this manufacturing method, an effective film thickness of 1.0 nm by electric measurement
Is formed.

In the present invention, molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), or the like can be deposited as the gate electrode 3 in addition to molybdenum.

[0055]

According to the present invention, the threshold voltage can be adjusted by introducing a chargeable material into the gate insulating film 11, so that the mobility of the conductive carriers can be kept high.

[Brief description of the drawings]

FIG. 1 shows an n-type MO as a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an SFET.

FIG. 2 is an energy band diagram of a cross section along a line segment AB of the semiconductor device shown in FIG.

FIG. 3 shows a p-type MO as a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an SFET.

FIG. 4 is an energy band diagram of a cross section along a line segment AB of the semiconductor device shown in FIG. 3;

FIG. 5 shows an n-type MO as a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an SFET.

6 is an energy band diagram of a cross section taken along a line AB of the semiconductor device shown in FIG. 5;

FIG. 7 shows an n-type MO as a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an SFET.

8 is an energy band diagram of a cross section along a line AB of the semiconductor device illustrated in FIG. 7;

FIG. 9 is an n-type MO as a semiconductor device according to one embodiment of the present invention;
FIG. 3 is a cross-sectional view of an SFET.

FIG. 10 is a sectional view of a conventional n-type MOSFET.

FIG. 11 is an energy band diagram of a cross section along a line AB of the semiconductor device shown in FIG. 10;

12 is an energy band diagram of a cross section along a line AB of the semiconductor device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon oxide film, 2 ... Silicon oxynitride film, 3 ... Gate electrode, 4 ... Source, 5 ... Drain, 6 ... Buried insulating film, 7 ... Channel stopper, 8 ... Silicon substrate, 9 ... Element isolation insulating film, 10 ... Channel region, 11 gate insulating film, 12 positive charge, 13 electron, 14 Fermi surface of electrode, 15 gallium-implanted silicon oxide film, 16 negative charge, 17 hole, 18 titanium oxide film, 19 ... Fermi surface of the substrate.

Continued on the front page (72) Inventor Shinpei Tsujikawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5F040 DA06 ED02 ED03 ED05 FC15

Claims (9)

[Claims] A gate electrode provided on a semiconductor substrate having a first conductivity type via a gate insulating film; and a diffusion layer region of a second conductivity type provided separately in the semiconductor substrate. In a semiconductor device, a whole or a part of a gate insulating film is charged to a first conductivity type. 2. The semiconductor device according to claim 1, wherein
The impurity concentration of the region where the conductive type carrier flows is 10 ¹⁶ /
A semiconductor device having a size of not more than cm ³ . 3. The semiconductor device according to claim 1, wherein the gate insulating film has a laminated structure, and includes at least two layers of a layer made of a material to be a first conductive type charging material and another layer. A semiconductor device comprising: 4. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a material to be a conductive type charging material is a silicon oxide film to which nitrogen atoms are added. 5. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a material serving as a conductive type charging material is a silicon nitride film. 6. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a material to be a conductive type charging material is a titanium oxide film. 7. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a material serving as a conductive charging material is a tantalum oxide film. 8. A semiconductor device having a first conductivity type, comprising a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, and a diffusion layer region of a second conductivity type provided separately in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: imparting chargeability to a first conductivity type to all or a part of a gate insulating film. 9. The semiconductor device according to claim 8, wherein:
Forming a silicon oxide film to which nitrogen atoms are added, a silicon nitride film, a titanium oxide film, or a tantalum oxide film in order to form an insulating film having conductivity-type chargeability; Production method.