JPH01199477A - Manufacture of zener diode - Google Patents

Abstract

PURPOSE:To decrease a base layer in a superficial carrier concentration so as to obtain a Zener diode excellent in reliability in a long operation by a method wherein a second conductivity type impurity and a first conductivity type impurity are introduced into a first conductivity type semiconductor in such a manner that the first conductivity impurity is introduced shallower and lower than the second conductivity impurity in concentration. CONSTITUTION:A mask layer 22 is formed on a first conductivity type semiconductor layer 21, and a base layer forming opening 23 is formed in a part of the layer 22. Next, a second and a first conductivity type impurity are introduced into the semiconductor layer 21 through the opening 23 in such a manner that the first conductivity type impurity is introduced shallower and lower than the second conductivity type in concentration to form a second conductivity base layer 26 low in a superficial carrier concentration on the semiconductor layer 21. Then, a first conductivity type emitter layer 30 is formed inside the base layer 26. For instance, boron is injected into the N-type silicon substrate 21 by 1-2X10<14>cm<-2> in a dose, which is subjected to a heat treatment to form an injected base layer 24. Then, phosphorus 25 is injected into the injected base layer 24 by a 1-5X10<13>cm<-2> in a dose, which is subjected to a heat treatment so as to make the injected base layer 24 re-diffused for the formation of the base layer 26.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a Zener diode in which the base-emitter junction is used in reverse bias.

(Prior Art) A conventional method for manufacturing a Zener diode will be explained with reference to FIG.

First, as shown in Figure 2 (al), the impurity concentration lXl0
An oxidized JJ stack with a thickness of about 3,000 to 5,000 layers is formed on a phosphorus-doped N-type silicon substrate or an epitaxial layer 1 of about am, and a part of it is etched away by photolithography to form a base diffusion pattern 3, and then,
From the pattern 3, boron was implanted using the ion implantation method at a dose of 1 to 2×10 an and an energy of 40 kaV.
Then, 900°C.

Heat treatment is performed in an N2 atmosphere for about 30 minutes to form the base implant layer 4.
form.

Next, heat treatment is performed at 900°C in a steam atmosphere for about 60 minutes to re-diffuse the base implanted layer 4, resulting in a bonding depth of 0.5 to 0.6μ as shown in FIG. 2(b).
A base layer 5 of m is formed. At this time, about 2,000 to 3,000 layers of oxide film 6 are formed on the surface of base layer 5.

Next, as shown in FIG. 2(c), a portion of the oxide films 6 and 2 on the surface of the base layer 5 and the surface of the N-type substrate or epitaxial layer 1 are etched away by photolithography to form the emitter diffusion pattern 7 and the surface of the epitaxial layer 1. A collector diffusion pattern 8 is formed.

Next, arsenic is ion-implanted from the pattern 7.8 at a dose of I x 10 ''em-2 and an energy of 4.
By implanting at 0 kaV and then performing heat treatment at 950° C. in a N2 atmosphere for about 30 minutes, an emitter layer 9 and a collector layer 10 having a junction depth of 0.25 μm are formed as shown in FIG. 1(d).

Next, as shown in FIG. 1 et, a portion of the oxide film 6 is etched away by photolithography to form a base contact hole 11 .

Next, the emitter wiring 12 and the base wiring are formed by vapor depositing aluminum and patterning it by photolithography.
Forms collector acid $13. With the above steps, the Zener diode is completed.

FIG. 4 shows the carrier concentration distribution in the base layer of the conventional Zener diode manufactured in this manner. The Zener voltage of the Zener diode formed in the base layer with this concentration distribution is approximately 5.4V.

This voltage is a value determined by electric field concentration on the emitter layer at the surface of the base layer, and the surface electric field at this time is 1.41×10'V/li.

(Problem to be Solved by the Invention) However, when the Zener voltage is determined at the surface of the base layer, as in the conventional Zener diode described above,
Due to the generation of hot carriers, electrons are trapped in the oxide film near the emitter junction, resulting in a phenomenon in which the electric field concentration at the surface weakens and the Zener voltage increases.

In other words, there is a problem of characteristic fluctuations during long-term operation.

Therefore, in order to eliminate the problem of Zener voltage fluctuation due to electron trapping and obtain a Zener diode with excellent 4M reliability for long-term operation, the carrier concentration on the surface of the base layer is lowered, and the electric field is not concentrated on the surface. The practice is to generate electric field concentration in a deep part of the surface and to determine the Zener voltage in the deep part.

For this purpose, there is a method of increasing the impurity concentration in a region deeper than the surface by ion implantation, as disclosed in, for example, Japanese Patent Application Laid-Open No. 58-85571.

However, in this method, if heat treatment is performed at high temperature for a long time after ion implantation, the ion implantation profile will be redistributed and the surface concentration will increase.

Therefore, when forming a deep base layer, it is necessary to dope impurities to a deep position by ion implantation, so the implantation energy must be extremely high. For example, in order to form a base layer with a junction depth of 2 μm or more, energy of 400 keV or more is required. However, with such high energy, it is necessary to make the mask material very thick for selective implantation, and if photoresist is used, the pattern may be distorted due to the effect of temperature rise due to the implantation power. (Considering mass production, a beam current of 1 to 2 mA is required, and in this case, the implant power is 4 mA.)
00~800W or more).

That is, the method using ion implantation has a drawback that the degree of freedom in forming conditions for the base layer is very small, and the performance is limited in integrated circuits in which many types of elements are formed on the same substrate.

As another method, as disclosed in JP-A-56-36171, a thick oxide film is formed in the base layer forming step, and this oxide film absorbs boron, which is an impurity for forming the base layer, and the semiconductor substrate is A method of lowering the boron concentration at the surface has also been proposed.

However, with this method, the thick oxide film must be removed by etching in the photolithography process for patterning the region where the next emitter will be formed, resulting in a large side etch, which reduces the accuracy of emitter pattern formation. There is. The emitter pattern accuracy affects the forward bias voltage accuracy of the emitter junction of a Zener diode or transistor, and when used in a linear circuit, this decrease in accuracy causes the circuit characteristics to deteriorate and becomes unusable. It ends up. Further, when a pattern is formed on a thick oxide film layer, the step coverage of a wiring material such as aluminum is reduced due to the difference in thickness, resulting in the problem of wire breakage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a Zener diode that can solve the above-mentioned problems, lower the surface carrier concentration of the base layer, and obtain a Zener diode with excellent reliability for long-term operation.

(Means for Solving the Problems) In the present invention, an impurity of a second conductivity type and an impurity of a first conductivity type are added to a semiconductor layer of a first conductivity type, and the impurity of the first conductivity type is an impurity of a second conductivity type. By introducing the carrier to a shallower depth and at a lower concentration, a base layer of the second conductivity type is formed in the semiconductor layer by lowering the carrier concentration at the surface.

(Function) As described above, the impurity of the opposite conductivity type (first conductivity type) is added together with the impurity of the second conductivity type for forming the base layer, and the impurity is shallower and has a lower concentration than the impurity of the second conductivity type. When introduced at a high concentration, the base layer is formed with a lower carrier concentration at the surface due to the influence of the impurity of the opposite conductivity type.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view of an embodiment of the present invention.

First, as shown in Figure 1 (al), the impurity concentration lXl0
An oxide film 22 of approximately 3,000 to 5000 nm is formed on a phosphorus-doped N-type silicon substrate or epitaxial layer (in this case, an N-type silicon substrate) 21, and a part of it is etched away by photolithography. forming an opening 23;
The dose of boron is 1~2X1 by ion implantation method.
0 cm and an energy of 40 keV into the substrate 21, then at 900°C.

A base implant @24 is formed on the substrate 21 by performing heat treatment in an N2 atmosphere for about 30 minutes. Here, according to the implantation conditions, boron has a peak depth of 1300 mm. Moreover, by subsequently performing the heat treatment,
The base implantation calendar 24 is formed to a depth of 0.35 to 0.4 μm.

Next, as shown in FIG. 1(b), phosphorus 25 is implanted into the base implantation layer 24 through the same opening 23 as in the case of boron, using an ion implantation method at a dose of 1 to 5×10C111° and an energy of 40 ksV. .

At this time, phosphorus has a peak at a depth of 500 people.

Next, heat treatment is performed at 900° C. in a steam atmosphere for about 60 minutes to re-diffuse the base implant layer 24, so that the bonding depth is 0.5 to 0.6 as shown in FIG. 1 (c1).
A base layer 26 having a thickness of μm is formed. At this time base JI2
6 is formed by lowering the carrier concentration on the surface due to the influence of the phosphorus implanted at a shallower depth and lower concentration than the boron for forming the base layer 26. Further, at this time, two oxide films of approximately 2,000 to 3,000 layers are laminated on the surface of the base layer 26.

Next, as shown in FIG. 1(d), a part of the oxide film 27, 22 on the surface of the base layer 26 and the N-type substrate 21 is etched away by photolithography to form an opening 28 for forming an emitter and a collector. An opening 29 is formed for the purpose.

Next, arsenic is ion-implanted through the openings 28 and 29 at a dose of IX10 am and an energy of 4'OkeV.
By implanting the emitter layer 30 into the base layer 26 with a junction depth of about 0.25 μm, as shown in FIG. , and a collector layer 31 are formed in the substrate region, respectively.

Next, as shown in FIG. 1(g), a portion of the oxide film 27 is etched away by photolithography to form a base contact hole 32.

Next, by depositing aluminum and patterning it by photolithography, as shown in FIG. 1(g),
An emitter wiring 33 and a base/collector wiring 34 are formed. Here, the emitter wiring 9133 is located at the opening 28.
Also, the base-collector wiring 34 connects the base layer 26 and the collector layer 3 through the base contact hole 32 and the opening 29.
1 to short-circuit them. With the above steps, a Zener diode with a Zener voltage of 5 to 6 V is completed.

FIG. 3 shows an example of the carrier concentration distribution in the base layer of the Zener diode manufactured in this manner.

As is clear from the figure, the carrier concentration on the surface has decreased due to the influence of phosphorus ion implantation, and the
, at a voltage of 4v, the electric field at the surface is 1,17X1G'V
/cd, no electric field concentration occurs, the electric field concentration at the surface is relaxed, and the Zener voltage is determined in the deep part.

In the above embodiment, an example of forming a base layer with a junction depth of 05 to 0.6 μm was shown, but 9 in FIG. 1(e)
After treatment at 00℃, continuous N treatment at 1050℃ for about 60 minutes
By performing the drive-in process in two atmospheres, a deep base layer with a junction depth of about 1.8 to 2.5 μm can be formed.

Further, the order of boron and phosphorus ion implantation can be reversed, and the impurities are not limited to boron and phosphorus.

Furthermore, the introduction of impurities is not limited to ion implantation, and thermal diffusion methods can also be used.

(Effects of the Invention) As explained above, according to the method of the present invention, the carrier concentration at the surface of the base layer is lowered by introducing impurities of opposite conductivity type, which improves emitter pattern accuracy by forming a thick oxide film. It is possible to easily form a highly reliable Zener diode with no change in Zener voltage by eliminating voltage drop and breakage in aluminum wiring, and it can also be applied to high-precision linear circuits. In addition, since it is possible to form a deep base layer by heat treatment without destroying the carrier concentration distribution where the carrier concentration is low at the surface, it is possible to introduce impurities shallowly even when obtaining a deep base layer, and the introduction method is When ion implantation is used, it is possible to perform implantation with low energy, so it can be expected to improve mass productivity.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing an embodiment of the Zener diode manufacturing method of the present invention, FIG. 2 is a process cross-sectional view showing a conventional Zener diode manufacturing method, and FIGS.
The figures are characteristic diagrams showing the carrier concentration distribution of the base layer according to the method according to an embodiment of the present invention and the conventional method, respectively. 21... N-type silicon substrate, 22... Oxide film, 23
...Opening portion, 24...Base implantation layer, 25...
Phosphorus, 26...Base layer, 30...Emitter layer. Figure 2 Abusive power crest ρ$/) Uty, F Ryoza Cpm'J approximate contact & face power ゛8/) Su 1 shrine

Claims (1)

[Scope of Claims] (a) forming a mask layer on a semiconductor layer of a first conductivity type and forming an opening for forming a base layer in a part of the mask layer; (b) passing the semiconductor layer through the opening; By introducing an impurity of the second conductivity type and an impurity of the first conductivity type into the layer, the impurity of the first conductivity type being shallower and at a lower concentration than the impurity of the second conductivity type, the surface of the semiconductor layer is A method for manufacturing a Zener diode, comprising: (c) forming a base layer of a second conductivity type by lowering carrier concentration; and (c) forming an emitter layer of a first conductivity type in the base layer.