JPH01198078A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it easy to judge whether recess etching quantity is suitable, and enable the control of recess etching quantity, by forming a monitoring element together with the main part of a semiconductor device, on a semiconductor substrate. CONSTITUTION:Real elements as the main part of a semiconductor device are formed in a chip region R. A monitoring element to monitor recess etching quantity is formed in a chip region M. In the respective chip regions R and M, the respective mesa patterns are simultaneously formed. Then in the respective regions R and M, ohmic electrodes 4, 4', and extending electrode parts 5, 5' are formed, respectively. The extending electrode parts 5 and 5' extend from the ohmic electrode 4, 4' to the side surface and on a substrate 1. Then a cap film 2 is formed. Further, in the region M, a gate pattern 6 having aperture parts 9, 9' on the extending electrode parts 5, 5' is used at the same time. A recess trench 8 is formed by recess etching. The recess etching quantity can be judged by applying a specified voltage between the measuring aperture parts 9, 9', and monitoring the decrease quantity of monitoring current between the aperture parts, and the etching quantity can be controlled.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for controlling the amount of recess etching in a group compound semiconductor.

(0) Prior Art Generally, in the case of a semiconductor device having an epitaxial layer and a recessed structure, such as a Ga As MESFET, the drain current tllJIj is controlled by controlling the impurity concentration of the active layer and the amount of recess etching. Generally, wet etching is used for this recess etching, and to control the amount of etching, a part (chip) of the substrate is divided after forming the ohmic electrode, and recess etching is performed while monitoring this, to ensure proper recess etching. A method is used to calculate the amount of etching.

(c) Problems to be Solved by the Invention However, in such a method, since a part of the substrate is divided, it is necessary to handle the wafer as an irregularly shaped wafer, which may lead to an increase in the number of manufacturing steps. In addition, if you want to know the amount of recess etching after recess etching, it is necessary to remove the photoresist, cap film, etc. stacked on the epitaxial layer, which requires a lot of man-hours. Even if the amount of etching is not appropriate, there are drawbacks such as the inability to immediately determine whether the recess etching layer is appropriate or not using an element on the substrate.

Therefore, in order to solve these drawbacks, the present invention provides a method for manufacturing a semiconductor device that does not require dividing the substrate, can immediately determine whether a recess etching layer is suitable or not after recess etching, and can control the amount of recess etching. This is one of its purposes.

(d) Means for Solving the Problems This invention forms an epitaxial layer on one compound semiconductor substrate, separates the layers between elements, then forms a large number of ohmic electrodes, and then When manufacturing a semiconductor device main body in which a recess groove for a gate electrode is formed at a position, at least one arbitrary ohmic electrode among a large number of ohmic N poles is different from the semiconductor device main body. A monitoring ohmic electrode having an extension portion is formed on the compound semiconductor substrate exposed by the epitaxial layer or element isolation, and the depth of the recess groove is measured by applying a monitor voltage to the monitoring ohmic electrode. This is a method of manufacturing a semiconductor device in which a desired recess groove is formed by monitoring the process.

That is, the present invention provides a method for manufacturing a semiconductor device having an epitaxial layer on a compound semiconductor substrate and having a recess structure, in which an appropriate number of monitoring elements are arranged at appropriate locations on the substrate. The monitoring element includes an extension layer 8i (monitoring ohmic electrode) for measuring the amount of recess etching on the main body of the semiconductor device (actual element), and makes it possible to measure the amount of recess etching during and after recess etching. It has an open pattern on the extended electrode.

(e) Since the monitoring element is formed on the working semiconductor substrate at the same time as the main body of the semiconductor device, the recess etching layer can be controlled without destroying the substrate, thereby reducing the number of manufacturing steps. Since the amount of recess etching can be monitored even after recess etching, the recess etching opening can be controlled more accurately, and the control can be simplified and the amount can be optimized. Furthermore, even in cases where it is difficult to control the amount of recess etching using conventional methods due to poor uniformity of the epitaxial layer, by arranging a monitoring element on the substrate, it is possible to control the amount of recess etching more appropriately.

(f) Example The present invention will be described in detail below based on embodiments shown in the figures.

Note that this invention is not limited by this.

When forming a GaAs MES FET, first, as shown in FIGS.
A growth layer (epitaxial layer) 3 is formed. This growth layer 3 includes, for example, a buffer layer made of high-purity non-doped GaAs, a Si doped N-G
Channel layer consisting of aAs and 3i doped N◆G
a Constructed by stacking contact layers made of As. Then, a mesa etching pattern (hereinafter abbreviated as mesa pattern) (not shown) is formed on this growth layer 3 using a photoresist.

At this time, GaASFET (
Mesa patterns are formed at the same time in a first chip region R in which a device, hereinafter referred to as an actual device, is formed and in a second chip region M in which a monitor element for monitoring the amount of recess etching, which will be described below, is formed.

That is, in the first chip region R, as shown in FIG. 1(a), the growth layer 3 is etched using the actual device mesa pattern as a mask material, and at the same time, in the second chip in region M, as shown in FIG. As shown in +b>, the growth layer 3 is etched using the mesa pattern for the monitor element as a mask material, thereby separating the elements, and the photoresist for mesa etching is removed using an organic solvent. Thereafter, conventional photolithography, electrode deposition, alloy processing, etc. are performed to form ohmic electrodes 4.4' (see ω in FIG. 1), ohmic electrodes 4.4' in the first and second chip regions R and M, respectively. An extended electrode section 5 extending from the side surface thereof and onto the Ga As I plate 1.
5" (see Figure 1+b>).

Then cap l! form 2. This cap film is made of silicon nitride, for example.

Further, in FIGS. 1C and 1D, a gate formation pattern (hereinafter referred to as gate pattern) 6 having a gate formation opening 7 made of photoresist is used, and FIG. As shown in FIG. 3, in the second chip region 1111M, a gate pattern 6 having an opening 9.9' above the extended electrode portion 5.5 is also used.

Thereafter, dry etching is performed using the gate pattern 6 as a mask material to open the cap film 2, and form an opening 7 for gate formation and an opening 9 for measuring the amount of recess etching.
9- is formed. After that, using the cap film 2 as a mask material, a part of the contact layer and channel layer of the growth layer 3 is etched with an etchant (for example, a phosphoric acid etchant).
The recess groove 8 is formed by wet etching, that is, recess etching using a etchant. Finally, a gate electrode (not shown) is deposited using an electron beam or the like, and then the photoresist is removed using an organic solvent to form Ga in the first chip region R.
Obtain As FET.

Next, a method of controlling the amount of recess etching will be explained.

The monitoring element has an extended electrode portion 5.5- for measuring the amount of recess etching, and a measurement opening 9.9' that makes it possible to measure the amount of recess etching during and after recess etching. Figure (see d+)
. As a result, after the recess groove 8 is formed, a predetermined voltage is applied between the measurement openings 9 and 9', and the amount of decrease in the monitor current value between the openings is monitored to determine the amount of recess etching. It is possible to judge whether the etching (especially the depth of the recess groove) is appropriate or not, and if the amount of etching is insufficient, further etching can be added.

Moreover, by selecting and arranging a predetermined number of monitor elements in the second chip region M at appropriate locations among the chips on the QaAs substrate 1, it is possible to control the amount of recess etching more accurately. It is.

In this way, in this example, the monitor element was formed on the GaAs substrate 1 at the same time as the actual element, and this monitor element was used to monitor the recess etching amount even after the recess groove was formed. The amount of recess etching can be controlled without dividing the As substrate into chips, and control of drain current can be improved.

FIGS. 2 and 3 show another embodiment of the present invention in which a monitor element with a recess etching ω having a recess groove size different from that of the actual element is formed on a substrate.

FIG. 3 shows a monitor element having a submicron gate length L1, which is the same as the actual element, and FIG. 2 shows a monitor element having a gate length L2, which is larger than the actual element (Ll<12).

That is, in FIG. 2.3, when forming the photoresist 6 for the gate electrode and the opening 19.19'' of the silicon nitride (cap film) 2, the monitor element having the gate length L1 suffers from a decrease in yield and a recess. While the line width shift of the gate length LL, which contributes to fluctuations in the etching amount monitoring current, is large, in the case of a monitor element with a gate length of 2, by setting the gate length of 2 to an appropriate value, the yield can be reduced to approximately 100. %, the above line width shift is also suppressed within the allowable value,
Accordingly, the number of monitor patterns on the GaAS substrate 1 can be reduced, and the number of monitor elements is reduced, making it possible to reduce the number of work steps and improve the accuracy of controlling the amount of recess etching. In this example, by forming a recess groove larger than the actual element in the recess etching amount monitoring element, for example, Q
a In the case of AsFET, the yield when forming the gate pattern of the monitor element is improved, and the variation in gate length line width is suppressed, so the variation in the drain current of the monitor during recess etching is suppressed, and accurate recess etching is possible. In addition to being able to control the amount, it is also possible to reduce the number of monitoring devices, reduce the number of work steps, and improve the device yield per substrate.

(g) Effects of the Invention As described above, according to the present invention, the amount of recess etching can be accurately and easily controlled without dividing the substrate, which simplifies the work process and improves work efficiency. Furthermore, it has great effects such as reducing the defective rate associated with recess etching and making the characteristics determined by the amount of recess etching uniform during mass production.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention.
FET manufacturing process explanatory diagrams, Figures 2 and 3 are based on other embodiments of this invention! ! FIG. 2 is an explanatory diagram of the structure of the fabricated monitor element. 1...Ga AS substrate, 2...Silicon nitride (cap Il!
), 3...Epitaxial layer, 4.4'...Ohmic electrode, 5.5'...
...Extension electrode part, 6...Photoresist for gate pattern, 7.
...Opening for gate formation, 8...Recess groove, 9.9', 19.19=...Opening for measurement. Figure 2

Claims (1)

[Claims] 1. Forming an epitaxial layer on one compound semiconductor substrate, forming a large number of ohmic electrodes after separating the elements in that layer, and then forming a recess groove for a gate electrode at a predetermined position between the ohmic electrodes. When manufacturing a semiconductor device main body consisting of a large number of ohmic electrodes, at least one arbitrary ohmic electrode is placed on the compound semiconductor substrate exposed through an epitaxial layer or element isolation, unlike the semiconductor device main body. A monitoring ohmic electrode having an extending portion is formed, and the depth of the recess groove is monitored while being measured by applying a monitor voltage to the monitoring ohmic electrode, and a desired recess groove is formed. A method for manufacturing a semiconductor device.