JPH01197846A - エラー探知回路 - Google Patents

エラー探知回路

Info

Publication number
JPH01197846A
JPH01197846A JP63285944A JP28594488A JPH01197846A JP H01197846 A JPH01197846 A JP H01197846A JP 63285944 A JP63285944 A JP 63285944A JP 28594488 A JP28594488 A JP 28594488A JP H01197846 A JPH01197846 A JP H01197846A
Authority
JP
Japan
Prior art keywords
error
counter
signal
trigger
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63285944A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0563823B2 (enExample
Inventor
David Meltzer
デビツド・メルザ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH01197846A publication Critical patent/JPH01197846A/ja
Publication of JPH0563823B2 publication Critical patent/JPH0563823B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Manipulation Of Pulses (AREA)
JP63285944A 1988-01-27 1988-11-14 エラー探知回路 Granted JPH01197846A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/148,826 US4852095A (en) 1988-01-27 1988-01-27 Error detection circuit
US148826 1988-01-27

Publications (2)

Publication Number Publication Date
JPH01197846A true JPH01197846A (ja) 1989-08-09
JPH0563823B2 JPH0563823B2 (enExample) 1993-09-13

Family

ID=22527564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63285944A Granted JPH01197846A (ja) 1988-01-27 1988-11-14 エラー探知回路

Country Status (3)

Country Link
US (1) US4852095A (enExample)
EP (1) EP0325727A3 (enExample)
JP (1) JPH01197846A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206948A (en) * 1989-12-22 1993-04-27 Bull Hn Information Systems Inc. Bus monitor with means for selectively capturing trigger conditions
US5361267A (en) * 1992-04-24 1994-11-01 Digital Equipment Corporation Scheme for error handling in a computer system
US6185630B1 (en) 1997-02-14 2001-02-06 Advanced Micro Devices, Inc. Device initializing system with programmable array logic configured to cause non-volatile memory to output address and data information to the device in a prescribed sequence
US6389557B1 (en) * 1998-09-16 2002-05-14 Advanced Micro Devices, Inc. Freezing mechanism for debugging
US6550022B1 (en) * 1999-11-02 2003-04-15 International Business Machines Corporation Hierarchical JTAG based checkstop architecture for computer systems
US20040216003A1 (en) * 2003-04-28 2004-10-28 International Business Machines Corporation Mechanism for FRU fault isolation in distributed nodal environment
US7251748B2 (en) * 2003-09-12 2007-07-31 Sun Microsystems, Inc. System and method for determining a global ordering of events using timestamps
JP4804408B2 (ja) * 2007-04-17 2011-11-02 株式会社日立製作所 ログ解析方法及び装置
US9425802B1 (en) * 2015-05-28 2016-08-23 Altera Corporation Methods and apparatus for configuring and reconfiguring a partial reconfiguration region

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4100605A (en) * 1976-11-26 1978-07-11 International Business Machines Corporation Error status reporting
US4167041A (en) * 1977-04-05 1979-09-04 International Business Machines Corporation Status reporting
US4139818A (en) * 1977-09-30 1979-02-13 Burroughs Corporation Circuit means for collecting operational errors in IC chips and for identifying and storing the locations thereof
US4184630A (en) * 1978-06-19 1980-01-22 International Business Machines Corporation Verifying circuit operation
US4679195A (en) * 1985-04-10 1987-07-07 Amdahl Corporation Error tracking apparatus in a data processing system

Also Published As

Publication number Publication date
US4852095A (en) 1989-07-25
JPH0563823B2 (enExample) 1993-09-13
EP0325727A3 (en) 1990-10-24
EP0325727A2 (en) 1989-08-02

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