JPH01196817A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an insulator due to a charge-up phenomenon caused by ion implantation, by using a conductive film as a material of a mask pattern resistant to the ion implantation, and by interconnecting parts of the pattern throughout an entire area of a semiconductor substrate. CONSTITUTION:A mask pattern for resisting ion implantation is formed of a conductive film throughout an entire area of a semiconductor substrate. The mask pattern for resisting the ion implantation is formed for each chip, and it is made up of chip patterns 2, 3, 4 and 5 to which a pattern 1 of each chip is adjacent and patterns 6 interconnecting the chip patterns 1, 2, 3, 4 and 5 respectively. When ions are implanted in this state, a charge caused by the ion implantation can be made run off through the periphery of the semiconductor substrate. Thereby the breakdown of an insulator due to a charge-up phenomenon caused by the ion implantation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the properties and pattern shape of a mask film for ion implantation.

[Conventional technology]

In recent years, in semiconductor devices, it is necessary to advance fine patterning through scaling in order to achieve higher densities and higher speeds, so techniques using shallow diffusion layers and very thin insulating films are used. However, when these thin insulating films and shallow diffusion layers are used, the dielectric breakdown voltage of the semiconductor device is lowered, and damage to the semiconductor device due to static electricity has become a problem.

In particular, in MO8 type dynamic RAM, etc., a small amount of charge is stored in a capacitor and this charge is handled as a signal, so even as the density increases and patterns become finer, as much charge as possible is stored and large signals are generated. A very thin insulating film is used to extract the amount.

By the way, conventionally, in the manufacturing process of MO8 type semiconductor devices, the amount of introduced impurities can be accurately controlled, and since the impurities can be implanted without heating the semiconductor substrate, it is possible to form a shallow diffusion layer. Ion implantation technology is often used.

In other words, since the amount of toss can be accurately counted as the current value, the amount of transistor (MOS) is also an important parameter.
To control the impurity concentration on the surface of the semiconductor substrate, which determines TM, 1010
Impurity ions of ~1013 atoms/cni are implanted into the semiconductor substrate to obtain the desired VTM. Furthermore, the M.O.S.
) For forming source and drain diffusion layers of transistors, doping polysilicon with impurities, and forming insulators within semiconductor substrates by introducing oxygen, nitrogen, etc. into semiconductor substrates, etc.
1014~10” at ~200KeV energy
Om/ad ion implantation is performed and is used as an essential technology for semiconductor device manufacturing.

FIG. 2(a) shows the semiconductor wafer, and the second
As shown in Figure (b), a part of which is enlarged, in the case of these ion implantations, in most cases, resist with a pattern formed thereon was used as it is as a mask-resistant material for ion implantation. . Generally, a resist pattern formed on a semiconductor substrate through a photolithography process (resist coating, alignment exposure, development and baking) for the ion implantation process is used as it is as a mask for ion implantation.

[Problems to be solved by the invention] In the conventional ion implantation technology described above, a resist, which is an insulator, is used as a mask for ion implantation, so when ions are implanted using charged particles, the surface of the resist is damaged. There is a serious drawback that charges build up and discharge occurs between the resist edge and the semiconductor substrate, destroying the insulator formed on the semiconductor substrate.

In conventional semiconductor devices, for example, the gate insulating film of an MO8 type semiconductor device has a thickness of about 500 to 1000, and no damage was seen due to charge-up during ion implantation as described above. Particularly, since the capacitive insulating film of MO3 type dynamic RAM and the like has a film thickness of about 100 μm, the capacitive insulating film is completely destroyed by the charge-up caused by the above-mentioned ion implantation. Also, in order to solve this problem, we tried changing the mask material for ion implantation from resist, which is an insulator, to a conductive metal, but most of the capacitive insulating films of the 100 people mentioned above, It has been destroyed and has a fatal defect that makes it impossible to manufacture semiconductor devices.

As mentioned above, attempts have been made in the prior art to use conductive materials as masking materials for ion implantation to prevent dielectric breakdown caused by charge-up during ion implantation, but the film thickness of the insulator becomes extremely thin (silicon 300 with oxide film
Å or less) and found that it had no effect. Furthermore, with the miniaturization of patterns (pattern width is around 1μ), when pattern formation is performed using reduced exposure, pattern design is easier with conventional technology, so each chip is In addition, in order to effectively operate the expensive reduction exposure equipment, only the area where a chip can be completely formed is exposed, and as shown in Figure 2(c), the entire semiconductor substrate is exposed. However, the present invention has the novelty of connecting each chip with a pattern and forming a pattern over the entire semiconductor substrate, which is not found in the prior art.

[Means for solving problems]

In the manufacturing method of the present invention, firstly, the mask-resistant material for ion implantation has conductivity, and secondly, the above-mentioned mask-resistant material patterned on the semiconductor substrate is spread over the entire area of the semiconductor substrate. This means that some or all of the respective patterns are connected.

〔Example〕

Embodiments of the present invention will be briefly described below with reference to the drawings.

In the method for manufacturing a semiconductor device of the present invention, first, in the step of forming a mask pattern for ion implantation, a conductive film, for example, an aluminum film of about 1 μm is deposited on a semiconductor substrate, and then an ordinary photolithography technique is used to deposit a conductive film, for example, an aluminum film of about 1 μm. Then, a mask pattern for resisting ion implantation is formed using photoresist on the above-mentioned conductive film. Next, etching is performed using the aforementioned photoresist pattern as a mask to form a mask pattern for resisting ion implantation using the conductive film, and then the resist used as the etching mask for the conductive film is removed. FIG. 1 shows this situation. In FIG. 1(a), an ion implantation-resistant mask pattern made of a conductive film is formed over the entire semiconductor substrate. FIG. 1(b) is an enlarged view of a part of FIG. 1(a), in which an ion implantation-resistant mask pattern is formed on a chip-by-chip basis. 4.5 and the chips are connected by a pattern 6 that connects them.

In this way, if ion implantation is performed with the ion implantation resistant mask pattern formed of a conductive film covering the entire semiconductor substrate connected at some parts, ion implantation can be performed even in a semiconductor device using a very thin insulating film. Breakdown of the insulating film due to charge-up during the implantation process can be prevented.

Incidentally, in the present invention, the connection pattern 6 may be any pattern as long as it is possible to connect patterns on a chip-by-chip basis.
Moreover, it has been confirmed that the effect is equally good even if all the patterns are not connected within a chip unit.

〔Effect of the invention〕

The effects of the present invention will be briefly explained using the drawings.

Figure 3 shows 500 people and 30 people depositing a silicon thermal oxide film on a silicon substrate as a semiconductor substrate and a silicon thermal oxide film as an insulating film, respectively.
These are the results of investigating the dielectric strength of the thermal oxide film after forming it by 0 and 100 people and undergoing an ion implantation process using the manufacturing method according to the present invention. Furthermore, FIG. 4 shows the results of an ion implantation process using the conventional method after forming the same thermal oxide film as in FIG. 3, and investigating the dielectric breakdown voltage of the oxide film in the same manner as described above.

As can be seen from FIG. 3, if the ion implantation process is performed according to the manufacturing method of the present invention, no deterioration in dielectric breakdown voltage will be observed even if the oxide film thickness becomes extremely thin by 100 mm. On the other hand, with the conventional method shown in Figure 4, if the oxide film is 500 thick, there is no significant difference in the dielectric strength of the present invention;
The dielectric strength deteriorates as the number of people increases from 0 to 100, and when the number of people reaches 100, it is almost destroyed and cannot withstand actual use.

As explained above, the present invention uses a conductive film as the material of the ion implantation-resistant mask pattern, and a part of the pattern is connected over the entire semiconductor substrate, so that the charge generated by ion implantation can be avoided. This allows the insulator to escape through the periphery of the semiconductor substrate, and even in semiconductor devices using very thin insulators, it is possible to prevent the insulator from being destroyed by the charge-up phenomenon caused by ion implantation.

Therefore, if the present invention is used, it is possible to realize a semiconductor device using a very thin insulator, and it is also possible to manufacture a semiconductor device with a higher degree of integration.Memory devices, which are required to increase the degree of integration by four times in two years, are now possible. It can also greatly contribute to the practical application of

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 1(a) is a diagram showing an embodiment of the present invention.
FIG. 1(b) shows how the ion implantation resistant mask pattern according to the present invention is formed over the entire semiconductor substrate.
is an enlarged view of a portion of FIG. 1(a). In FIG. 1, 1, 2, 3, and 4.5 are patterns in chip units, and 6 is a connected pattern. Fig. 2 is a diagram showing an example of the conventional method. Fig. 2(a)
1 shows how a chip-by-chip ion implantation resistant mask pattern is formed on a semiconductor substrate. FIG. 2(b) is an enlarged view of a portion of FIG. 2(a), showing that in the conventional method, an ion implantation-resistant mask pattern is formed for each chip. FIG. 3 is a diagram showing the effect of the present invention, and is a diagram showing the dielectric strength of a thermal oxide film formed on a silicon substrate. In FIG. 3, the vertical axis shows the incidence rate, and the horizontal axis shows the dielectric strength voltage. Figures 3 (a), (b), and (c) show that the thermal oxide film is
FIG. 4 is a diagram showing the dielectric breakdown voltage of a thermal oxide film after ion implantation is performed by forming the ion implantation resistant mask pattern of the present invention in the case of 00, 300, and 100 people. FIG. 4 is a diagram showing the dielectric breakdown voltage when ion implantation is performed using the same structure as FIG. 1 and FIG. 3 by forming an ion implantation-resistant mask pattern using the conventional method, in order to compare the effects of the present invention. . In FIG. 4, the vertical and horizontal axes are the same as in FIG. 3. Figure 4(a). (b), (c) C (-500 thermal oxide films, 3
00 people. Insulation of the thermal oxide film when ion implantation was performed using the conventional ion implantation mask pattern as described above with 100 people and the same configuration as in Figures 3 (a), (b), and (c). FIG. 3 is a diagram showing breakdown voltage. Agent Patent Attorney Oto Uchihara (Lung (α) 1st Runo Kuni (a,) ZTE 1MEAKD014/N FxELD M3 times

Claims (1)

[Claims] In the process of introducing impurities into a semiconductor substrate by ion implantation, the substance serving as the ion implantation resistant mask material has conductivity, and the pattern of the ion implantation resistant mask material is connected over the entire area of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized by: