JPH03237720A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the collection and storage of charges in an element from plasma during treatment by a plasma process, and to improve the reliability of the element by forming a wiring during a wiring forming process so as not to be brought to an insulated state with a substrate. CONSTITUTION:The layer 9 of polysilicon as the wiring material of a lower layer and the layer 10 of a tungsten silicide as the wiring material of an upper layer are deposited onto a semiconductor substrate under the state, in which a gate oxide film 2, a gate electrode 3, a field oxide film 4, a P<+> region 5, an N<+> region 5, a P well 7 and a PSG film 8 are formed onto an N-type Si substrate 1, through CVD, and a positive resist pattern 11 is further formed onto the layer 9. The tungsten silicide layer 10 is etched, and the resist layer 11 is peeled through plasma ashing. Since the wiring layer of the lower layer remains on the whole surface of a wafer at that time, there is no wiring under the state insulated from the substrate, thus preventing the collection and storage of charges to an element from plasma during treatment by a plasma process.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device that improves the process of forming element wiring by etching. Provided is a method for manufacturing a semiconductor device that ensures reliability of the device by preventing charge from being collected and accumulated in the device from plasma during plasma processing by forming the device so as not to be insulated from the substrate. With the purpose of is formed as a multilayer film made of a plurality of different materials, the upper layer of the multilayer film is dry etched, and the lowermost layer of the multilayer film is wet etched using the dry etched upper layer as a mask to form wiring. Configure to form.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which the process of forming element wiring by etching is improved.

[Conventional technology]

As the density of semiconductor devices increases, the elements themselves and the wiring of the elements become finer, so today, most of the etching processes for forming wiring are performed by dry etching.
Plasma etching is the most widely used dry etching method. Plasma processes are used in many processes during the process of forming device wiring, such as etching the wiring itself, resist ashing, and interlayer insulating film deposition.

When performing processing using plasma as described above, it is necessary to minimize damage to already formed elements due to the plasma. In particular, when forming an integrated circuit with multilayer wiring, MOS)
If a wiring layer is formed that is connected only to the gates of the transistor, damage to the device due to plasma becomes a serious problem. In other words, during etching or resist ashing of a wiring layer, if wiring, which is designed to be isolated from the board and is insulated, is exposed to plasma, this wiring acts as an "antenna" and absorbs charges from the plasma. is collected and stored at the gate of a MOS) transistor. There is a problem in that excessively accumulated charges damage the gate oxide film or the gate oxide film/substrate interface, deteriorating the reliability of the device.

[Problem to be solved by the invention]

The present invention improves device reliability by preventing charge from being collected and accumulated in the device from plasma during plasma processing by forming the wiring so as not to be insulated from the substrate during the wiring formation process. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that ensures the following.

[Means to solve the problem]

According to the present invention, the above object is achieved by depositing a conductive film over the entire surface of an element formed on a semiconductor substrate via an interlayer insulating film, and patterning the conductive film by etching to form wiring. , the conductive film is formed as a multilayer film made of a plurality of different materials, the upper layer of the multilayer film is dry etched, and then the lowermost layer of the multilayer film is wet etched using the dry etched upper layer as a mask. This is achieved by a method for manufacturing a semiconductor device characterized in that wiring is formed by performing the following steps.

[For production]

According to the method of the present invention, when the resist is removed by plasma ashing, the underlying wiring layer remains on the entire surface of the wafer, so there is no wiring that is insulated from the substrate, and the etching of the wiring is completed. When the wiring becomes insulated from the board, it is processed by wet etching.
The device is not exposed to plasma. Therefore, charges from the plasma are not collected and accumulated in the device, particularly in the gate oxide film of a MOS transistor, etc., thereby preventing damage to the device due to the plasma.

In the following, the invention will be explained in more detail by means of examples with reference to the accompanying drawings.

〔Example〕

An example of wiring according to the present invention will be described with reference to FIGS. 1(a) to 1(C).

In the step shown in FIG. 1(a), a gate oxide film 2, a gate electrode 3, a field oxide film 4 are formed on an n-type Si substrate 1.
, p" region 5, n+ region 6, p well 7, and PSG film 8 are formed on the semiconductor substrate, and a polysilicon layer 9 (thickness: 0.2 .mu.m), which will be the underlying wiring material, is placed on top of the semiconductor substrate. Layer 1 of tungsten silicide, which becomes the upper layer wiring material.
0 (thickness: 1.0 μm) is deposited by CVD, and a positive resist pattern 11 is further formed thereon.

Next, in the step shown in FIG. 2B, the tungsten silicide layer 10 is etched using SFs gas mixed with 25% O2, and then the resist layer 11 is removed by plasma ashing.

Next, in the step shown in FIG. 2C, the polysilicon layer 9 is wet-etched with a mixed solution of HF and HNOa to complete the wiring.

FIG. 2 shows the results of measuring the withstand voltage of a MOS transistor whose wiring was formed in the process shown in FIG. 1, when the area ratio of the wiring to the gate oxide film was 40:1.

For comparison, the same figure also shows the results when there is no wiring part that is insulated from the substrate during wiring formation.

From FIG. 2, it can be seen that the breakdown voltage of the device formed according to the present invention is exactly the same as that without the insulated wiring portion, and was not damaged during plasma ashing of the resist.

Figure 3 shows the case where the resist is removed by plasma ashing while the wiring is insulated from the substrate in the wiring formation process as in the past, and the wiring area ratio to the gate oxide film is 40:■ or 200:2. : This is the withstand pressure measurement result when set to 1.

Similar to FIG. 2, this figure also shows the results when there is no wiring part that is insulated from the substrate during wiring formation for comparison. It can be seen that the breakdown voltage of a device with a large area ratio of the wiring metal to the gate oxide film is greatly reduced.

FIG. 4 shows M with wiring formed by the present invention or the conventional method.
The results of measuring the long-term reliability of the O3I-transistor are shown. The figure shows that when the element life is determined by characteristic fluctuations due to hot carrier effects, the wiring area ratio is 4.
The graph shows the relationship between the operating time until the transconductance deteriorates by 10% after hot carrier injection and the cumulative number of deteriorated elements for a 00:1 element. From the figure, it can be seen that when compared with the same wiring area ratio, the element life according to the present invention is significantly improved than the conventional element life.

〔Effect of the invention〕

As explained above, according to the present invention, by forming the wiring so that it is not insulated from the substrate during the wiring formation process, electric charges can be collected and accumulated in the element from the plasma during the plasma process. It is possible to manufacture a semiconductor device while preventing this and ensuring reliability of the element.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are cross-sectional views showing an example of the process of manufacturing a MOS (MOS) transistor by forming wiring according to the present invention. FIG. M.O.S.
) Figure 3 is a graph showing the breakdown voltage measurement results for MOS transistors whose wiring was formed using the conventional method, and Figure 4 is a graph showing the breakdown voltage measurement results for MOS transistors manufactured using the procedure shown in Figure 1 according to the present invention. M.O.S.
) is a graph showing the measurement results of element life for transistors. 1: Si substrate, 2: Gate electrode, 3: Gate oxide film, 4: Field oxide film, 5: P” region, 6:
n+ region 7: p well, 8: PSG film, 9: polysilicon layer, 10: tungsten silicide layer, 11: positive resist layer. (Q) (b) (C) Figure 1 Figure 2 Figure

Claims (1)

[Claims] 1. A conductive film is deposited on the entire surface of an element formed on a semiconductor substrate via an interlayer insulating film, and when patterning the conductive film by etching to form wiring, the conductive film is coated with a plurality of different materials. After dry etching the upper layer of the multilayer film, and then wet etching the lowermost layer of the multilayer film using the dry etched upper layer as a mask, wiring is formed. A method for manufacturing a featured semiconductor device.