JPH01193935A - Program control system by sub-command execution system - Google Patents

Program control system by sub-command execution system

Info

Publication number
JPH01193935A
JPH01193935A JP63018714A JP1871488A JPH01193935A JP H01193935 A JPH01193935 A JP H01193935A JP 63018714 A JP63018714 A JP 63018714A JP 1871488 A JP1871488 A JP 1871488A JP H01193935 A JPH01193935 A JP H01193935A
Authority
JP
Japan
Prior art keywords
command
sub
function
order processor
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63018714A
Other languages
Japanese (ja)
Inventor
Hiroshi Hibara
啓 桧原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Solution Innovators Ltd
Original Assignee
NEC Solution Innovators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Solution Innovators Ltd filed Critical NEC Solution Innovators Ltd
Priority to JP63018714A priority Critical patent/JPH01193935A/en
Publication of JPH01193935A publication Critical patent/JPH01193935A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the burden of a high-order processor, to improve function with less memory capacity and to facilitate the addition of the function by permitting a low-order processor to collate a prescribed table while it sequentially executes processing programs. CONSTITUTION:A function command (command B) 101 is given from the high- order processor 1. The low-order processor 2 collates to the sub-command B on the table 3 corresponding to the command B101. The order of executing the processing programs 'b', 'a', 'f' and 'd' and the parameters of respective programs are mentioned in the sub-command B. The low-order processor 2 sequentially loads and executes the processing programs 'b', 'a', 'f' and 'd' in correspondence with the sub-command B. Thus, the load of the high-order processor can be reduced and processing speed is improved. Furthermore, the complicated function can be realized with less memory capacity and the function can be easily added.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプログラム制御方式に関し、特にマイクロプロ
セッサ上での文字、イメージ処理プログラムの制御を行
なうプログラム制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program control system, and particularly to a program control system for controlling character and image processing programs on a microprocessor.

〔従来の技術〕[Conventional technology]

従来のこの種のマイクロプロセッサにおけるプログラム
制御においては、1機能の実現に複数個のプログラム(
オブジェクト・プログラム)を要する場合以下の方式が
あった。
In conventional program control for this type of microprocessor, multiple programs (
(object program) was required, the following methods were available.

(1)複数個のプログラムを結合(リンク)して1個の
実行形式のプログラム(ロード・モジ−一ル)を作成し
、そのロード・モジー−ルを実行する方式。
(1) A method in which multiple programs are combined (linked) to create one executable program (load module), and the load module is executed.

(2)上位プロセッサが複数個のプログラムを順次メモ
リ上にロードして実行する方式。
(2) A method in which a host processor sequentially loads multiple programs onto memory and executes them.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の方式は、前者の場合は機能追加や修正の
たびにリンクしなおさなければならず、人 また複雑な機能を実現しようとした場合は多2なメモリ
容量を必要とする問題点を有し、また後者の場合は上位
プログラムが複雑になり、上位プロセッサの負荷が大き
くなり高い処理性能が得られないという問題点があった
The conventional method described above has the problem that in the former case, the link must be re-linked every time a function is added or modified, and that it requires a large amount of memory capacity when trying to implement complex functions. In the latter case, the host program becomes complicated and the load on the host processor increases, making it impossible to obtain high processing performance.

本発明の目的は、下位プロセッサが上位プロセッサより
与えられた機能コマンドに対応する複数個のオブジェク
トプログラムの実行順序とそのパラメータをサブコマン
ドとして記述したテーブルを参照しながら各プログラム
を順次ロード実行することにより上位プロセッサの負荷
を減らし処理速度を向上させ、また少ないメモリ容量で
の複雑な機能の実現や機能付加の容易さをも提供するこ
とにある。
An object of the present invention is for a lower processor to sequentially load and execute a plurality of object programs corresponding to a function command given by an upper processor while referring to a table that describes the execution order of the object programs and their parameters as subcommands. The purpose of this is to reduce the load on the upper processor and improve processing speed, and also to realize complex functions with a small memory capacity and make it easy to add functions.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のプログラム制御方式は、上位プロセッサから与
えられたコマンドに対応する複数個の処理プログラムの
実行順序およびそのパラメータをサブコマンドとして記
述したテーブルと、前記テーブルに記述されたサブコマ
ンドを参照しながら処理プログラムを順次実行すること
により上位プロセッサから与えられたコマンドを実現す
る手段を有している。
The program control method of the present invention includes a table that describes the execution order of a plurality of processing programs corresponding to a command given from a host processor and its parameters as subcommands, and a table that describes the subcommands described in the table. It has means for realizing commands given from a higher-level processor by sequentially executing processing programs.

〔実施例〕 以下、本発明の実施例について図面を参照して説明する
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の実施例の全体構成図である。FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

(1)上位プロセッサ1から機能コマンド(コマンドB
)101が与えられる。コマンドB101次実行しなけ
ればならない。
(1) Function command (command B) from upper processor 1
) 101 is given. Command B10 must be executed first.

(2)下位プロセッサ2はコマンドB101に対応した
テーブル3上のサブコマンドBを参照する。
(2) The lower processor 2 refers to the subcommand B on the table 3 corresponding to the command B101.

サブコマンドBには処理プログラム「イ」、「ア」。Subcommand B has processing programs "I" and "A".

「力」、「工」の実行の順序とそれぞれのプログラムの
パラメータが記述しである。
The order of execution of ``force'' and ``work'' and the parameters of each program are described.

(3)  下位プロセッサ2にサブコマンド1m従い、
処理プログラム「イ」、「ア」、「力」、「工」を順次
ロードし実行する。
(3) Follow subcommand 1m to lower processor 2,
Load and execute the processing programs "I", "A", "Riki", and "Work" in sequence.

第2図は、サブコマンドBの構成例を示す概念図である
。サブコマンドには複数個の処理プログラムの実行順序
に従って、それぞれの処理プログラムについてのロード
・コマンド201と入力パラメータ202と実行コマン
ド203が記述されている。
FIG. 2 is a conceptual diagram showing an example of the configuration of subcommand B. A load command 201, an input parameter 202, and an execution command 203 for each processing program are described in the subcommand in accordance with the execution order of the plurality of processing programs.

第3図は第1図に示す処理Bのコマンド101の例とし
て2倍拡大縦書き白黒反転文字展開(以下、処理Aと略
す)を処理例を示した模式図である。上位プロセッサ1
から下位プロセッサ2へ処理Aの機能コマンド(301
)が発行されると下位プロセッサ2は以下の動作を行う
FIG. 3 is a schematic diagram showing a processing example of double enlarged vertical black and white inverted character development (hereinafter abbreviated as process A) as an example of the command 101 of process B shown in FIG. Upper processor 1
from the lower processor 2 to the processing A function command (301
) is issued, the lower processor 2 performs the following operations.

(1)下位プロセッサ2はテーブル3内の処理Aのサブ
コマンドを参照(302)して文字展開プログラム(1
番目の処理)をロード(302−1)および実行する(
303−1)。
(1) The lower processor 2 refers to the subcommand of process A in table 3 (302), and the character expansion program (1
load (302-1) and execute (302-1)
303-1).

(2)文字展開が終了すると下位プロセッサ2は再び処
理Aのサブコマンドを参照して文字拡大プログラム(2
番目の処理)をロード(302−2)および実行する(
303−2)。
(2) When the character expansion is completed, the lower processor 2 again refers to the subcommand of process A and the character expansion program (2
Load (302-2) and execute (302-2) the
303-2).

(3)同様にして文字拡大の次に90度回転プログラム
(3番目の処理)をロード(302−3’)および実行
する(303−3)。
(3) Similarly, after character enlargement, a 90 degree rotation program (third process) is loaded (302-3') and executed (303-3).

(4)同様にして白黒反転プログラム(4番目の処;〉
5− 理)をロード(302−4)および実行する(303−
4)。
(4) Similarly, black and white inversion program (4th place;
5- Load (302-4) and execute (303-
4).

以上の処理Aに必要な処理プログラムの実行が全て終了
すると下位プロセッサ2は上位プロセッサ1に対して終
了信号(304)を返す。
When the execution of all the processing programs necessary for the above processing A is completed, the lower processor 2 returns a completion signal (304) to the upper processor 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は1手巻寺判いろいろな変換
を順次施して印刷する事を目的とする文字処理等の制御
において、各機能に対応した複数個の処理プログラムの
実行順序を記述したテーブルを参照しながら処理プログ
ラムを順次実行する処理方式により、上位プロセッサの
負荷の低減少ないメモリ容量での高機能の実現、機能追
加を容易にするという効果がある。
As explained above, the present invention describes the execution order of a plurality of processing programs corresponding to each function in controlling character processing etc. for the purpose of sequentially applying various conversions and printing. A processing method that sequentially executes processing programs while referring to a table has the effect of reducing the load on the host processor, realizing high functionality with a small memory capacity, and making it easy to add functionality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す全体構成図、第2図は
第1図のテーブル3に示されるサブコマンドの一構成例
を示す概念図、第3図はコマンドの例として2倍拡大縦
書き白黒反転文字展開を例とした処理の模式図である。 ・−N− 1・・・・・・上位プロセッサ、2・・・・・・下位プ
ロセッサ、3・・・・・・テーブル、4・・・・・・オ
ブジェクトプログラム。 代理人 弁理士  内 原   晋 X−
Figure 1 is an overall configuration diagram showing an embodiment of the present invention, Figure 2 is a conceptual diagram showing an example of the configuration of subcommands shown in Table 3 in Figure 1, and Figure 3 is an example of a command twice as large. FIG. 3 is a schematic diagram of a process taking enlarged vertical writing black and white inverted character development as an example. -N- 1... Upper processor, 2... Lower processor, 3... Table, 4... Object program. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims]  文字、イメージ処理を行うマイクロプロセッサにおけ
るプログラム制御方式において、上位プロセッサから与
えられたコマンドに対応する複数個の処理プログラムの
実行順序とパラメータをサブコマンドとして記述したテ
ーブルと、前記テーブルに記述されたサブコマンドを参
照しながら前記複数個の処理プログラムを順次実行し、
上位プロセッサから与えられたコマンドを実現する手段
とを有することを特徴とするサブコマンド実行形式によ
るプログラム制御方式。
In a program control system for a microprocessor that processes characters and images, there is a table that describes the execution order and parameters of multiple processing programs corresponding to a command given from a host processor as subcommands, and a subcommand that describes the subcommands. sequentially executing the plurality of processing programs while referring to commands;
1. A program control method using a subcommand execution format, characterized by having means for realizing a command given from a host processor.
JP63018714A 1988-01-28 1988-01-28 Program control system by sub-command execution system Pending JPH01193935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63018714A JPH01193935A (en) 1988-01-28 1988-01-28 Program control system by sub-command execution system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63018714A JPH01193935A (en) 1988-01-28 1988-01-28 Program control system by sub-command execution system

Publications (1)

Publication Number Publication Date
JPH01193935A true JPH01193935A (en) 1989-08-03

Family

ID=11979327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63018714A Pending JPH01193935A (en) 1988-01-28 1988-01-28 Program control system by sub-command execution system

Country Status (1)

Country Link
JP (1) JPH01193935A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105021A (en) * 1993-06-15 1995-04-21 Xerox Corp Processing emulation method of multiprocessing pipeline data
JPH07105020A (en) * 1993-06-15 1995-04-21 Xerox Corp Pipelined image processing system
JP2000089959A (en) * 1998-07-31 2000-03-31 Sony United Kingdom Ltd Data processor and data processing method
JP2007304802A (en) * 2006-05-10 2007-11-22 Fuji Xerox Co Ltd Data processing device and its program
JP2010128908A (en) * 2008-11-28 2010-06-10 Canon It Solutions Inc Information processing apparatus, control method for the same, and program
JP2017162215A (en) * 2016-03-09 2017-09-14 ソフトバンク株式会社 Command processor and program

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105021A (en) * 1993-06-15 1995-04-21 Xerox Corp Processing emulation method of multiprocessing pipeline data
JPH07105020A (en) * 1993-06-15 1995-04-21 Xerox Corp Pipelined image processing system
JP2000089959A (en) * 1998-07-31 2000-03-31 Sony United Kingdom Ltd Data processor and data processing method
JP2007304802A (en) * 2006-05-10 2007-11-22 Fuji Xerox Co Ltd Data processing device and its program
JP2010128908A (en) * 2008-11-28 2010-06-10 Canon It Solutions Inc Information processing apparatus, control method for the same, and program
JP2017162215A (en) * 2016-03-09 2017-09-14 ソフトバンク株式会社 Command processor and program

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