JPS59172060A - Controlling system of multiprocessing system - Google Patents

Abstract

PURPOSE:To shorten the time for processing by indicating directly a program to be processed stored in a controlling memory by a host microprocessor to a subordinate microprocessor. CONSTITUTION:A host microprocessor 6 controls a multiplexer 11 and connects a program counter 12 to the host microprocessor 6. The host microprocessor 6 sets the address of a microprogram corresponding to the content to be processed by a subordinate microprocessor 10 stored in a controlling memory 14. Then, the multiplexer 11 is switched to the microprocessor 10 side and the microprocessor 10 is started. The microprocessor 10 reads and processes the microprogram of the controlling memory 14 by the address indicated by the program counter 12 through a multiplexer 13.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a multiprocessing system using a plurality of microprocessors and in which the microprocessors share and process a plurality of tasks. The present invention relates to a control method for a multi-processing system that reduces the processing time of a lower-level microprocessor and improves the efficiency of the entire system when processing is divided into lower-level microprocessors.

(b) Prior art and problems In a multiprocessing system composed of multiple microprocessors, when each microprocessor performs control to process multiple tasks, the control order is divided into upper and lower levels. An interface register is provided between an upper microprocessor and a lower microprocessor, instructions and information accompanying the instructions are transmitted from the upper microprocessor to the lower microprocessor via the register, and processed results are transferred via the register. It was reported to the upper microprocessor. Therefore, the upper microprocessor needs to create instructions and information, and the lower microprocessor analyzes the instructions and information and understands the content of the work it needs to perform.

processing was being performed. However, there are disadvantages in that it may take a lot of time to analyze the instructions and information, and a program for analysis is also required.

(()Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by eliminating the need to analyze the instructions and information of the lower microprocessor, thereby saving time and controlling a multiprocessing system with high speed and efficiency. The purpose is to provide a method.

(d) Structure of the Invention The structure of the present invention is such that in each city processing system composed of a plurality of microprocessors, a program to be processed stored in a control memory is transferred to a microprocessor located at a lower level. The program to be processed is directly instructed by the processor, and the program to be processed is loaded into the control memory by the microprocessor located at the upper level.

(e) Embodiments of the Invention The present invention provides the time required for the upper microprocessor to create instructions and information to be given to the lower microprocessor, and the time required for the lower microprocessor to directly instruct the program counter of the lower microprocessor with the contents to be processed by the lower microprocessor. Since the time required for processing is the same and there is no difference in hardware, it is possible to build a high-speed and efficient multiprocessing system by omitting the time required to analyze the instructions and information of the lower microprocessor. It is.

FIG. 1 shows an example of a multiprocessing system to which the present invention is applied. This example is a high-speed printing device. The main microprocessor 1 is a high-level microprocessor, including a data processing section 2 that processes print data and a BG that performs image processing, etc.
(Business Graph Inc.) Each of the processing units 3 uses a microprocessor, and is controlled by five main microprocessors 1.

Processing is performed according to each function. Particularly those requiring high-speed processing are processed by the logic circuit section 4.

The printing unit 5 is controlled to perform high-speed printing. Therefore, the microprocessors of the data processing section 2 and the BG processing section 3 are microprocessors located at a lower level. Further, the main microprocessor 1 is connected to the host Wt computer through a terminal A and receives control therefrom.

FIG. 2 is a block diagram illustrating an embodiment of the present invention. The upper microprocessor 6 corresponds to the main microprocessor 1 in FIG. 1, and the microprocessors 10 and 15 are lower microprocessors. Therefore, it corresponds to the microprocessor used in the data processing section 2 and the BG processing section 3 in FIG. The host microprocessor 6 controls the multiplexer 11 and the program counter 12.
is connected to the host microprocessor 6. Here, the upper microprocessor 6 writes the address of the microprogram stored in the control memory 14 that corresponds to the content to be processed by the lower microprocessor 10. Next, switch the multiplexer 11 to the microprocessor 10 side,
Start up the microprocessor 10. The microprocessor 10 sequentially outputs microprograms from the control memory 14 via the multiplexer 13 at the address indicated by the program counter 12 and performs processing. Therefore, the microprocessor 10 at the lower level does not need to analyze the plurality of processes given from the upper level, and the processing speed is improved.

Furthermore, when processing many types of programs, the host microprocessor 6 uses the auxiliary storage device 7.

Drives a direct memory access (DMA) circuit 8,
The multiplexer I3 is switched to the DM8 side, and the program is dynamically loaded into the control memory 14 to execute processing.

Microprocessor15. Program counter 17, control memory 19. The operation of the circuit consisting of multiplexer 16 and I8 is the same as described above.

Detailed explanation will be omitted.

(f) Detailed Description of the Invention 9 As described in the present invention, the processing time is reduced because the lower microprocessor processes the microprogram in the control memory indicated by the program counter without analyzing the instructions and information indicated by the upper microprocessor. Not only is it shortened and efficiency is improved, but it also has great effects because it dynamically loads and processes many types of programs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a multiprocessing system to which the present invention is applied, and FIG. 2 is a block diagram illustrating an embodiment of the present invention. ■- is the main microprocessor, 2 is the data processing section. 3 is a BG processing unit, and 6 is a host microprocessor. 7 is an auxiliary storage device, 8 and 9 are direct memory access (DMA) circuits, 10.15 is a microprocessor, 1
2.17 is a program counter, and 14.19 is a control memory.

Claims (1)

[Claims] 1) In a multiprocessing system composed of a plurality of microprocessors, a program to be processed stored in a control memory is directly transmitted to a microprocessor located at a lower level by a microprocessor located at a higher level. A control method for a multi-processing system, characterized in that instructions are given. 2) The control method for a multiprocessing system according to claim 1, wherein the program to be processed is loaded into the control memory by the microprocessor located at the upper level.