JPH01192212A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To attain ease of manufacture without degradating the reliability and to reduce the chip size by constituting the circuit such that a back gate bias is applied to a MOS transistor(TR) being a component of a CMOS output circuit so as to set the logic state of the circuit at application of power easily. CONSTITUTION:Since a threshold value of an N-channel MOS TR Q2 in a power-on reset circuit is higher than a threshold value of other N-channel MOS TR Q4, the N-channel MOS TR Q4 is easily turned on by comparing both the MOS TRs Q2, Q4. Thus, in case of application of a power supply VCC, the N-channel MOS TR Q4 is turned on and the potential at an output terminal Q2 of the 2nd circuit 2 is set to a low leel. The potential at an output terminal O1 of the 1st circuit 1 receiving the low level at its input terminal I1 is set to a low or a high level in response to the input. Since the power-on reset circuit forms a latch circuit, the potential of the output terminal O2 is kept to the low level at application of power VCC in the logic state in the 2nd circuit 2 receiving the potential of the output terminal O1 at its input terminal I2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit that is set to a predetermined logic state upon power-on.

(Prior Art) Fig. 13 is a circuit diagram showing a conventional example of this type of power-on reset circuit. In the figure, 1 is a first inverter consisting of a complementary MOS output circuit (hereinafter referred to as 0M08 circuit) , 2 is a second inverter consisting of the same <0M08 circuit, and P-channel MO forming the first inverter 1.
The common drain of the S transistor RO 1 and the N channel MOS transistor RO 2, that is, the output terminal 0 of this inverter 1.
1 is a P-channel MOS that constitutes the second inverter 2
Transistor Q3 and N-channel MOS transistor Q4
It is connected to the common gate of the inverter 2, that is, the input terminal 2 of the inverter 2. Further, the common drain of the P-channel MOS transistor Q3 and the N-channel MOS transistor Q4, that is, the output terminal 02 of the second inverter 2, is connected to the common gate of the P-channel MOS transistor Q3 and the N-channel MOS transistor Q4, that is, the output terminal 02 of the second inverter 2. It is connected to the input terminal (■) of inverter 1. Zarani P channel MOS
The sources of transistors Q1 and Q3 are power supply V. 0 in common, and the sources of N-channel MOS transistors Q2 and Q4 are commonly connected to ground GND.

And power supply ■. A capacitor C1 is connected between the output terminal 0 and the output terminal 01, and a capacitor C2 is connected between the output terminal 02 and the ground GND.

A conventional power-on reset circuit is configured as described above, and the power supply ■. 0, charging of the capacitor C1 and discharging of the capacitor C2 occur instantaneously, and the potential of the output terminal 01 of the first inverter becomes a high level due to the capacitor C1, and the potential of the output terminal 02 of the second inverter 2 increases. becomes low level by capacitor C2. Therefore, the P-channel MOS transistor Q, whose gate receives a low-level input from the output terminal 02, and the N-channel MOS transistor Q4, whose gate receives a high-level input from the output terminal 01, are turned on, and the potential at the output terminal 01 becomes high. to the level,
The potential of the output terminal 02 is set to 0-level.

[Problem to be solved by the invention]

Conventional power-on reset circuits like the one above require a large capacitance capacitor, so this can be replaced with a complementary MOSI!
When applied to integrated circuit devices, the insulating layer must be thin and the area must be large to form a capacitor. As a result, there were problems such as difficulty in manufacturing to ensure circuit reliability and an increase in chip size.

This invention was made to solve these problems, and it is possible to simplify the circuit configuration by eliminating the need for a large-capacity capacitor, and also to reduce reliability when applied to a complementary MOS integrated circuit device. It is an object of the present invention to provide a power-on reset circuit that can be easily manufactured without any problems and can also reduce the chip size.

[Means to solve the problem]

The power-on reset circuit according to the present invention has a complementary MO
A second circuit having the same CMOS output circuit receives the output of a first circuit having an S output circuit (hereinafter referred to as a CMOS output circuit) as an input, while the first circuit receives the output of the second circuit. The first and second circuits are connected so as to receive the signal as an input, and one of the P-channel MOS transistor and the N-channel MOS transistor constituting the CMOS output circuit of at least one of the first and second circuits is connected. A backgate bias is applied.

[Effect]

In the power-on reset circuit of this invention, since the threshold voltage of the back-gate biased transistor increases, that transistor becomes difficult to turn on when the power is turned on, and the other complementary transistor always turns on. The first and second circuits are thereby set to a predetermined logic state.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a power-on reset circuit according to the present invention. In the figure, 1 is a first circuit having a CMOS output circuit 1a, 2 is a second circuit having the same CMOS output circuit 2a, and the output terminal 01 of the first circuit 1 is the input terminal I2 of the second circuit 2. connected to the second
The output terminal O of the circuit 2 is connected to the input terminal 11 of the first circuit 1 to form a latch circuit. Ql and Ql are P-channel MOS transistors and N-channel MOS transistors that constitute the CMOS output circuit 1a of the first circuit 1, and Q and Q4 are P-channel MOS transistors and N-channel MOS transistors that constitute the CMOS output circuit 2a of the second circuit 2. Channel MOS transistor, each P channel MO
The sources of S transistors Q and Q3 are connected to the voltage m v cc, and the sources of each N channel MOS transistor Q2 and Q4
The source of is connected to ground GND. And the first
A back gate bias power supply BG1 is connected between the source of the N-channel MOS transistor Q2 of the circuit 1 and the substrate of that transistor, and this makes it possible to use the source as a reference! ! - is configured so that a negative potential, that is, a back gate bias is applied.

Figure 2 shows the back gate bias and threshold value ΔV□ when back gate bias is applied to the MOS transistor.
FIG. 6 is a characteristic diagram showing the relationship between the threshold value 67 and the threshold value 67, which shows that as the back gate bias increases, the threshold value 67 also increases. As is clear from this, in the power-on reset circuit of FIG.
This means that the threshold value is set higher than the threshold value of transistor Q4.

In the power-on reset circuit configured as described above, since the threshold of the N-channel 1VOS transistor Q2 is higher than the threshold of another N-channel MOS transistor Q4, both of these MOS transistors Q2, Q4 When compared, N-channel MOS transistor Q4 is easier to turn on. Therefore, when the power supply ■cc is turned on, the N-channel MOS transistor Q is turned on and the potential of the output terminal 02 of the second circuit 2 is set to a low level. In the first circuit 1 which receives this low level potential at its input terminal 11, the potential at its output terminal 01 is set to a low level or a high level in accordance with the input. Since this power-on reset circuit constitutes a latch circuit as described above, the second circuit 2 receives the potential of the output terminal O at the input terminal I2, and the second circuit 2 receives the potential of the output terminal O at the input terminal I2. It is maintained in a logic state of low level.

FIG. 3 shows an embodiment in which the first and second circuits 1.2 are respectively CMOS output circuits constituting inverters, and the N-channel MOS transistor Q2 of the first circuit 1 is connected to the power supply BG1. The configuration for applying a back gate bias is the same as that shown in FIG. In this circuit, of both MOS transistors Q2 and Q4, transistor Q4 is easier to turn on, so when the power is turned on, transistor Q4 is turned on and the output terminal becomes 0.
The potential of No. 2 becomes low level. This low level potential is applied to the input terminal 11, turns on the transistor Q, and the potential at the output terminal 01 becomes high level. Then, this high-level potential is applied to the input terminal (2) to maintain the on state of the transistor Q4, and the transistor Q4 shifts to the latch state.

FIG. 4 shows another embodiment in which the back gate bias power supply BG1 in the case of FIG. 3 is connected to the P-channel MOS transistor Q2 in the first circuit 1 instead of the N-channel MOS transistor Q2. . That is, the back gate bias power supply BG1 is connected between the source of the P-channel MOS transistor Q1 and the substrate of the transistor so that a positive potential is applied to the substrate with the source as a reference. In this power-on reset circuit,
P-channel MO with back gate bias
The threshold of S transistor Q1 is different from that of other P channel MOS.
Since it is higher than the threshold of transistor Q3,
When the power supply vcc is turned on, the P-channel MOS transistor Q3 is turned on, and the potential at the output terminal 02 becomes high level.
Upon receiving this at the input terminal 1, the N-channel MOS transistor Q is turned on, and the potential at the output terminal 01 is set to a low level.

FIG. 5 shows a P-channel MOS transistor Q3 in addition to the N-channel MOS transistor Q2 in the configuration of FIG.
This shows another embodiment in which another back gate bias power source BG2 is also connected to the side. In other words, the new back gate bias power supply BG2 is a P channel MOS)-
The source of transistor Q3 is connected to the substrate of the transistor so that a positive potential is applied to the substrate with reference to the source. In this power-on reset circuit,
P channel MO from P channel MOS transistor Q1
The threshold voltage of the S transistor Q3 is higher than that of the N channel MOS transistor Q4, and the threshold voltage of the N channel MOS transistor Q2 is higher than that of the N channel MOS transistor Q4. When C is turned on, P channel MOS transistors Q1 and N
Channel MOS transistor Q4 is turned on, and the potential at output terminal o1 is set to high level, and the potential at output terminal 02 is set to low level.

FIG. 6 shows the back gate bias mi! in the configuration shown in FIG. This shows another embodiment in which a back gate bias is applied to the N-channel MOS transistor Q2 by using a diode P1 in place of 1lBG1. That is, diode P1 is an N-channel MOS
It is connected between the source of the transistor Q2 and the ground GND, and the substrate of the transistor is connected to the ground GND so that the forward voltage of the diode P applied between the source and the ground GND becomes a back gate bias. It is composed of The operation in this case is the same as that in FIG.

Figure 7 shows a P-channel MOS transistor in which the diode P1 is replaced with an N-channel MOS transistor Q2 in the case of Figure 6.
This shows another embodiment in which the transistor is connected to the transistor 1 side. That is, the diode P1 is connected to the source of the P-channel MOS transistor Q1 and the power supply V. 0, and the substrate of that transistor is connected to the power supply V. The forward voltage of the diode P1 is applied to the P-channel MOS transistor Q1 as a back gate bias. The operation in this case is the same as in the case of FIG.

FIG. 8 shows a P-channel MOS transistor Q in addition to the N-channel MOS transistor Q2 in the configuration of FIG.
This shows another embodiment in which another diode P2 is also connected to the side. That is, the new diode P2 connects the source of the P-channel MOS transistor Q and the power supply V. 0, and the substrate of the transistor is connected between the power supply vc
P channel MOS transistor Q with the forward voltage of diode P2 as back gate bias.
It is configured to give 3. The operation in this case is similar to that in FIG.

FIG. 9 shows the case of FIG. 6 in which a diode P1 is connected between the common source of two N-channel MOS transistors Q2 and Q4 and the ground GND, and the substrate of the N-channel MOS transistor Q2 is connected to the ground GND. This shows another embodiment in which the forward voltage of diode P1 is applied as the back gate bias of N-channel MOS transistor Q2. The operation in this case is the same as that in FIG.

FIG. 10 shows a P-channel MOS transistor in which the diode P1 is replaced with an N-channel MOS transistor Q2 in the case of FIG.
This shows another embodiment in which the S transistor is connected to the Q3 side. That is, the diode P1 is connected to the common source of the two P-channel MOS transistors Q and Q3 and the power supply vC.
At the same time, the substrate of the P-channel MOS transistor Q is connected to the power supply vCo, and the forward voltage of the diode P1 is connected between the P-channel MOS transistor Q and the
This figure shows another embodiment configured to provide the back gate bias of the circuit. The operation in this case is the same as in the case of FIG.

FIG. 11 shows a P-channel MOS transistor Q in addition to the N-channel MOS transistor Q2 in the configuration of FIG.
This shows another embodiment in which another diode P2 is also connected to the side. That is, the new diode P2 is 2
It is connected between the common source of the two P-channel MOS transistors Q and Q3 and the power supply voo, and the substrate of the P-channel MOS transistor Q is connected to the power supply ■. 0, so that the black direction voltage of diode P2 is applied as a back gate bias of P channel MOS transistor 63. The operation in this case is the same as in the case of FIG.

Figure 12 shows the power supply ■ in the configuration of Figure 3. Switch S that turns on in response to control signal φ when 0 is turned on.
This shows another embodiment in which the output terminal 01 and the input terminal I2 are connected via W, and the power supply V. When the switch SW is turned on at the same time as 0 is turned on, it functions as a latch circuit as in the case of FIG. 3 and maintains the set logic state.

〔Effect of the invention〕

As described above, according to the present invention, a back gate bias is applied to the MOS transistors constituting the CMOS output circuit, so that the logic state of the circuit at power-on can be easily set. The circuit configuration is simplified compared to the required conventional circuit, and even when applied to complementary MOS m integrated circuit devices, it can be easily manufactured without reducing reliability, and the chip size can be reduced. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of this invention, and FIG.
A characteristic diagram showing the relationship between the back gate bias and the threshold value in an OS transistor, FIGS. 3 to 12 are circuit diagrams showing other embodiments of the present invention, and FIG. 13 shows a conventional power-on reset circuit. It is a circuit diagram. In the figure, 1 is the first circuit, 2 is the second circuit, 1a,
2a is 0M08 circuit, 1.12 is input terminal, 01.0□ is output terminal, Q, Q3 is P channel MOS transistor,
Q, Q4 are N-channel MOS transistors, BG, BG
2 is a back gate bias power supply. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A first circuit having a complementary MOS output circuit, which also has a complementary MOS output circuit, receives the output of the first circuit as an input, and receives its own output as an input of the first circuit. A power-on reset circuit, wherein the first and second circuits are set to a predetermined logic state upon power-on, and at least one of the first and second circuits. The complementary form M of
A power-on reset circuit characterized in that a back gate bias is applied to either a P-channel MOS transistor or an N-channel MOS transistor constituting an OS output circuit.