JPH0119169B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a stored program type sequence controller, and particularly to a sequence controller in which an arithmetic processing section is made exclusively for single-bit operations necessary for sequence control. In a stored program type sequence controller, the arithmetic processing section is made up of a microcomputer, and the arithmetic circuit that can execute only the single-bit arithmetic required for sequence control is made using flip-flops, gate circuits, etc. Although there is an arithmetic processing unit, it is preferable to use a dedicated logic arithmetic circuit that can only perform single-bit operations in terms of a simpler circuit, lower price, and faster operation speed. However, if this is done, there is a problem that multi-bit operations cannot be performed at all. For this reason, in the past, there have been devices in which a simple multi-bit arithmetic circuit was provided in addition to a logical arithmetic circuit dedicated to single-bit arithmetic operations to provide multi-bit arithmetic functions; In order to perform this, a word operation instruction is required in addition to the sequence instruction, which not only makes it impossible to use a program writing device that can only program sequence instructions, but also requires multi-bit calculations on the setting values of externally installed digital switches, etc. There was a problem in that a special interface was required when reading into the circuit. The present invention has been made in view of these conventional problems, and allows multi-bit arithmetic instructions to be executed without using special arithmetic instructions, and multi-bit arithmetic instructions to be executed from outside without providing a special interface. An object of the present invention is to provide a sequence controller that can supply information of the following information to an arithmetic circuit. Embodiments of the present invention will be described below based on the drawings. In FIG. 1, 10 is a memory that stores sequence programs, 11 is a program counter that sequentially reads out the sequence programs stored in this memory 10, and the sequence program data read out from the memory 10 is temporarily stored in a latch circuit 12. Of the sequence program data stored in this latch circuit 12, the lower n bits of data for selecting input/output elements are outputted onto the address bus AB as input/output address data IOAD, and the upper m bits of data are used as commands. The data is supplied to the single-bit arithmetic circuit 13 as data. Further, 15 indicates an input circuit having a plurality of input terminals to which input elements such as limit switches are connected, and 16 indicates an output circuit having a plurality of output terminals to which output elements such as relays are connected. This input circuit 15 and output circuit 16 are connected to a connector 17a.
~17c to the address bus AB, 1-bit input data line IDL, 1-bit output data line ODL, and strobe signal line.
SSL, the input circuit 15 selects an input element according to the input/output address data IOAD output on the address bus AB, outputs its on/off state to the input data line IDL, and the output circuit 16 selects an output element using the input/output address data IOAD on the address bus AB, and activates the selected output element according to the state of the output data line ODL when a strobe signal is output to the strobe signal line SSL. , become powerless. On the other hand, the single-bit arithmetic circuit 13 performs single-bit arithmetic operations necessary for sequence control, and if the instruction data given from the latch circuit 12 is a test instruction, it turns on and off the input elements via the input data line IDL. It reads the signal and performs a logical operation on the previous test result, and if the given instruction data is an output instruction, outputs the output signal and strobe signal according to the operation result to the output data line ODL and strobe signal line SSL. energize or deenergize the selected output element by outputting the respective output elements. Next, the configuration of the multi-bit arithmetic circuit 20, which is a feature of the present invention, will be explained. This multi-bit arithmetic circuit 20, like the input/output circuits 15 and 16,
The input/output circuit 15,
Connector 1 provided for adding 16
It is connected to address bus AB, input data line IDL, output data line ODL, and strobe signal line SSL via line 7d. As shown in FIG.
7, one shot circuit 28, comparator 30, parity signal generator 31, gate circuits G1a, G1b,
Consists of G1c, G2a, and G2b, among which,
Comparator 30, parity signal generator 31, gate G
A calculation unit 3 that performs multi-bit calculations in 1a to G2b.
2 are configured. Of the registers 21 to 23, register 21,
Reference numeral 22 is a data register for setting data to be subjected to a multi-bit operation, and the latch 26 is for temporarily storing the operation result. Further, the register 23 is
It stores the type of command to be executed and data instructing the start of execution of the command. The registers 21 to 23 have eight storage elements inside, and when a signal is applied to the enable terminal E, the data terminal D is stored in the storage element specified by the 3-bit address data applied to the address terminal AT. The enable terminals E of these registers 21 to 23 store the strobe signal SS output to the strobe signal line SSL.
The address terminal AT is connected to the lower bit line of the address bus AB, and the data input terminal is connected to the output data line ODL. . The input terminal of the address decoder 25 is connected to the upper bit line of the address bus AB, and the registers 21 to 23 are selected based on the upper bit address data. Therefore, register 21~
Each storage element in registers 21 to 23 has a different input/output address for each bit, and the single-bit arithmetic circuit 13 writes on/off information bit by bit to the storage elements in registers 21 to 23 by executing an output command. Can be done. On the other hand, the data selector 27 outputs the contents of the latch 26 to the input data line IDL when a signal is applied to the enable terminal E and all zero data is applied to the address terminal AT. E is connected to output 3 of the address decoder 25, and is the address terminal
AT is connected to the lower bit of address bus AB. Therefore, the storage elements in latch 26 have unique input/output addresses different from the storage elements in registers 21-23, and when a test instruction for this input/output address is executed, the single bit data in latch 26 is is applied to the single bit arithmetic circuit 13. Note that when the calculation result is multi-bit data, the register 26 is made to have a plurality of storage elements, and the selection of this storage element is performed by the data selector 27.
This can be done by Further, in this embodiment, the calculation section 32 has the function of comparing multi-bit data and generating a corresponding parity signal from the multi-bit data, and the calculation result becomes 1-bit data as described above. . That is, a pair of input terminals of the comparator 30 are connected to the register 2 via gates G1a and G1b, respectively.
1 and 22, and the parity generator 31
The input terminal of is connected to the register 21 via gate G2a.
The outputs of the comparator 30 and the parity generator 31 are connected to the gate G
1c and G2b to the input of the latch circuit 26. And these gates G1a~
Of G2b, gates G1a to G1c are register 2
The gates G2a and G2b are connected to the output corresponding to the bit zero of the register 23, and are opened when a 1 is written to the storage element of the bit zero.
It is connected to the output terminal corresponding to bit 1 of the bit 1, and is opened when 1 is written to the storage element of bit 1. Further, the load terminal of the latch 26 is connected to the register 23 via a one-shot circuit 28.
It is connected to the output terminal corresponding to bit 7 of , and when 1 is written to the storage element of bit 7, the operation result is stored in latch 26. Note that the registers 21 to 23 and latch 2
The input/output addresses of each storage element in 6 are assigned so as not to overlap with the input/output addresses of input/output circuits 15 and 16, and in this embodiment, addresses 0 to 1777 (in octal notation) are assigned as input addresses. Output circuit 1
5, 16, and addresses 2000 to 2030 (8
(indicator) are allocated to storage elements in registers 21-23 and latch 26. Now, eight output terminals are connected to the terminals corresponding to addresses 100 to 107 of input circuit 15.
The setting value of the BCD output digital switch 40,
The outputs of limit switches LS0 to LS7 are compared with the outputs of limit switches LS0 to LS7, which are connected to the terminals corresponding to addresses 200 to 207 of the input circuit 15 and are attached to the pallets on which the workpiece is placed. Value and limit switch LS0
~If the pallet numbers read by LS7 are equal, the relay CR10 connected to address 500 of the output circuit 16 is to be energized.The program shown in Table 1 is written in the memory 10 as a sequence program. put.

【table】

Claims (1)

[Claims] 1 Select input/output elements based on the data in the input/output address part of the sequence program read from the storage device, and perform a single bit operation based on the data in the instruction part of the sequence program and an output command based on the result of this operation. In the sequence controller, each element has a unique input/output address and can be selected by the data in the input/output address field, and the input/output elements are selected bit by bit by the output command. a first data register and a second data register that are composed of a plurality of storage elements into which on/off information is written; and a third data register that stores the type of instruction to be executed and the start of execution of the instruction in accordance with the output instruction. , an operation for performing a predetermined operation on the data stored in the first data register and the second data register according to the type of the instruction written in the third data register and the data for starting execution of the instruction; a latch circuit that temporarily latches the output of this arithmetic circuit, and a gate circuit that outputs this latched output to the single-bit arithmetic circuit as an on/off signal for an input/output element having a specific input/output address. A sequence controller characterized by: