JPH01189143A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01189143A
JPH01189143A JP63014266A JP1426688A JPH01189143A JP H01189143 A JPH01189143 A JP H01189143A JP 63014266 A JP63014266 A JP 63014266A JP 1426688 A JP1426688 A JP 1426688A JP H01189143 A JPH01189143 A JP H01189143A
Authority
JP
Japan
Prior art keywords
voltage
abnormal
impurity layer
pulsating
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63014266A
Other languages
Japanese (ja)
Inventor
Masahiro Takeuchi
正浩 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63014266A priority Critical patent/JPH01189143A/en
Publication of JPH01189143A publication Critical patent/JPH01189143A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To protect a device against a pulsating abnormal voltage, by providing a metal film which is to become an external connecting terminal in connection with a region comprising a reverse conductivity type impurity layer with respect to a first conductivity type semiconductor substrate. CONSTITUTION:A signal from the outside is inputted into a gate electrode 105 through a bonding wiring 109, an external connecting terminal 108, an N-type impurity layer 102 and thereafter an aluminum wiring 107. At this time, when an abnormal pulsating negative voltage is applied from the wiring 109, a diode between the impurity layer 102 and a P-type silicon substrate 101 is conducted in the forward direction. Thus, the pulsating abnormal voltage is absorbed. When an abnormal pulsating positive voltage is applied, the abnormal voltage higher than the breakdown voltage of the diode between the impurity layer 102 and the substrate 101 is absorbed. In this way, a semiconductor device can be protected against the pulsating abnormal voltage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の静電保護装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrostatic protection device for semiconductor devices.

〔従来の技術〕[Conventional technology]

従来の半導体装置の静電保護装置を第３図（ａ）、（ｂ
）を用いて説明する０図において３０１はＰ型シリコン
基板、３０２はＮ型不純物層、３０３．３０６はシリコ
ン酸化膜、３０４はゲート酸化膜、３０５はゲート電極
、３０７．３０８はアルミニウム配線、３０９はアルミ
ニウムによる外部接続端子、３１０は外部へ配線を引き
出すためのボンディング配線である。ここでＮ型不純物
層３０２は、Ｐ型シリコン基板３０１との間にＰＮ接合
ダイオードを形成している。外部からの信号はボンディ
ング配線３１０、外部接続端子３０９、アルミニウム配
線３０８を通り、Ｎ型不純物層３０２を介した後、アル
ミニウム配線３０７を通り、ゲート電［！３０５に入力
される。このとき外部からの信号に異常な負電圧が加わ
ると、Ｎ型不純物層３０２とＰ型シリコン基板３０１と
の間のダイオードが順方向に導通することで異常電圧が
吸収され、ゲート電極３０５には電圧の絶対値が該ダイ
オードの順方向電圧以上の異常な電圧は加わらない、ま
た、外部からの信号に異常な正電圧が加えられると、Ｎ
型不純物層３０２とＰ型シリコン基板３０１との間のダ
イオードの降伏電圧以上の異常電圧が吸収され、ゲート
電［３０５には降伏電圧以上の異常な電圧は加わらない
。Conventional electrostatic protection devices for semiconductor devices are shown in Figures 3(a) and (b).
), 301 is a P-type silicon substrate, 302 is an N-type impurity layer, 303.306 is a silicon oxide film, 304 is a gate oxide film, 305 is a gate electrode, 307.308 is an aluminum wiring, 309 310 is an external connection terminal made of aluminum, and 310 is a bonding wiring for leading out wiring to the outside. Here, the N-type impurity layer 302 forms a PN junction diode between it and the P-type silicon substrate 301. Signals from the outside pass through the bonding wiring 310, the external connection terminal 309, the aluminum wiring 308, the N-type impurity layer 302, the aluminum wiring 307, and the gate electrode [! 305. At this time, if an abnormal negative voltage is applied to the external signal, the diode between the N-type impurity layer 302 and the P-type silicon substrate 301 becomes conductive in the forward direction, absorbing the abnormal voltage, and the gate electrode 305 absorbs the abnormal voltage. An abnormal voltage whose absolute value is greater than the forward voltage of the diode will not be applied, and if an abnormal positive voltage is applied to an external signal, N
An abnormal voltage higher than the breakdown voltage of the diode between the type impurity layer 302 and the P-type silicon substrate 301 is absorbed, and no abnormal voltage higher than the breakdown voltage is applied to the gate voltage [305].

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前述の従来技術では、外部からの異常な電圧が
パルス状の電圧であった場合、パルスの立ち上がり時間
、アルミニウム配線３０８の厚さや幅や長さ、シリコン
酸化膜３０３．３０６の厚さにより、パルス状の異常電
圧が外部接続端子３０つとＮ型不純物層３０２間で入射
・反射をくり返し、その間にシリコン酸化膜３０３．３
０６がパルス状異常電圧により絶縁破壊を起こし、外部
接続端子３０９とシリコン基板３０１、あるいはアルミ
ニウム配線３０８とシリコン基板３０１が導通してしま
うという問題点を有していた。However, in the above-mentioned conventional technology, when the abnormal voltage from the outside is a pulse-like voltage, the rise time of the pulse, the thickness, width, and length of the aluminum wiring 308, and the thickness of the silicon oxide films 303 and 306 , a pulse-like abnormal voltage is repeatedly incident and reflected between the 30 external connection terminals and the N-type impurity layer 302, and in between, the silicon oxide film 303.3
06 has a problem in that dielectric breakdown occurs due to pulsed abnormal voltage, resulting in conduction between the external connection terminal 309 and the silicon substrate 301, or between the aluminum wiring 308 and the silicon substrate 301.

そこで本発明は、このような問題点を解決するもので、
その目的とするところは外部からパルス状の異常電圧が
加わっても、外部接続端子と半導体基板間の絶縁膜が破
壊しない半導体装置を提供するところにある。Therefore, the present invention aims to solve these problems.
The purpose is to provide a semiconductor device in which an insulating film between an external connection terminal and a semiconductor substrate does not break down even if an abnormal pulse-like voltage is applied from the outside.

〔課題を解決するための手段〕 本発明の半導体装置は、第１導電型の半導体基板に設け
られた前記半導体基板と反対導電型の不純物層からなる
第１の領域と、前記半導体基板上に設けられた金属膜を
有する半導体装置において、前記第１の領域上に前記第
１の領域と接続して前記金属膜が設けられ、前記金属膜
が前記半導体装置の外部接続端子であることを特徴とす
る。[Means for Solving the Problems] A semiconductor device of the present invention includes a first region provided on a semiconductor substrate of a first conductivity type and comprising an impurity layer of a conductivity type opposite to that of the semiconductor substrate; A semiconductor device having a metal film provided thereon, wherein the metal film is provided on the first region and connected to the first region, and the metal film is an external connection terminal of the semiconductor device. shall be.

〔実　施　例〕〔Example〕

本発明の実施例を第１図（ａ）、（ｂ）、第２図（ａ）
〜（ｆ）を用いて詳しく説明する。第１図は本発明の一
実施例を示す断面図であるが、１０１はＰ型シリコン基
板、１０２はＮ型不純物層、１０３．１０６はシリコン
酸化膜、１０４はゲート酸化膜、１０５はゲート電極、
１０７はアルミニウム配線、１０８はアルミニウムによ
る外部接続端子、１０９は外部へ配線を引き出すための
ボンディング配線である０次に、この実施例の工程断面
図を第２図を用いて説明する。まず、Ｐ型シリコン基板
上に１０００℃ドライ酸化により１０００Ａのシリコン
酸化膜を形成後、シリコン窒化膜をＣＶＤ法により２０
０ＯＡ形成する０次に写真蝕刻法によりシリコン窒化膜
の不要部分を除去後、ウェット雰囲気で約７時間酸化し
約１μｍの厚い酸化膜を形成し、その後詰シリコン窒化
膜を除去する。これらの工程により第２図（ａ）のよう
にＰ型シリコン基板２０１上に素子分離用シリコン酸化
膜２０３が形成される６次に１０００℃ドライ酸化によ
り５００Ａのシリコン酸化膜を形成し、続いてＣＶＤ法
により５０００Ａの多結晶シリコン膜を形成し、この多
結晶シリコン膜に９ｏｏ’ｃでリンの熱拡散を行なう。Examples of the present invention are shown in FIGS. 1(a), (b), and 2(a).
-(f) will be used to explain in detail. FIG. 1 is a cross-sectional view showing one embodiment of the present invention, in which 101 is a P-type silicon substrate, 102 is an N-type impurity layer, 103 and 106 are silicon oxide films, 104 is a gate oxide film, and 105 is a gate electrode. ,
107 is an aluminum wiring, 108 is an external connection terminal made of aluminum, and 109 is a bonding wiring for leading out the wiring to the outside.Next, a process cross-sectional view of this embodiment will be explained using FIG. 2. First, a silicon oxide film of 1000A is formed on a P-type silicon substrate by dry oxidation at 1000°C, and then a silicon nitride film of 20A is formed by CVD.
After removing unnecessary portions of the silicon nitride film by photolithography, oxidation is performed in a wet atmosphere for about 7 hours to form a thick oxide film of about 1 μm, and the subsequent filling silicon nitride film is removed. Through these steps, a silicon oxide film 203 for element isolation is formed on the P-type silicon substrate 201 as shown in FIG. A 5000A polycrystalline silicon film is formed by CVD, and phosphorus is thermally diffused into this polycrystalline silicon film at 900°C.

次に写真蝕刻法により該多結晶シリコン膜の不要部分を
除去して第２図（ｂ）のようにゲート酸化膜２０４、ゲ
ート電極２０５を形成する０次にイオン注入によりヒ素
を注入エネルギー１００Ｋｅ　ｖ、注入ドーズ量ｌＸｌ
０１６ｃｍ””でイオン注入した後、１０００℃の熱処
理を行ない、第２図（ｃ）のようにＮ型不純物層２０２
を形成する０次にＣＶＤ法によりシリコン酸化膜を５０
０ＯＡ形成後、写真蝕刻法により不要部分を除去して第
２図（ｄ）のようにシリコン酸化膜２０６にコンタクト
ホールを形成する０次にスパッタ法によりアルミニウム
を１μｍ形成した後、写真蝕刻法により不要部分を除去
して第２図（ｅ）のようにアルミニウム配線２０７、外
部接続端子２０８を形成する０次に該半導体装置と外部
装置との接続、あるいは該半導体装置とパッケージとの
接続のため、第２図（ｆ）のように外部接続端子２０８
からボンディング配線２０９を形成する。Next, unnecessary parts of the polycrystalline silicon film are removed by photolithography to form a gate oxide film 204 and a gate electrode 205 as shown in FIG. 2(b). Arsenic is implanted by ion implantation at an energy of 100 Ke v , implantation dose lXl
After ion implantation at 0.016 cm'', heat treatment at 1000°C is performed to form an N-type impurity layer 202 as shown in FIG. 2(c).
A silicon oxide film of 50% is deposited by the zero-order CVD method to form
After forming the OA, unnecessary parts are removed by photolithography to form a contact hole in the silicon oxide film 206 as shown in FIG. Unnecessary parts are removed and aluminum wiring 207 and external connection terminals 208 are formed as shown in FIG. , as shown in FIG. 2(f), the external connection terminal 208
A bonding wiring 209 is then formed.

第１図による本発明の実施例では、外部からの信号はボ
ンディング配線１０９、外部接続端子１０８を通り、Ｎ
型不純物層１０２を介した後、アルミニウム配線１０７
を通り、ゲート電極１０５に入力される。このとき、ボ
ンディング配線１０９から入力される外部からの信号に
異常なパルス状の負電圧が加わると、Ｎ型不純物層１０
２とＰ型シリコン基板１０１との間のダイオードが順方
向に導通することでパルス状の異常電圧が吸収され、ア
ルミニウム配線１０７およびゲート電極１０５には電圧
の絶対値が該ダイオードの順方向電圧以上の異常な電圧
は加わらない。また外部からの信号に異常なパルス状の
正電圧が加わると、Ｎ型不純物層１０２とＰ型シリコン
基板１０１との間のダイオードの降伏電圧以上の異常電
圧が吸収され、アルミニウム配線１０７およびゲート電
極１０５には該ダイオードの降伏電圧以上の異常な電圧
は加わらない。In the embodiment of the present invention shown in FIG.
After passing through the type impurity layer 102, the aluminum wiring 107
and is input to the gate electrode 105. At this time, if an abnormal pulse-like negative voltage is applied to the external signal input from the bonding wiring 109, the N-type impurity layer 10
The diode between 2 and the P-type silicon substrate 101 conducts in the forward direction, absorbing the pulse-like abnormal voltage, and the absolute value of the voltage on the aluminum wiring 107 and the gate electrode 105 exceeds the forward voltage of the diode. No abnormal voltage is applied. Furthermore, when an abnormal pulse-like positive voltage is applied to an external signal, the abnormal voltage higher than the breakdown voltage of the diode between the N-type impurity layer 102 and the P-type silicon substrate 101 is absorbed, and the aluminum wiring 107 and gate electrode No abnormal voltage higher than the breakdown voltage of the diode is applied to 105.

本実施例ではＮ型拡散層１０２はヒ素で形成したが他に
リン、アンチモンを用いてもよい、また、ヒ素とリンな
どのように、これらの不純物を同時に導入して形成して
もよい。また、保護ダイオードとしてＰ型シリコン基板
にＮ型不純物を導入してダイオードとしたが、Ｎ型シリ
コン基板にＰ型不純物を導入したダイオードでもよい、
この場合Ｐ型不純物としてはホウ素、アルミニウム、ガ
リウム等を用いる。また、ホウ素とアルミニウムのよう
に、これらの不純物を同時に導入して形成してもよい。In this embodiment, the N-type diffusion layer 102 is formed of arsenic, but phosphorus or antimony may also be used, or these impurities, such as arsenic and phosphorus, may be introduced at the same time. In addition, although the protection diode was made by introducing an N-type impurity into a P-type silicon substrate, a diode in which a P-type impurity was introduced into an N-type silicon substrate may also be used.
In this case, boron, aluminum, gallium, etc. are used as the P-type impurity. Further, impurities such as boron and aluminum may be introduced at the same time.

さらに本実施例では外部接続端子にアルミニウムを用い
たが、銅、クロムなどの金属やタングステン、チタン、
モリブデンなどの高融点金属を用いてもよい、さらに外
部装置への配線は本実施例におけるボンディング配線だ
けでなく、ハンダリフローによる配線を用いてもよい。Furthermore, although aluminum was used for the external connection terminals in this example, metals such as copper, chromium, tungsten, titanium, etc.
A high-melting point metal such as molybdenum may be used. Furthermore, wiring to an external device may be performed not only by bonding wiring in this embodiment but also by solder reflow wiring.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、外部からパルス状の
異常電圧が加わっても、異常電圧は外部接続端子の下に
あるダイオードにより吸収されるため、外部接続端子と
半導体基板間の絶縁膜および、外部接続端子からグー１
〜電極への配線と半導体基板間の絶縁膜は破壊しない、
よって半導体装置の検査、ダイシング、選別、実装時に
発生する静電気破壊による歩留まり低下が避けられる効
果がある。さらに、静電保護ダイオードが外部接続端子
下にあるため静電保護ダイオード用の面積が縮小でき、
半導体装置の微細化、高集積化に大きな効果がある。As described above, according to the present invention, even if a pulse-like abnormal voltage is applied from the outside, the abnormal voltage is absorbed by the diode under the external connection terminal, so that the insulating film between the external connection terminal and the semiconductor substrate And goo 1 from the external connection terminal
~The insulation film between the wiring to the electrode and the semiconductor substrate will not be destroyed.
Therefore, it is possible to avoid a decrease in yield due to electrostatic damage that occurs during inspection, dicing, sorting, and mounting of semiconductor devices. Furthermore, since the electrostatic protection diode is located below the external connection terminal, the area for the electrostatic protection diode can be reduced.
This has a great effect on miniaturization and higher integration of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明の半導体装置の一実施例
を示す平面図（ａ）と主要断面図（ｂ）。 第２図（ａ）〜（ｆ）は本発明の半導体装置の一実施例
を示す工程順断面図。 第３図（ａ）、（ｂ）は従来例による半導体装置の平面
図（ａ）と主要断面図（ｂ）である。 １０１．２０１．３０１・・Ｐ型シリコン基板１０２．
２０２．３０２・・Ｎ型不純物層１０３．２０３．３０
３．１０６．２０６．３０６・・シリコン酸化膜 １０４．２０４．３０４・・ゲート酸化膜１０５．２０
５．３０５・　・ゲート電極１０７．２０７．３０７．
３０８ ・・・アルミニウム電極 １０８．２０８．３０９・・外部接続端子１０９．２０
９．３１０・・ボンディング配線以上 出願人　セイコーエプソン株式会社 （す （し） 元　１目 Ｃｔ）　　　　　　　　　　　　　　　　　　　　　（
し）（ｃ−）　　　　　　　　　　　　　　（＜）（ｅ
）　　　　　　　　　　　　　　びジ（ａ−） ｏｌFIGS. 1(a) and 1(b) are a plan view (a) and a main cross-sectional view (b) showing an embodiment of the semiconductor device of the present invention. FIGS. 2(a) to 2(f) are process-order sectional views showing an embodiment of the semiconductor device of the present invention. FIGS. 3(a) and 3(b) are a plan view (a) and a main cross-sectional view (b) of a conventional semiconductor device. 101.201.301...P-type silicon substrate 102.
202.302...N-type impurity layer 103.203.30
3.106.206.306...Silicon oxide film 104.204.304...Gate oxide film 105.20
5.305・Gate electrode 107.207.307.
308...Aluminum electrode 108.208.309...External connection terminal 109.20
9.310... Bonding wiring and above Applicant: Seiko Epson Corporation (formerly 1st Ct) (
shi)(c-)(<)(e
) Biji (a-) ol

Claims (1)

【特許請求の範囲】[Claims] 　第１導電型の半導体基板に設けられた前記半導体基板
と反対導電型の不純物層からなる第１の領域と、前記半
導体基板上に設けられた金属膜を有する半導体装置にお
いて、前記第１の領域上に前記第１の領域と接続して前
記金属膜が設けられ、前記金属膜が前記半導体装置の外
部接続端子であることを特徴とする半導体装置。A semiconductor device comprising: a first region formed on a semiconductor substrate of a first conductivity type and comprising an impurity layer of a conductivity type opposite to that of the semiconductor substrate; and a metal film provided on the semiconductor substrate; A semiconductor device, characterized in that the metal film is provided thereon and connected to the first region, and the metal film is an external connection terminal of the semiconductor device.
JP63014266A 1988-01-25 1988-01-25 Semiconductor device Pending JPH01189143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63014266A JPH01189143A (en) 1988-01-25 1988-01-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63014266A JPH01189143A (en) 1988-01-25 1988-01-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01189143A true JPH01189143A (en) 1989-07-28

Family

ID=11856289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63014266A Pending JPH01189143A (en) 1988-01-25 1988-01-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01189143A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2221862A1 (en) * 2007-11-16 2010-08-25 Toyota Jidosha Kabushiki Kaisha Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2221862A1 (en) * 2007-11-16 2010-08-25 Toyota Jidosha Kabushiki Kaisha Semiconductor device
EP2221862A4 (en) * 2007-11-16 2013-11-27 Toyota Motor Co Ltd Semiconductor device
US8674511B2 (en) 2007-11-16 2014-03-18 Toyota Jidosha Kabushiki Kaisha Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surface

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