JPH03101130A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03101130A JPH03101130A JP23791189A JP23791189A JPH03101130A JP H03101130 A JPH03101130 A JP H03101130A JP 23791189 A JP23791189 A JP 23791189A JP 23791189 A JP23791189 A JP 23791189A JP H03101130 A JPH03101130 A JP H03101130A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- impurities
- insulating film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 229910052796 boron Inorganic materials 0.000 claims abstract description 5
- 239000010936 titanium Substances 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 22
- 230000001681 protective effect Effects 0.000 abstract description 16
- 239000011229 interlayer Substances 0.000 abstract description 9
- 229910021645 metal ion Inorganic materials 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 239000000356 contaminant Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、さらに詳し
くは、半導体装置に侵入する汚染不純物のゲンタリング
に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to Gentering of contaminating impurities that enter a semiconductor device.
半導体装置は、装置Gこ侵入する汚染不純物の影響によ
りその性能は大きく左右される。又、近年の半導体集積
回路装置の高集積化は著しいものがあり、微量の汚染不
純物でも悪影響を及ぼし、その対策としてゲンタリング
技術は、クリーン化技術と共に今後いっそう重要である
。The performance of a semiconductor device is greatly influenced by the influence of contaminant impurities that enter the device G. In addition, in recent years, semiconductor integrated circuit devices have become extremely highly integrated, and even a small amount of contaminating impurities can have an adverse effect, and as a countermeasure against this, the gentering technology, along with the cleaning technology, will become even more important in the future.
第2図は従来の半導体装置の製造方法(こよって製造さ
れた半導体素子の一例であるNMOSトランジスタc以
下NMO8Tと称す)の構造を模式的に示す断面図であ
る。FIG. 2 is a cross-sectional view schematically showing the structure of a conventional semiconductor device manufacturing method (an example of a semiconductor device manufactured using this method is an NMOS transistor c, hereinafter referred to as NMO8T).
第2図において、(1)はP型のシリコン単結晶基板、
(2)は素子間を分離するためのフィールド酸化膜、(
3)および(4)はNMO8Tのソース領域およびドレ
イン領域となるそれぞれに高濃度のN型不純物拡散層、
(5)はゲート酸化膜、(6)はゲート電極である。又
、(力は層間絶縁膜、(8)は第1のコンタクトホール
、(9)はアルミによる内部配線層、(1Gは保s膜、
aυは第2のコンタクトホール、@はアルミ電極配線層
である。In Figure 2, (1) is a P-type silicon single crystal substrate;
(2) is a field oxide film for isolating between elements, (
3) and (4) are highly concentrated N-type impurity diffusion layers in the source and drain regions of NMO8T, respectively.
(5) is a gate oxide film, and (6) is a gate electrode. (1G is an interlayer insulating film, (8) is a first contact hole, (9) is an internal wiring layer made of aluminum, (1G is an sulfur retaining film,
aυ is a second contact hole, and @ is an aluminum electrode wiring layer.
そして、この従来例の製造方法は、まずP型のシリコン
単結晶基板(1)に素子間分離のためのフィールド酸化
膜(2)を選択的に形成させ、その後ソース領域および
ドレイン領域+3)、(4)と、ゲート酸化膜(5)を
介したゲートit FM(61をそれぞれ選択的に形成
させ、これらの上を層間絶縁膜(7)で覆う。次(こ各
ソーズおよびドレイン領域(3)i4)の選択された所
定の部分に第1のコンタクトホール(8)を開口させ、
アルミによる内部配線層(9)を形成する。続いて、内
部配線層(9)を保護し、最低限必要である電極のみ引
き出すため憂こ、保護膜(1(Iを形成し、その後保護
膜員に第2のコンタクトホール0υを開口させ、アルミ
電極配線層0諺を形成する。In this conventional manufacturing method, first, a field oxide film (2) for isolation between elements is selectively formed on a P-type silicon single crystal substrate (1), and then a source region and a drain region (+3), (4) and a gate IT FM (61) via a gate oxide film (5) are selectively formed, and these are covered with an interlayer insulating film (7). ) i4) a first contact hole (8) is opened in a selected predetermined portion;
An internal wiring layer (9) made of aluminum is formed. Next, in order to protect the internal wiring layer (9) and draw out only the minimum necessary electrodes, a protective film (1) was formed, and then a second contact hole 0υ was opened by the protective film member. Form an aluminum electrode wiring layer.
しかしながら、前記した従来例による半導体装置の製造
方法の場合、層間絶縁膜および保護膜は、外環境からの
汚染不純物C金属イオン、H+、H,0等)を防ぐ役目
をしてはいるが、上記の影響を完全に遮断するものでは
ない0層間絶縁膜および保護膜中に汚染不純物が存在す
れば、半導体装置の特性を劣化させる原因となる。特に
H”Gまゲート酸化膜を還元する事蚤こよりゲート酸化
膜を劣化させ、又H20は有極性分子であるためリーク
電流を生じさせる事により素子特性を著しく劣化させる
。However, in the case of the conventional semiconductor device manufacturing method described above, although the interlayer insulating film and the protective film serve to prevent contaminant impurities (C metal ions, H+, H, 0, etc.) from the external environment, If contaminant impurities are present in the zero interlayer insulating film and the protective film, which do not completely block the above effects, they will cause deterioration of the characteristics of the semiconductor device. In particular, reducing the gate oxide film of H''G deteriorates the gate oxide film, and since H20 is a polar molecule, it causes a leakage current, thereby significantly degrading the device characteristics.
この発明は、従来のこのような問題点を解消するために
なされたもので、その目的とするところは、絶縁膜中の
汚染不純物を捕獲させる事のできる半導体装置の製造方
法を提供することである。This invention was made to solve these conventional problems, and its purpose is to provide a method for manufacturing a semiconductor device that can trap contaminant impurities in an insulating film. be.
前記目的を達成するために、この発明【こ係る半導体装
置の製造方法は、絶縁膜中の汚染不純物を捕獲するため
に、絶縁膜中にチタン、リン、砒素又はボロンを含有さ
せる工程を含む事を特徴とする。In order to achieve the above object, the present invention [this method of manufacturing a semiconductor device includes a step of incorporating titanium, phosphorus, arsenic, or boron into an insulating film in order to capture contaminant impurities in the insulating film] It is characterized by
すなわち、この発明においては、半導体装置の絶縁膜に
チタン、リン、砒素、又はボロンが含有されているため
に、含有された上記物質が上記膜中の汚染不純物と反応
する事により汚染不純物を捕獲し、これら汚染不純物の
半導体装置への悪影響を取り除く事ができるのである。That is, in this invention, since the insulating film of the semiconductor device contains titanium, phosphorus, arsenic, or boron, the contained substances react with the contaminant impurities in the film to capture the contaminant impurities. However, the adverse effects of these contaminant impurities on the semiconductor device can be removed.
以下、この発明に係る半導体装置の製造方法の一実施例
について、チタン(Ti)を保護膜中に含有させる場合
について、第1図を参照して鮮細に説明する。Hereinafter, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIG. 1, regarding a case where titanium (Ti) is contained in a protective film.
第1図(a)ないしくe)はこの実施例を適用したNM
OSトランジスタの製造方法を示すもので、主要な製造
工程を順次模式的に示すそれぞれに断面図である。Figures 1(a) to 1(e) show NMs to which this embodiment is applied.
1A and 1B illustrate a method for manufacturing an OS transistor, each of which is a cross-sectional view schematically illustrating the main manufacturing steps sequentially.
すなわち、第1図においても、C1)はP型のシリコン
単結晶基板、(2)は素子間を分離するためのフィール
ド酸化膜、(3)および(4)はNMOSのソース領域
およびドレイン領域となるそれぞれに高濃度のN型不純
物拡散層、(5)はゲート酸化膜、(6)はゲート電極
である0又、(7)は層間絶縁膜、(8)は第1のコン
タクトホール、C9)g;tアルミによる内部配線層、
aOは保護膜、0ηは第2のコンタクトホール、(2)
はアルミ電極配線層である。さらに、(2)はレジスト
膜、α尋は注入されたチタンである。That is, in FIG. 1, C1) is a P-type silicon single crystal substrate, (2) is a field oxide film for separating elements, and (3) and (4) are NMOS source and drain regions. (5) is a gate oxide film, (6) is a gate electrode, (7) is an interlayer insulating film, (8) is a first contact hole, and C9 is a high concentration N-type impurity diffusion layer. ) g; t internal wiring layer made of aluminum,
aO is the protective film, 0η is the second contact hole, (2)
is an aluminum electrode wiring layer. Furthermore, (2) is a resist film, and α fathom is injected titanium.
そして、製造方法は、まずP型のシリコン単結晶基板(
1)上に素子間分離のためのフィールド酸化膜(2)を
選択的に形成させ、その後ソース領域およびドレイン領
域13)、 C4)とゲート酸化膜(5)を介したゲー
ト電極(6)をそれぞれ選択的に形成させ、これらの上
を層間絶aiil膜(7)で覆う。次に各ソースおよび
ドレイン領域(3)、(4)の選択された所定の部分に
第1のコンタクトホール(8)を開口させ、アルミによ
る内部配線層(9)を形成させる。(第1図(a))。The manufacturing method begins with a P-type silicon single crystal substrate (
1) A field oxide film (2) for isolation between elements is selectively formed on top, and then a gate electrode (6) is formed through the source and drain regions 13), C4) and the gate oxide film (5). These are selectively formed and covered with an interlayer insulation film (7). Next, a first contact hole (8) is opened in a selected predetermined portion of each source and drain region (3), (4), and an internal wiring layer (9) made of aluminum is formed. (Figure 1(a)).
続いて、内部配線層(9)を保護し、最低限必要である
電極のみ引き出すために保護膜C1lを形成する。Subsequently, a protective film C1l is formed to protect the internal wiring layer (9) and draw out only the minimum necessary electrodes.
(第1図(b) ) 、保饅膜員としては、酸化膜(S
1O3)、窒化膜(Si3N4)、スピンオングラス
(SOG)などの使用が可能であり、アルミニ程以降に
形成される膜であるため、酸化膜(Si02)、窒化膜
(Si、N4)はアルミの融点以下の低温プロセスのプ
ラズマCVD法により形成する。(Figure 1(b)) As a protective film member, an oxide film (S
1O3), nitride film (Si3N4), spin-on glass (SOG), etc. can be used, and since it is a film formed after aluminum, oxide film (Si02) and nitride film (Si, N4) can be used on aluminum. It is formed by plasma CVD, a low temperature process below the melting point.
次に保護膜四の所定の部分に第2のコンタクトホール0
ηを開口させ、アルミ電極配線層@を形成する。(第1
図(C))。Next, a second contact hole 0 is formed in a predetermined portion of the protective film 4.
η is opened and an aluminum electrode wiring layer @ is formed. (1st
Figure (C)).
その後チタンを保護膜(10中番こ含有させる。まずア
ルミ電極配線層@の表面を覆うよう(こレジスト膜03
を第1図(d)のように形成する。これはアルε電極配
線層(2)と保護膜uQ中のチタンα尋がショートする
のを防ぐためである。続いて、チタンをイオン注入機を
用いて保獲膜ul中に注入する。(第1図(d))。After that, titanium is included in a protective film (10th grade).First, it covers the surface of the aluminum electrode wiring layer (this resist film 03).
is formed as shown in FIG. 1(d). This is to prevent a short circuit between the aluminum ε electrode wiring layer (2) and the titanium α fat in the protective film uQ. Subsequently, titanium is injected into the retention membrane ul using an ion implanter. (Figure 1(d)).
最後にレジスト膜(至)を除去する。(第1図(e))
0以上のような製造方法でチタンを保護中に含有させる
わけであるが、チタンは真空ポンプであるゲンターボン
プに利用されているように、活性な金属である。そのた
め保護膜中に注入されたチタンによ−〕で、保護膜中に
存在するH+% H,0又は金属イオンなどの汚染不純
物を捕獲する事ができ、それら汚染不純物による半導体
装置への悪影響を取り除く事ができる。Finally, the resist film is removed. (Figure 1(e))
Although titanium is contained in the protection using the manufacturing method described above, titanium is an active metal, as is used in Genter Bump, a vacuum pump. Therefore, the titanium implanted into the protective film can capture contaminant impurities such as H+%H,0 or metal ions that exist in the protective film, thereby preventing the adverse effects of these contaminant impurities on the semiconductor device. It can be removed.
なお、前記実施例では保護膜中にチタンを含有させる事
Gこよって汚染不純物を捕獲したが2層間絶縁膜中の汚
線不純物も同様の方法で捕獲する事ができる。In the above embodiment, the contaminating impurities were captured by including titanium in the protective film, but the dirty line impurities in the interlayer insulating film can also be captured by the same method.
又、前記実施例ではチタンを用いたが、リンP)、砒素
(As)、ポロン(B)を用いても同様の効果を得る事
ができる。Further, although titanium was used in the above embodiment, similar effects can be obtained by using phosphorus (P), arsenic (As), or poron (B).
又、前記実施例ではNMO8)ランジスタの製造方法を
示したが、半導体装置の構成において、絶縁膜を有する
ものであればよい。Further, in the above embodiment, a method for manufacturing an NMO8) transistor was shown, but any structure of a semiconductor device may be used as long as it has an insulating film.
以上詳述したように、この発明によれば、半導体装置の
絶縁膜中にチタン、リン、砒素又はポロンを含有させた
ので、それらの物質が上記膜中の汚染不純物を捕獲し、
汚染不純物による半導体装置への悪影響を取り除く事が
でき、半導体装置の信頼性を向上させる事ができる。As detailed above, according to the present invention, since titanium, phosphorus, arsenic, or poron is contained in the insulating film of a semiconductor device, these substances capture contaminant impurities in the film,
The adverse influence of contaminating impurities on a semiconductor device can be removed, and the reliability of the semiconductor device can be improved.
第1図(a)ないしくe)は、この発明の一実施例を適
用した半導体装置の製造方法を示すもので、主要な製造
工程を順次模式的に示すそれぞれに断面図であり、また
、第2図は従来の製造方法による半導体装置の構造を模
式的に示す断面図である。
図において、(7)は層間絶縁膜、顛は保護膜、α荀は
含有されたチタンである。
なお、図中、同一符号は同一、または相当部分を示す。FIGS. 1(a) to 1(e) show a method for manufacturing a semiconductor device to which an embodiment of the present invention is applied, each of which is a cross-sectional view schematically showing the main manufacturing steps sequentially. FIG. 2 is a cross-sectional view schematically showing the structure of a semiconductor device manufactured by a conventional manufacturing method. In the figure, (7) is an interlayer insulating film, the back is a protective film, and α is the contained titanium. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
絶縁膜中にチタン、リン、砒素又はボロンを含有させる
工程を含むことを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device having an insulating film,
1. A method for manufacturing a semiconductor device, comprising the step of incorporating titanium, phosphorus, arsenic, or boron into an insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23791189A JPH03101130A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23791189A JPH03101130A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03101130A true JPH03101130A (en) | 1991-04-25 |
Family
ID=17022268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23791189A Pending JPH03101130A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03101130A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
-
1989
- 1989-09-13 JP JP23791189A patent/JPH03101130A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
US6268657B1 (en) | 1995-09-14 | 2001-07-31 | Sanyo Electric Co., Ltd. | Semiconductor devices and an insulating layer with an impurity |
US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
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