JPH01188122A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPH01188122A JPH01188122A JP63010757A JP1075788A JPH01188122A JP H01188122 A JPH01188122 A JP H01188122A JP 63010757 A JP63010757 A JP 63010757A JP 1075788 A JP1075788 A JP 1075788A JP H01188122 A JPH01188122 A JP H01188122A
- Authority
- JP
- Japan
- Prior art keywords
- current
- circuit
- logic
- transistor
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 6
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
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- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、論理演算内容を変更でき、しかも低電源電圧
で動作するようにした論理回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit that can change the content of logic operations and operates at a low power supply voltage.
従来、論理回路は74LSで代表されるように動作のた
めに数V以上の高電圧を必要とし、また論理演算内容は
固定であった。Conventionally, logic circuits, as typified by 74LS, require a high voltage of several volts or more for operation, and the content of logic operations is fixed.
従って、上記のような論理回路では、低電圧駆動が不可
能であり、また他の論理演算に変更する場合には回路の
変更が必要であった。Therefore, the logic circuit as described above cannot be driven at a low voltage, and when changing to other logical operations, the circuit needs to be changed.
本発明の目的は、低電圧駆動が可能でしかも回路変更な
しで論理演算内容の切替も可能となった論理回路を提供
することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit that can be driven at a low voltage and also allows switching of logic operations without changing the circuit.
このために本発明は、2以上の入力電圧を電流信号に変
換する電流変換回路と、該電流変換回路で変換された電
流を合成する電流合成回路と、変化可能なスレッショル
ド電流と合成電流とを比較しその比較結果を出力する電
流比較回路とでなり、各回路を電源/接地間2個直列の
トランジスタ素子で構成した。To this end, the present invention provides a current conversion circuit that converts two or more input voltages into a current signal, a current synthesis circuit that synthesizes the currents converted by the current conversion circuit, and a variable threshold current and composite current. It consists of a current comparator circuit that compares and outputs the comparison result, and each circuit is composed of two transistor elements connected in series between the power supply and the ground.
以下、本発明の実施例について説明する。第1図はその
一実施例の論理回路の回路を示す図である、1は入力電
圧を電流信号に変換する電流変換回路、2は電流を合成
する電流合成回路、3は合成電流をスレッショルド電流
と比較する電流比較回路であり、いずれの回路も電源ラ
イン(Vcc)と接地ライン間に、2個のトランジスタ
を直列接続して構成されている。トランジスタQ1、C
5、C13、C14はトランジスタQ18と共にカレン
トミラーを構成し、それらには定電流源4の電流Iと同
じ電流が流れる。Examples of the present invention will be described below. FIG. 1 is a diagram showing a logic circuit according to an embodiment of the present invention. 1 is a current conversion circuit that converts an input voltage into a current signal, 2 is a current synthesis circuit that synthesizes currents, and 3 is a diagram that converts the combined current into a threshold current. Both circuits are constructed by connecting two transistors in series between a power supply line (Vcc) and a ground line. Transistor Q1, C
5, C13, and C14 constitute a current mirror together with the transistor Q18, and the same current as the current I of the constant current source 4 flows through them.
電流変換回路1は、入力端子TNI、IN2に印加する
電圧信号を、トランジスタQl、Q5に流れる電流信号
に変化する。トランジスタQ2に印加する電圧信号はト
ランジスタQ3、C4で電流方向を反転し、またトラン
ジスタQ6に印加する電圧信号はトランジスタQ7、C
8で電流方向を反転する。The current conversion circuit 1 converts voltage signals applied to input terminals TNI and IN2 into current signals flowing through transistors Ql and Q5. The voltage signal applied to transistor Q2 has its current direction reversed by transistors Q3 and C4, and the voltage signal applied to transistor Q6 has its current direction reversed by transistors Q7 and C4.
8 to reverse the current direction.
そして、この反転された電流は、カレントミラーを構成
するトランジスタQ9、QIOでなる電流合成回路2の
トランジスタQ9に入力されて合成され、トランジスタ
Q10のコレクタから出力する。Then, this inverted current is input to the transistor Q9 of the current combining circuit 2 including the transistors Q9 and QIO forming a current mirror, and is combined, and is output from the collector of the transistor Q10.
電流比較回路3においては、比較基準値、つまりスレッ
ショルド電流がトランジスタQllとC15を流れる電
流の合計値Isで決定される。論理切換端子L−INが
「Ljのときは、トランジスタQ15はオンしてその電
流値が電流源4の電流と同じ電流Iとなり、一方論理切
換端子L−INが’HJのときは、そのトランジスタQ
15はオフする。また、トランジスタQllとC12は
常時オンしている。このトランジスタQllとC12は
面積比が2の関係にあり、トランジスタQ12に電流■
が流れるときトランジスタQllにはvrの電流が流れ
る。In the current comparison circuit 3, the comparison reference value, that is, the threshold current, is determined by the total value Is of the currents flowing through the transistors Qll and C15. When the logic switching terminal L-IN is "Lj", the transistor Q15 is turned on and its current value becomes the current I, which is the same as the current of the current source 4. On the other hand, when the logic switching terminal L-IN is "HJ", the transistor Q
15 is off. Further, transistors Qll and C12 are always on. These transistors Qll and C12 have an area ratio of 2, and a current of
When Qll flows, a current vr flows through the transistor Qll.
以上から、論理切換端子L−INが’LJのときは、ト
ランジスタQ17がオフ、トランジスタQ15、C16
がオンとなり、トランジスタQ15を流れる電流Iとト
ランジスタQllを流れる電流zIの合計値が電流比較
回路3のスレッショルド電流Isとなる。From the above, when the logic switching terminal L-IN is 'LJ', the transistor Q17 is off, and the transistors Q15, C16
is turned on, and the sum of the current I flowing through the transistor Q15 and the current zI flowing through the transistor Qll becomes the threshold current Is of the current comparison circuit 3.
l5=I+%I干3I/2
また論理切換端子L−INが’HJのときは、トランジ
スタQ15、C16がオフであるので、トランジスタQ
llを流れる電流%Iが、スレッショルド電流Isとな
る。l5=I+%I3I/2 Also, when the logic switching terminal L-IN is 'HJ', transistors Q15 and C16 are off, so transistor Q
The current %I flowing through ll becomes the threshold current Is.
Is=%I
そして、トランジスタQIOのコレクタから出力する電
流の内から、上記したスレッショルド電流を差し引いた
電流がトランジスタQ19のペース流入する。Is=%I Then, a current obtained by subtracting the above threshold current from the current output from the collector of the transistor QIO flows into the transistor Q19.
第2図はこの回路のタイミングチャートを示したもので
ある。入力端子INI、IN2に第2図(a)、(b)
に示すような波形の電圧を印加したとき、トランジスタ
Q4のコレクタには(d)に示す波形の電流が、またト
ランジスタQ8のコレクタにはtelに示す波形の電流
が流れ、それらの合成値の波形は(「)のQ101cに
示す波形となる。FIG. 2 shows a timing chart of this circuit. Figure 2 (a), (b) to input terminals INI and IN2.
When a voltage with the waveform shown in is applied, a current with the waveform shown in (d) flows through the collector of transistor Q4, a current with the waveform shown in tel flows through the collector of transistor Q8, and the waveform of their composite value is has the waveform shown in Q101c in (').
途中で論理切換端子L−INのレベルを第2図(C1に
示すように’LJから’HJに変化させれば、スレッシ
ョルド電流Isは(f)に示すような波形の電流となる
。If the level of the logic switching terminal L-IN is changed from 'LJ to 'HJ as shown in FIG. 2 (C1) during the process, the threshold current Is will have a waveform as shown in (f).
従って、トランジスタQ19のコレクタには、論理切換
端子L−INが’LJの間は再入力端子INI IN
2の論理の論理和(OR)の演算結果が、また「H」の
間は論理積(AND)の演算結果が電圧として出力され
ることなる。Therefore, the collector of the transistor Q19 has a re-input terminal INI IN while the logic switching terminal L-IN is 'LJ'.
The result of the logical sum (OR) of the two logics is output as a voltage, and the result of the logical product (AND) during "H" is output as a voltage.
以上のように本発明によれば、制御信号により論理を切
り換えることができ、またトランジスタ素子は電ra/
接地間に直列2個使用しているので、その電源電圧も低
電圧化することができる。As described above, according to the present invention, the logic can be switched by the control signal, and the transistor element can
Since two are used in series between the ground, the power supply voltage can also be lowered.
【図面の簡単な説明】
第1図は本発明の一実施例の論理回路の回路図、第2図
は同回路のタイミングチャートである。
l・・・電流変換回路、2・・・電流合成回路、3・・
・電流比較回路、4・・・定電流源、INI、IN2・
・・入力端子、L−IN・・・論理切換端子。
代理人 弁理士 長 尾 常 明BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a logic circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart of the same circuit. l...Current conversion circuit, 2...Current synthesis circuit, 3...
・Current comparison circuit, 4...constant current source, INI, IN2・
...Input terminal, L-IN...Logic switching terminal. Agent Patent Attorney Tsuneaki Nagao
Claims (2)
換回路と、該電流変換回路で変換された電流を合成する
電流合成回路と、変化可能なスレッショルド電流と合成
電流とを比較しその比較結果を出力する電流比較回路と
でなり、各回路を電源/接地間2個直列のトランジスタ
素子で構成したことを特徴とする論理回路。(1) Compare a current conversion circuit that converts two or more input voltages into a current signal, a current synthesis circuit that synthesizes the currents converted by the current conversion circuit, and a variable threshold current and the combined current. 1. A logic circuit comprising a current comparator circuit that outputs a comparison result, each circuit comprising two transistor elements connected in series between a power supply and a ground.
を入力する論理切換端子を有することを特徴とする特許
請求の範囲第1項記載の論理回路。(2) The logic circuit according to claim 1, further comprising a logic switching terminal into which a control signal for changing the threshold current is input.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63010757A JP2733545B2 (en) | 1988-01-22 | 1988-01-22 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63010757A JP2733545B2 (en) | 1988-01-22 | 1988-01-22 | Logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01188122A true JPH01188122A (en) | 1989-07-27 |
JP2733545B2 JP2733545B2 (en) | 1998-03-30 |
Family
ID=11759198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63010757A Expired - Fee Related JP2733545B2 (en) | 1988-01-22 | 1988-01-22 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2733545B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49118357A (en) * | 1973-03-14 | 1974-11-12 | ||
JPS5092154U (en) * | 1973-12-27 | 1975-08-04 | ||
JPS524139A (en) * | 1975-06-23 | 1977-01-13 | Nippon Signal Co Ltd:The | Sales data processing system |
-
1988
- 1988-01-22 JP JP63010757A patent/JP2733545B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49118357A (en) * | 1973-03-14 | 1974-11-12 | ||
JPS5092154U (en) * | 1973-12-27 | 1975-08-04 | ||
JPS524139A (en) * | 1975-06-23 | 1977-01-13 | Nippon Signal Co Ltd:The | Sales data processing system |
Also Published As
Publication number | Publication date |
---|---|
JP2733545B2 (en) | 1998-03-30 |
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