JPS62107521A - Conditional branching circuit - Google Patents

Abstract

PURPOSE:To attain plural conditional branchings in response to a potential of an input signal by providing a means setting a potential range corresponding to plural branching destination stored by a register with respect to an input signal thereby deciding the potential range of the input signal and a conditional branching logic circuit controlling the branching. CONSTITUTION:An output signal of comparators 17-20 is converted into a signal as shown in the truth table by a logic circuit 11 and the result is inputted to a conditional branching logic circuit 12 as a selection signal for a register 13 storing the branch destination address. The conditional branching logic circuit 12 uses a signal through selection signal lines 31, 32, 33, 34 to select one register among 4 registers 13 and to output a branch destination address stored in the selected register 13 and to output a branch destination address stored in the selected register 13 to a control signal line 15 together with other control signals. If the level of an input signal is a level or below bringing an output of even a comparator 20 to a high level, the level of the signal through the selection signal lines 31-34 goes all to a low level, any of the 4 registers 13 is not selected and no conditional branching executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a conditional branching circuit that is provided in a semiconductor integrated circuit and controls conditional branching in response to a signal input through one input terminal. .

[Conventional technology]

Figure 5 fal and fbl are block diagrams showing examples of conventional conditional branch circuits in this building, respectively.
1) is an input terminal, 12) is a D flip-flop, (3
) is a conditional branch logic circuit, 14) is a timing input signal line, and (5) is an inverter.

Next, the operation will be explained. In the case of the circuit shown in FIG. 5fal, the input signal from the input terminal (1) is set to the D flip-flop (2) at the time of the timing signal input via the timing input signal line (4), and the conditional branch logic It is transmitted to the circuit (3). That is, the input signal is sent to the conditional branch logic circuit w! by the D flip/70 knob. 131 and is converted into an appropriate timing and an appropriate voltage level.

In the case of the circuit shown in Fig. 5 fbl, a two-stage inverter (
5), the input signal is converted to an appropriate voltage level and input to the conditional branch logic circuit M131.

The conditional branch logic circuit (3) determines whether the input voltage level is high potential (High level) or low potential (Low level), and controls conditional branching.

[Problem that the invention seeks to solve]

Since the conventional conditional branch circuit is configured as described above, the level for determining whether the high level of the potential of the input signal is the low level is a value specific to the element determined by the D flip-flop (2) and the inverter (5). becomes. Therefore, if the level of the signal input to the input terminal (1) does not match the judgment level of the D-flip Flora 7"+2) or the inverter]5), convert the voltage of the signal completely before inputting it. It becomes necessary to match the above judgment level.

In addition, in the conventional configuration, the conditional branch
When control is possible only by selecting one of high level and low level, and multiple choice control based on the potential level of the input signal is impossible, and when attempting to realize multiple choice control, A complete complex circuit must be added before the input terminal (1).

This invention was made in view of the above-mentioned problems, and it is possible to change the judgment level of High level and Low level at the time of conditional branching, and it is also possible to make conditional branching with a binary choice of 1 High level or LOW level. Not, but
It is an object of the present invention to provide a conditional branching circuit capable of performing a plurality of conditional branches depending on the potential of an input signal.

[Means for solving problems]

The conditional branch circuit according to the present invention includes a register that stores in advance addresses of main storage devices (memories including ROM and RAM) of a plurality of branch destinations, and a plurality of registers that store addresses in response to input signals. A potential range corresponding to each branch destination is set, a means for determining which potential range the input signal belongs to, and a branch control by instructing the branch destination corresponding to the input signal based on the above determination result. It is equipped with a conditional branch logic circuit.

[Effect]

In the conditional branching circuit according to the present invention, one of the plurality of signal lines is selected in accordance with the potential of the input signal, and conditional branching to a plurality of branching destinations is performed according to the selected signal line.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an embodiment of the present invention,
In the figure, (1) is the input terminal, (6) is the input terminal (1)
A sample-and-hold circuit that captures the input signal from the input signal at a certain timing and holds the input signal for a certain period of time. The logic circuit that performs the operation, (12) is a conditional branch logic circuit, (13) is a plurality of registers (four in the example shown in this figure), and (14) is a condition for the address stored in register (13). (15) is a plurality of control signal lines for signals that control other circuits for the conditional branch logic (16) is an output signal line of the sample-and-hold circuit , (17), (18), (19),
(20) is a potential comparator (hereinafter referred to as a comparator),
(21) is the power supply voltage, (22) is the ground potential, (23)
, (24), (25), (26) are comparators (17), (
18) , (19) , (20) +7) Reference potential signal line, (27) , (28) , (29) ,
(30) is the comparator (17), (Is),
(19), (20) output signal line, (31),
(32), (33).

(34) is a selection signal line for register (13).

Next, the operation will be explained.

First, the address of each branch destination memory is stored in the register (13). When in the operating state, the sample-and-hold circuit (6) constantly monitors the input potential at a certain period, and connects the input potential to the signal line (
16) and a comparator (17).

Input in parallel to (18), (19), and (20). On the other hand, comparators (17), (1B), (
19) and (20), the power supply voltage (2
1) t-resistance 171, 181, +91, (
The values obtained by dividing the resistance in step 10) are each input. For example, resistance +71, +8).

If +91 and (10) are all of the same resistance value, the signal line (23) has a source of pressure, the signal line (24) has a fang of the source, and the signal line (25) has a % of the power supply voltage is applied to the signal line (26) as a reference potential.

Comparators (17), (18), (19)
, (2(1) compares the human potential and the reference potential, and if the human potential is higher, the output signal line (27)
# (28), (29) # (30) High
Since it outputs a level signal, the output signal lines (27) IC28) and (29) of the comparators (17), (1B), (19), and (20).

At (30), a signal of either High level or Low level is output, corresponding to the potential of the input signal. However, it is impossible for the output of the comparator (19) to be High level and the output of the comparator (20) to be Low level, and the output signal lines (27), (28)
), (29), and C(0) are limited to the cases shown in the left input column of the truth table in FIG.

Next, comparators (17), (18), (1
9) The output signals of (20) are converted by the logic circuit (11) into signals as shown in the truth table in Figure 2, and the register (13) in which the branch destination address is stored is selected. The signal is input manually to the conditional branch logic circuit (I2).

The conditional branch logic circuit (12) includes a selection signal line (31),
(32).

The signals (33) and (34) select one register from the four registers (13), and control the branch destination address stored in the selected register (13) along with other control signals. Output to signal line (15).

If the input signal also makes the output of the comparator (20) Hi
If the potential is below the gh level, select signal line (
31), (32), (33), and (34) all go to LOW level, and the four registers (13
) are not selected, and no conditional branching is performed.

The above embodiment sets a CD range corresponding to each of a plurality of branch destinations for an input signal, and uses a divided voltage obtained by dividing the power supply voltage by a resistor as a means for fully determining which spiral range the input signal belongs to. Although the configuration is based on a comparator used as a reference potential, analog-digital fm
It may also be configured using a converter (hereinafter referred to as an A-D converter).

FIG. 3 is a block diagram showing another embodiment of the present invention, in which fil, +61, (12), (1
3), (14), (15).

(16), (31), (32), (33)
, (34) indicates all parts that are the same as or correspond to the same reference numerals in FIG. 1, and (35) indicates A-1) converter, (36)
) is the digital output signal line from the A-D converter (35), and (37) is the input of digital values (four digital values in this example) for setting the entire potential range corresponding to each of the plurality of branch destinations. register, (38)
is the output signal line from register (37), and (39) is the fourth
This is a logic circuit that operates according to the truth table shown in the figure.

In advance, four digital values for setting the entire potential range corresponding to each branch destination are input into the register (37).

When the input signal enters the operating state, the input signal is connected to the signal line (1) for a certain period of time.
6) and input to the A-D converter (35). The input signal is converted into a digital signal by the AD converter (35) and output to the digital output signal line (36). In the logic circuit (39), the digital comparison between the output signal of the digital output signal line (36) and the output signal of the output signal line (38) from the register (37)
This is done according to the truth table in the figure, and the signals for selecting one of the registers (13) into which the branch destination address is input are the selection signal lines (31), (32), (33),
(34) can be output. The subsequent operations are the same as those shown in FIG.

Note that the resolution of the AD converter (35) needs to be log2 (n-1) bits or more, where n is the number of conditional branches.

Although the above embodiment shows the case where there are four branch destinations, it is of course not limited to the case where there are four branch destinations.

〔Effect of the invention〕

As described above, according to the present invention, the judgment level of the human input signal can be changed arbitrarily, so there is no possibility that the level of the input signal does not match the judgment level, and
A plurality of conditional branches can be performed using a signal manually input from one input terminal, and the effect is that complex control of a controlled device can be performed easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanation showing a truth table of a logic circuit that operates the selection signal of a register that stores all branch destination addresses in the embodiment of FIG. 1. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing a block diagram of another embodiment of the present invention. FIG. Explanatory diagram showing the truth table, Figure 5 fal, f
b) is a block diagram showing an example of a conventional conditional branching circuit of this value. In the figure, (1) is an input terminal, (61 is a sample and hold circuit, +71, +81, 191, (
10) is a resistor, (11) is a logic circuit, (12) is a conditional branch logic circuit, (13) is a register, (17), (1
8), (19), (2(1) is a comparator,
(35) is A-D converter, (37) is resist%
(39) is a logic circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a conditional branching circuit that is provided on a semiconductor integrated circuit and controls conditional branching in response to a signal input through one input terminal, there is a register that stores memory addresses of multiple branch destinations in advance, and an input terminal. means for determining which potential range the input signal belongs to by setting a potential range corresponding to each of a plurality of branch destinations whose addresses are stored in the register for a signal inputted through the register, and based on the above determination result. A conditional branching circuit comprising a conditional branching logic circuit that selects a register corresponding to the potential of an input signal and controls branching by instructing a branching destination according to the contents of this register.