JPS58177033A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To improve the yield at manufacture, by constituting a frequency dividing circuit with simple constitution, decreasing the number of elements, current and power consumption, and reducing the size in circuit-integrating the frequency dividing circuit of multi-stage connection. CONSTITUTION:The 1st differential switch comprising transistors (TRs) Q1, Q2 in which the conducting and interrupting state is switched with an input clock pulse, the 2nd differential switch comprising TRQ3-Q6 operated with the state of the 1st switch, and a latch circuit are provided. Further, the 3rd and the 4th differential switches comprising TRs Q7-Q10 the conducting and interrupting state of which is switched with the conducting and interrupting state of the TRQ3-Q6 and the input clock pulse are provided. The output of the 3rd and the 4th differential switches is fed back to the 2nd differential switch via diodes D1, D2. The constitution of the circuit is simplified, and the number of elements, the current and current consumption are reduced.

Description

[Detailed description of the invention] The present invention relates to a high-speed frequency divider circuit.

FIG. 1 shows the configuration of a conventional frequency divider circuit. In the same figure,
Transistor Q11-o, 9 and resistor R11-R1
, block A and transistors Q) 1 to Q,
19 and resistors h~% have the same circuit configuration, and those indicated by the same numbers correspond to each other. 101 and 102 are clock pulse input terminals,
103 is a reference voltage terminal, 104 and 106 are output terminals, 1
06 is a power supply terminal, and 107 is a GND terminal.

First, the operation of block A will be explained. Transistor Q1
1. Q12 and Q13. Q14 constitutes an emitter-coupled differential switch, and transistors Q16.
Q16 is provided with positive feedback by an emitter follower composed of a transistor, 91□, Q18, and resistors R13+R14, forming a launch circuit.

The transistor Q19 and the resistor R16 form a constant current circuit using the reference voltage applied to the terminal 103.
A constant current of 0 flows through the transistor Q19.

The differential type input clock pulses applied to the input terminals 101 and 102 switch the differential switches Q11 and Q12, so that the constant current switch 0 switches to the differential switch Q1.
3. Q14 or latch circuit Q16. The constant current Io flows from either one of Q16, and the one where this constant current Io flows is in the operating state, and the other is in the cutoff state. Block B has the same number as block A and has the same operation, but differential switch Q11. Since Q12 and Qll and Q'12 of Q)1°Q)2 and Q12 and Q'11 operate in the same manner, the differential switch Q13. Q14 and Q'+31Q',
.

and latch circuit Q16. Q16 and Q'1. , Q'16
The operating states of block A and block B are inverted in phase with respect to the input clock pulse.

FIG. 2 shows voltage waveforms at each node shown in FIG. 1, where a and b are differential input clock pulses applied to terminals 101 and 102, respectively. During the period tl, Q12 and Q-1 are in a conductive state, and the latch circuit Q
16. Q16 is the differential switch Q'l in block B.
31Q'14 becomes operational. At this time, launch circuit Q16 of block A. C changes the state of outputs c and d of Q16 to 'H'
When the output of the differential switch of block B is set to "high" level and d is set to "low" level, e is set to "high" level and f is set to "low" level. These e and f signals become input signals to the differential switches Q13 to Q14 of block A, but during the period tl, the differential switches Q13 to Q14. Since Q14 is in the cutoff state, it does not operate.

From this state, the input clock pulses a and b are reversed and +2
Moving on to the period, in block A, the differential switch Q13.
Q14 is the launch circuit Q'+61"+6 in block B.
becomes operational. At this time, in block B, the latch circuit holds the state of the differential switches Q'+3 +Q'+4, so the outputs e and f do not change. On the other hand, in block A, differential switch Q13. Q14 becomes operational, output e,
The base input of Q, 3 to which f is applied is 'Low' and the base human power U of Reheno 1Q14 is 'Hiqh' level, so the output C is 'Low' level and d is 'High' level, from the state of period t1. It would have been reversed.

Next, when moving to period +3, in block A, latch circuit Q1. ．． Q16 is the differential switch Q'+ in block B.
3IQ'+4 becomes operational, and in block A, differential switch Q13. The state of Q14 is latched by the circuit Q16.
゜Since Q16 is held, the outputs c and did do not change. On the other hand, in block B, differential switch q3. Qj4 is in the operating state, and the base input of Q10 is at the °'Low' level.

Since the base input of Q', 4 is at "High" level, the output e is at "Low" level, and f (/i"High"
level, which means a reversal from the +2 period state.

By repeating such an operation, the voltage waveform at each node becomes as shown in FIG. 2, and the output terminals 104, 104,
The voltage waveforms e and f of 106 are two duplex waveforms.

As described above, in the past, two blocks each having a differential switch and a launch circuit were provided, and division was performed by switching currents using clock pulses so that the operating states were different. In such a circuit, the circuit configuration is complicated and two current sources are required, so when integrating a multi-stage frequency divider circuit, the chip size becomes large and the current consumption and power consumption increase. .

The present invention has been made in view of these problems, and it is an object of the present invention to provide a frequency divider circuit with a simple circuit configuration, a small number of elements, and a low current consumption.

Rather than providing two circuits of blocks each having a differential switch and a launch circuit as in the past, the present invention provides a differential switch, a latch circuit, and a cascode with a differential switch that can be switched between conducting and blocking states by an input clock pulse. By providing this, it is possible to realize a frequency dividing circuit that performs the same frequency dividing operation as the conventional one with a simple circuit configuration.

FIG. 3 shows an embodiment of the present invention. In the same figure, Ql-
01°, 021~Q2. are transistors, R1-R9 are resistors, D1-D6 are tie-outs, and 301-3o6 are terminals. Emitter boat transistor pair Q connected to each other
1 and Q2. Q3 and Q4. Q7 and Q8 and Q9 and Ql.

constitute a differential switch, and among these differential switches, Ql and Q2. Q7 and Q8 and Q9 and Ql
o is driven by an input clock pulse applied to input terminals 301 and 302.

Transistor Q23. Q24. Diodes D3-D6
The resistors R7 and R8 constitute an emitter follower, and the diode D-D is for level shifting so that the transistor Q1-1 does not become saturated. transistor Q6
．． Q6 are mutually given positive feedback and form a launch circuit. Transistor Q21. Q22. Diode D1. D2 and resistors R5 and R6 constitute an emitter follower, and diodes D1. D2 is transistor Q
3. This is for level shifting to prevent Q4 from becoming saturated. 30
3 is the reference voltage terminal, 304.305 is the output terminal, 306
307 is a power supply voltage terminal, and 307 is a GND terminal. Transistor Q26 and resistor R9 form a constant current circuit using a reference voltage applied to terminal 303, and transistor Q26 has a constant current circuit.

flows. Differential switch Q1. Q2 is connected to transistors Q23 . Q24. The diodes D3 to D6 are driven via emitter followers composed of Oyohi resistors R7 and R8, and when Ql is conductive and Q2 is cut off, the constant current 1o is driven by the differential switch Q3. Q4 flows into this differential switch Q3. Q4 becomes operational, and launch circuit Q6. Q6 is in a cut-off state. In addition, when Q2 is conductive and Ql is cut off, the latch circuit Q5. A constant current Io flows from Q6, and this latch circuit Q6. Q6 becomes operational, and the differential switch Q3. Q4 is in a cut-off state. With such a circuit configuration, it is possible to have the same function as a conventional frequency divider circuit.

The operation in response to input clock pulses will be explained using the voltage waveforms at each node shown in FIG. Each node is shown in FIG. a and b are differential input clock pulses, and during period t1, Q2 is conductive and Ql is disconnected.

Therefore, latch circuit Q6. Q6 becomes operational,
Differential switch Q3. Q4 is in a cut-off state. At this time, latch circuit Q5. When Q6 is turned on and Q6 is cut off, constant current Io flows through resistor R1 and transistor Q6 to transistor Q2, d becomes "Low" level due to the voltage drop across resistor R1, and node C is connected to resistor R2. Since there is no voltage drop, the level becomes "High". Differential switch Q7. Q8 and Q9. Qlo is driven by the input clock pulse and Q8. Since the base of Q9 is at the "High" level and the base of +07+010 is at the "Low" level, QB1)5 becomes conductive, and the constant current Io flows through the resistor R4 and the transistor Q8 to the transistor Q6. Therefore, the base voltage of the transistor Q21 goes to the "Low" level due to the voltage drop across the resistor R4, and the base voltage of the transistor Q21 becomes "Low" level.
The base voltage of 2 is “H” because there is no voltage drop across resistor R3.
level.

Therefore, the voltage at node e is the voltage at transistor Q22. Since the base voltage of the transistor Q22 is outputted via the emitter follower composed of the diode D2 and the resistor R6, the voltage at the node f becomes "High" level, and the voltage at the node f is outputted from the transistor Q21. The base voltage of the transistor Q21 is outputted via the emitter follower composed of the diode D1 and the resistor R6, so that it becomes a "Low" level. This voltage is applied to the diode D1. D2 via differential switch Q3.
It is applied to the base of Q4, but at this time differential switch Q3
．． Since Q4 is in the cutoff state, it does not operate. From this state, when the input clock pulses a and b are inverted and the period moves to t2, the differential switch Q1. Q2 switches, Ql becomes conductive, Q2 becomes cut off, and the differential switch Q3. Q4 is activated and the latch circuit Q6. Q6 is in a cut-off state. Here, since the base voltage of the transistor Q3 was at the "Low" level and the base voltage of the transistor was at the "High" level, Q3 was cut off, Q4 was turned on, and the constant current Io passed through the resistor R2 and the transistor Q4. The current flows through transistor Q1.

Therefore, node C becomes "Low" due to the voltage drop of resistor R2.
Since there is no voltage drop across the resistor R1, the node d becomes a "High" level and is inverted from the period tl, but the differential switches Q7, Q8 and Q9, Ql.

The base voltage of is also switched by the input clock pulses a and b, transistor Q1o becomes conductive, and constant current Io is generated by resistor R4 and transistor Q. and flows to transistor Q4. Therefore, the base voltage of the transistor Q21 is "Low" level, and the base voltage of the transistor Q12 is "Low" level.
The base voltage of is “High” level and the node e”
High" level 1. Node f is at Low" level and maintains the state during the period tl. This Ql is blocked,
Q2 becomes conductive, and the latch circuit Q6. Q6 is in operation, differential switch Q3. Q4 is in a cut-off state. Latch circuit Q5. Q6 is a differential switch Q3. Since the state of Q4 is maintained, Q5 is conductive and Q6 is cut off, and constant current generator 0 passes through resistor R2 and transistor Q6 to transistor Q2.
, and node C becomes “Low” due to the voltage drop across resistor R2.
Since there is no voltage drop across the resistor R1, the node d becomes the "High" level and maintains the state during the period t2.The base voltages of the differential switches Q7, Q8 and Q9.Qlo are based on the input clocks a, b Switched by
Transistor Q9 becomes conductive, and constant current generator 0 becomes resistor R3,
The voltage flows through the transistor Q9 to the transistor Q5, and the base voltage of the transistor Q12 is at the "Low" level due to the voltage drop across the resistor R3, and the base voltage of the transistor Q21 is at the "High" level since there is no voltage drop across the resistor R4. e (d becomes ``Low'' level, and node f becomes ``High'' level, which is reversed from the state during period t2.

By repeating such an operation, the voltage waveform of each node becomes as shown in FIG. The waveform becomes a bipartite waveform. The voltage waveform of each node shown in Fig. 2 is also the operating waveform of the frequency divider circuit in the conventional example shown in Fig. 1, and the present invention shown in Fig. 3 has the same function as the conventional example. .

When the frequency divider circuit shown in FIG. 3 is connected in multiple stages, the output signal of the output terminals 304 and 306 may be set as the input clock pulse of the next stage. Therefore transistor Q2
1. Q2□, diode D1. D2 and resistor R6,
Emitter follower composed of R6 and transistor Q
23. Q24. diodes D3 to D6 and resistor R7,
The emitter follower composed of R8 can be shared, and the current consumption per stage is the current IO of the constant current circuit and the current of the two emitter follower circuits. Φ′ and emitter follower 4
It is half the current of the circuit.

As explained above, according to the present invention, a branch circuit with a small number of elements, low current consumption, and low power consumption can be realized with a simple circuit, and when connected in multiple stages, the current consumption is halved. or,
When a multi-stage connected frequency divider circuit as in the present invention is integrated into an integrated circuit, the chip size becomes smaller and the cost is reduced by two steps. Furthermore, since power consumption is reduced, the package can be made smaller.

[Brief explanation of drawings]

Figure 1 is a conventional frequency dividing circuit diagram, Figure 2 is an explanation diagram of operation, and Figure 3 is a diagram of a conventional frequency dividing circuit.
The figure is a diagram of a frequency dividing circuit according to the present invention. Q1-Q1o, Q21-Q26...Transistor, R1-R9...Resistor, D1-p9.e...Diode, 3o1゜302...eO input terminal, 3Q4.
305...Fist output terminal, 306...Power terminal, 307...GND terminal.

Claims (2)

[Claims] (1) A first differential switch whose conduction and cutoff states are switched by an input clock pulse, and a second behavior switch and latch circuit in which one of the first differential switches is in a dynamic operating state depending on the state of the first differential switch. ,
a third differential switch and a fourth differential switch whose conduction and cutoff states are switched depending on the conduction and cutoff states of the second differential switch and the launch circuit and the input pulse; and the third differential switch. and means for feeding back the output of the fourth differential switch to the input of the second differential switch. (2) The first differential switch is the first differential switch. The second differential switch is composed of a third transistor, a fourth transistor, and a launch circuit is composed of a fifth transistor. The 3rd and 4th differential switches are respectively composed of the 7th and 6th transistors. The eighth transistor and the ninth transistor. the collector of the first transistor is the third transistor. the collector of the second transistor is connected to the common emitter of the fourth transistor; a sixth common emitter, the base of the sixth transistor is connected to the collector of the third transistor, the base of the sixth transistor is connected to the collector of the fourth transistor, and the base of the sixth transistor is connected to the collector of the fourth transistor; The collectors of the sixth transistors are respectively connected to the sixth transistors. the base of the sixth transistor, and the collector of the third transistor is connected to the base of the seventh transistor. The common emitter of the eighth transistor and the collector of the fourth transistor are connected to the common emitter of the ninth transistor. the seventh common emitter; 8th
The bases of the transistors 10, . connected to the base of the ninth transistor; The collectors of the eighth transistors are respectively connected to the ninth transistors. the fourth . The frequency divider circuit according to claim 1, wherein the frequency divider circuit is connected to the base of the third transistor.