JPH01184904A - Ceramic substrate for electronic component - Google Patents

Ceramic substrate for electronic component

Info

Publication number
JPH01184904A
JPH01184904A JP63009802A JP980288A JPH01184904A JP H01184904 A JPH01184904 A JP H01184904A JP 63009802 A JP63009802 A JP 63009802A JP 980288 A JP980288 A JP 980288A JP H01184904 A JPH01184904 A JP H01184904A
Authority
JP
Japan
Prior art keywords
substrate
ceramic substrate
dividing
shape
warpage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63009802A
Other languages
Japanese (ja)
Other versions
JPH0748408B2 (en
Inventor
Noribumi Yoshida
則文 吉田
Kazuyuki Mawaki
間脇 和幸
Hideki Matsuura
秀樹 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63009802A priority Critical patent/JPH0748408B2/en
Publication of JPH01184904A publication Critical patent/JPH01184904A/en
Publication of JPH0748408B2 publication Critical patent/JPH0748408B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To reduce the irregularity in thickness of printed films as well as to contrive improvement in dividability by a method wherein the shape of warpage of the substrate in transverse and longitudinal directions is formed into a projecting shape. CONSTITUTION:Grooves 2 and 3, to be used for dividing a substrate, are provided on the surface of a ceramic substrate 1, and the shape of the warpage of the ceramic substrate 1 is formed into a conical shape against its surface. It is desirable that the measurement of the A shown in the diagram is 30mum, the B and C is 15mum, the D is 40mum, and the E and F is 20mum, for example. When the title substrate is constituted as above-mentioned, the warpage of the substrate is turned flat when working and sintering processes are conducted, and also when a glass paste printing process and the lateral direction dividing groove forming process are conducted. Also, as the irregularity in the thickness of the printed film can be reduced, the yield of resistance value can be improved, and the irregularity in total thickness of finished articles can also be decreased.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電子機器に使用されるチップ部品等に用いられ
る電子部品用セラミック基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a ceramic substrate for electronic components used in chip components and the like used in electronic equipment.

従来の技術 一般に、チップ抵抗器は、第5図に示すように、セラミ
ック基板11上にスクリーン印刷等により抵抗体ペース
トを塗布し焼成することにより抵抗体12を設け、そし
てその抵抗体12と接続されかつセラミック基板11の
端面から底面に亘って形成されるように電極13を設け
、さらに抵抗体12を保護するようにガラス膜14を設
けることにより構成されている。
BACKGROUND OF THE INVENTION Generally, as shown in FIG. 5, a chip resistor is manufactured by coating a resistor paste on a ceramic substrate 11 by screen printing or the like and baking it to provide a resistor 12, and then connecting the resistor 12. In addition, an electrode 13 is provided to extend from the end surface to the bottom surface of the ceramic substrate 11, and a glass film 14 is further provided to protect the resistor 12.

従来、この種のチップ抵抗器等に用いられる電子部品用
セラミック基板は第6図〜第8図に示すような形状であ
った。第6図〜第8図はチップ部品を作るだめのセラミ
ック基板の概略図を示しており、16は分割前のセラミ
ック基板、16は縦方向の分割用溝、17は横方向の分
割用溝であり、この分割用溝16,1了を有した面を表
面とした場合、横方向の基板の反りは側面から見ると、
表面に対し谷形形状であり、また縦方向の基板の反りも
側面から見ると、表面に対し谷形形状である。
Conventionally, ceramic substrates for electronic components used in this type of chip resistor and the like have had shapes as shown in FIGS. 6 to 8. Figures 6 to 8 show schematic diagrams of ceramic substrates for making chip parts, where 16 is the ceramic substrate before division, 16 is a vertical division groove, and 17 is a horizontal division groove. If the surface with the dividing grooves 16 and 1 is the front surface, the horizontal warpage of the board is as follows when viewed from the side.
It has a valley shape with respect to the surface, and the warpage of the substrate in the vertical direction also has a valley shape with respect to the surface when viewed from the side.

このような従来のセラミック基板では、基板の反りが谷
形形状であることと、工程加工焼成毎に、第13図のよ
うにセラミック基板の谷形形状が進行することから次の
ような欠点があった。
Such conventional ceramic substrates have the following drawbacks because the warpage of the substrate is in the shape of a valley, and the valley shape of the ceramic substrate progresses as shown in Fig. 13 with each step of processing and firing. there were.

第9図は一般的なチップ抵抗器の製造工程において、ス
クリーン印刷した時のペースト状態を示している。第1
3図に示すように、第1焼成後、セラミック基板15の
谷形形状は極端に進行するため、抵抗体、ガラス部を第
9図のようにスクリ−ン印刷で形成した時、ペースト1
8の膜厚は場所毎にバラツキを生じ、抵抗値歩留りの悪
化及び製品総厚のバラツキが生じる欠点があった。
FIG. 9 shows the paste state when screen printing is performed in a typical chip resistor manufacturing process. 1st
As shown in FIG. 3, after the first firing, the valley shape of the ceramic substrate 15 is extremely advanced, so when the resistor and the glass portion are formed by screen printing as shown in FIG.
The film thickness of No. 8 varied from place to place, resulting in deterioration of resistance value yield and variation in total product thickness.

又、第10図は第3焼成後のセラミック基板を横方向の
分割用溝17に沿って分割する工程を正面から見たもの
であり、19はセラミック基板15の分割ポイン)20
.21は分割用治具である。
Further, FIG. 10 is a front view of the step of dividing the ceramic substrate after the third firing along the horizontal dividing grooves 17, and 19 is the dividing point of the ceramic substrate 15) 20
.. 21 is a dividing jig.

このような分割ポイント19では分割をするための抗折
力が分割ポイント19に集中してしまい、分割後第11
図に示すような異形部分22を生じやすく、分割寸法バ
ラツキが大きくなり、チップ部品の実装マウント時にお
けるトラブルが生じゃすい欠点がある。又、分割を行う
瞬間セラミック基板15が多少たわみ、縦方向の分割用
溝16にストレスが加わるため、横方向の分割用溝17
に沿って分割されると同時に、縦方向の分割用溝16も
分割されてしまい、第12図に孝子ような分割不良が発
生してしまう欠点があった。
In such a dividing point 19, the transverse rupture force for dividing is concentrated at the dividing point 19, and after dividing, the 11th
This method has disadvantages in that irregularly shaped portions 22 as shown in the figure are likely to occur, variations in the division dimensions become large, and troubles are likely to occur when mounting chip components. In addition, the ceramic substrate 15 is slightly bent at the moment of dividing, and stress is applied to the vertical dividing grooves 16, so that the horizontal dividing grooves 17
12, the vertical dividing groove 16 is also divided, resulting in defective division as shown in FIG. 12.

発明が解決しようとする課題 このような従来のセラミック基板で印刷膜厚バラツキを
減少させるためには、分割用溝の深さを浅くし、セラミ
ック基板の反りを小さくしなければならないが、分割性
に悪影響を及ぼす問題点を有しており、又逆に分割性を
良くするためには、分割用溝の深さを深くしなければな
らないが、セラミック基板の反りが大きくなり、印刷膜
厚バラツキに悪影響を及ぼす問題点を有している。
Problems to be Solved by the Invention In order to reduce the variation in printed film thickness on such conventional ceramic substrates, it is necessary to reduce the depth of the dividing grooves and reduce the warpage of the ceramic substrate. On the other hand, in order to improve the dividing property, the depth of the dividing groove must be increased, but this increases the warpage of the ceramic substrate and causes unevenness in printed film thickness. It has problems that have a negative impact on

本発明は上述したようなセラミック基板の印刷膜厚バラ
ツキの安定化、及び分割性の問題点を解決することを目
的とする。
An object of the present invention is to stabilize the variation in printed film thickness of a ceramic substrate and to solve the problem of divisibility as described above.

課題を解決するための手段 以上のような問題点を解決するために本発明は、セラミ
ック基板の分割用溝を設けた表面が山形形状となる反り
を持たせたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is such that the surface of the ceramic substrate on which the dividing grooves are provided is warped into a chevron shape.

作用 この構成によれば、工程加工焼成を行うことにより抵抗
、ガラヌペースト印刷時、及び横方向の分割溝を分割す
る工程において、基板の反りが7ラソトになり印刷膜厚
バラツキが減少するため、抵抗値歩留りの向上及び製品
総厚のバラツキ低減が図れ、又横方向の分割溝を分割す
る工程において分割のポイントが線になり、分割をする
ための抗折力の分散が行なえ異形が生じなくなると共に
、分割時の基板のたわみもなくなり、縦方向の分割溝に
加わるストレスが小さくなり、分割不良の低減が図れる
Effect: According to this configuration, by performing process processing and baking, the warpage of the substrate is reduced to 7 rasot during printing of the resistor, Galanu paste, and the process of dividing the horizontal dividing grooves, reducing the variation in printed film thickness. In addition, in the process of dividing the horizontal dividing groove, the dividing point becomes a line, the transverse rupture force for dividing is distributed, and irregular shapes do not occur. , there is no bending of the substrate during division, the stress applied to the vertical division grooves is reduced, and division defects can be reduced.

実施例 以下、本発明について、チップ抵抗器用セラミック基板
の実施例を用いて図面を参照しながら説明する。
EXAMPLE Hereinafter, the present invention will be explained using an example of a ceramic substrate for a chip resistor with reference to the drawings.

第1図に本発明の一実施例におけるセラミック基板を示
し、第2図に横方向から見たセラミック基板の反り形状
を示し、第3図に縦方向から見たセラミック基板の反り
形状を示している。すなわち、本発明は第2図、第3図
に示すようにセラミック基板1の表面に分割用溝2.3
を設け、そしてその表面に対しセラミック基板1の反り
形状を山形形状にしたものである。その寸法は、例えば
第2図の人は3oμm、B、Cは15/jmで、第3図
のDは40μm、E、Fは20μmにした。
Fig. 1 shows a ceramic substrate according to an embodiment of the present invention, Fig. 2 shows a warped shape of the ceramic substrate viewed from the horizontal direction, and Fig. 3 shows a warped shape of the ceramic substrate seen from the vertical direction. There is. That is, the present invention provides dividing grooves 2.3 on the surface of the ceramic substrate 1 as shown in FIGS. 2 and 3.
The ceramic substrate 1 is curved in a chevron shape with respect to its surface. For example, the dimensions of the person in FIG. 2 are 30 μm, B and C are 15/jm, D in FIG. 3 is 40 μm, and E and F are 20 μm.

尚、セラミック基板横方向の基板の反り形状は第7図に
対応し、縦方向の基板の反り形状は第8図に対応する。
The warped shape of the ceramic substrate in the horizontal direction corresponds to FIG. 7, and the warped shape of the ceramic substrate in the vertical direction corresponds to FIG. 8.

以下、本発明のセラミック基板を利用した場合の具体的
な効果を述べる。
Hereinafter, specific effects when using the ceramic substrate of the present invention will be described.

本発明のセラミック基板を1,000枚作成し、チップ
抵抗器製造ラインに投入し工程加工焼成毎の基板反り形
状の確認、抵抗値バラツキの確認、ガラス膜厚バラツキ
の確認、分割異形発生率の確認、分割不良率の確認を行
った。
1,000 ceramic substrates of the present invention were made and put into a chip resistor production line to check the warped shape of the substrate, check the resistance value variation, check the glass film thickness variation, and check the splitting irregularity occurrence rate. We checked the split defect rate.

第4図に示すように、工程加工焼成による基板反り形状
は、はぼフラットな形状になったため、抵抗値バラツキ
は、従来σ匈4%だったものがσ角1.6%にすること
ができ、又、ガラス膜厚バラツキも従来σ=6.8μm
だったものがσ=3.6μmに小さくすることが出来る
。又、分割異形発生率も、従来3.2%だったものが、
1.3%と半減以下になり、分割不良率においても0.
8%だったものが0.3%と半減することが出来る。
As shown in Figure 4, the warped shape of the substrate due to process processing and firing has become almost flat, so the resistance value variation can be reduced from the conventional σ angle of 4% to σ angle of 1.6%. Also, the glass film thickness variation is conventionally σ = 6.8 μm.
This can be reduced to σ=3.6 μm. In addition, the incidence of splitting dysmorphia was previously 3.2%, but
The split defect rate was reduced by more than half to 1.3%, and the split defect rate was also 0.
What used to be 8% can be halved to 0.3%.

発明の効果 以上のように本発明におけるセラミック基板は、横方向
、縦方向の基板の反り形状を山形形状にすることにより
印刷膜厚バラツキの低減、及び分割性の向上を図ること
が出来る。
Effects of the Invention As described above, in the ceramic substrate of the present invention, by making the curved shape of the substrate in the horizontal and vertical directions into a chevron shape, it is possible to reduce variations in printed film thickness and improve divisibility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による電子部品用セラミック
基板を示す斜視図、第2図は第1図の横方向から見た説
明図、第3図は第1図の縦方向から見た説明図、第4図
は同基板の工程加工焼成に対する反りの状況を示す説明
図、第5図は一般的なチップ抵抗器を示す断面図、第6
図は従来のセラミック基板を示す斜視図、第7図は第6
図の横方向から見た断面図、第8図は第6図の縦方向か
ら見た断面図、第9図は従来のセラミック基板を使用し
た時の印刷膜厚状態を示す説明図、第10図は横方向の
分割溝を分割する工程を示す正面図、第11図、第12
図は第10図により分割した時発生する問題点を示す斜
視図、第13図は従来のセラミック基板の工程加工焼成
に対する反りの状況を示す説明図である。 1・・・・・・セラミック基板、2.3・・・・・・分
割用溝。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名/−
−−セラミック基版 2、3−一一分91用肴 第1図 ! 第2図 第3図 第4図 第5図 第6図 横方向口〉 第7図 /g 第8図 第9図 1月 第10図 π 第13図 一項方崗の基板及す
FIG. 1 is a perspective view showing a ceramic substrate for electronic components according to an embodiment of the present invention, FIG. 2 is an explanatory diagram seen from the horizontal direction of FIG. 1, and FIG. 3 is an explanatory diagram seen from the vertical direction of FIG. 1. An explanatory diagram, Fig. 4 is an explanatory diagram showing the state of warping of the same board due to process processing and firing, Fig. 5 is a cross-sectional view showing a general chip resistor, and Fig. 6
The figure is a perspective view showing a conventional ceramic substrate, and FIG.
8 is a sectional view seen from the horizontal direction of the figure, FIG. 8 is a sectional view seen from the vertical direction of FIG. 6, FIG. 9 is an explanatory diagram showing the printed film thickness state when using a conventional ceramic substrate, The figures are a front view showing the process of dividing the horizontal dividing groove, Figures 11 and 12.
10 is a perspective view showing the problem that occurs when the substrate is divided according to FIG. 10, and FIG. 13 is an explanatory view showing the state of warpage caused by process processing and firing of a conventional ceramic substrate. 1...Ceramic substrate, 2.3...Dividing groove. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Ceramic base plate 2, 3-11 minute 91 appetizer figure 1! Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Lateral opening〉 Fig. 7/g Fig. 8 Fig. 9 January Fig. 10 Fig. π Fig. 13

Claims (1)

【特許請求の範囲】[Claims]  表面に多数個に分割するための分割用溝を有し、かつ
表面が山形形状となる反りを設けたことを特徴とする電
子部品用セラミック基板。
1. A ceramic substrate for electronic components, characterized in that it has dividing grooves on its surface for dividing into a large number of parts, and has a curved surface so as to have a chevron shape.
JP63009802A 1988-01-20 1988-01-20 Ceramic substrate for sheet electronic parts Expired - Fee Related JPH0748408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63009802A JPH0748408B2 (en) 1988-01-20 1988-01-20 Ceramic substrate for sheet electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63009802A JPH0748408B2 (en) 1988-01-20 1988-01-20 Ceramic substrate for sheet electronic parts

Publications (2)

Publication Number Publication Date
JPH01184904A true JPH01184904A (en) 1989-07-24
JPH0748408B2 JPH0748408B2 (en) 1995-05-24

Family

ID=11730320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63009802A Expired - Fee Related JPH0748408B2 (en) 1988-01-20 1988-01-20 Ceramic substrate for sheet electronic parts

Country Status (1)

Country Link
JP (1) JPH0748408B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5056566A (en) * 1973-09-21 1975-05-17
JPS52155357A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Method of making electronic parts

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5056566A (en) * 1973-09-21 1975-05-17
JPS52155357A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Method of making electronic parts

Also Published As

Publication number Publication date
JPH0748408B2 (en) 1995-05-24

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