JPS62287656A - Formation of lead for electronic component - Google Patents
Formation of lead for electronic componentInfo
- Publication number
- JPS62287656A JPS62287656A JP61131616A JP13161686A JPS62287656A JP S62287656 A JPS62287656 A JP S62287656A JP 61131616 A JP61131616 A JP 61131616A JP 13161686 A JP13161686 A JP 13161686A JP S62287656 A JPS62287656 A JP S62287656A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- protecting thin
- semiconductor device
- thin plate
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000000465 moulding Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 238000005452 bending Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔概要〕
成形加工用金型において、電子部品リードの損傷を防止
するために、ダイとリードの間及びパンチとリードの間
に保護薄板を挟み込み、保護薄板と共に成形加工する電
子部品リードの成形方法。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In order to prevent damage to electronic component leads in a mold for forming processing, a protective thin plate is provided between the die and the lead and between the punch and the lead. A method of forming electronic component leads that is sandwiched and formed together with a protective thin plate.
本発明は表面処理を行なった後に行なう、電子部品リー
ドの成形方法に関するものである。The present invention relates to a method for molding electronic component leads after surface treatment.
成形後には表面処理を施せない加工物、例えば半田メッ
キした半導体装置のリードを、表面状態を損なうことな
く折り曲げ加工することが要求されている。It is required to bend workpieces that cannot be surface-treated after molding, such as leads of solder-plated semiconductor devices, without damaging the surface condition.
従来半導体装置のリードの成形は第２図に示すように、
特別の処理や加工をしていない一般に使用されている金
型と同じ金型を使用して行なっている。As shown in Figure 2, conventional semiconductor device leads are formed as follows.
This is done using the same molds that are commonly used, without any special treatment or processing.
図において、半導体装置４はダイ２にセットされており
、リード４ａを折り曲げ加工する場合には先ずクランパ
３が降下してリード４ａを押さえ、更にバンチ１が降下
しり−ド４ａを折り曲げ加工する。In the figure, a semiconductor device 4 is set on a die 2, and when bending a lead 4a, the clamper 3 first descends to hold the lead 4a, and then the bunch 1 descends to bend the lead 4a.
加工が終わると先ずバンチ１がリード４ａから離れ、次
にクランパ３と共に更に上昇して初期状態に復帰する。When the machining is finished, the bunch 1 first separates from the lead 4a, and then rises further together with the clamper 3 to return to its initial state.
〔発明が解決しようとする問題点９
以上説明の従来の半導体装置のリードの成形方法で問題
となるのは、特に損傷を受けやすい半田メッキをしたリ
ードを成形する場合に、■半導体装置のプリント配線板
実装時に、メッキが剥離した部分には半田が付かずに半
田付は不良となる。[Problem to be Solved by the Invention 9] Problems with the conventional method of forming leads for semiconductor devices described above are that when forming solder-plated leads that are particularly susceptible to damage, When mounting on a wiring board, solder does not adhere to the parts where the plating has peeled off, resulting in poor soldering.
■加工部の外観が汚くなるので、製品の信頼性を損なう
。■The appearance of the processed part becomes dirty, which impairs the reliability of the product.
■金型に剥離した半田が付着し、次に加工するリードに
圧痕をつけたり、寸法不良等の障害が発生する。- Peeled solder adheres to the mold, causing problems such as indentation on the next lead to be processed and dimensional defects.
などの問題点である。Problems such as:
上記問題点は、金型と半導体装置のリードの表面の間に
薄板を介在させて、加工を行なう時にダイとリードの間
及びパンチとリードの間に保護薄板を挟み込みリードと
共に折り曲げ加工することにより解決される。The above problem can be solved by interposing a thin plate between the mold and the surface of the lead of the semiconductor device, and during processing, inserting a protective thin plate between the die and the lead and between the punch and the lead and bending it together with the lead. resolved.
即ち本発明においては、金型とリードが直接に接触しな
いように保護薄板を挟み込んだ状態で折り曲げ加工が施
されるので、従来のように金型により表面の半田メッキ
層が損傷を受けることが無くなり外観が良くなるばかり
でなく、表面の半田メッキ層の剥離も防止でき、従って
剥離した半田メ、・７キ層の金型への付着も無くなる。That is, in the present invention, since the bending process is performed with a protective thin plate sandwiched between the mold and the lead so that they do not come into direct contact, the solder plating layer on the surface is not damaged by the mold as in the conventional method. This not only improves the appearance, but also prevents the solder plating layer on the surface from peeling off, thus eliminating the adhesion of peeled solder metal and 7 layers to the mold.
以下第１図について本発明の一実施例を半導体装置の場
合について説明する。An embodiment of the present invention will be described below with reference to FIG. 1 in the case of a semiconductor device.
第１図（ａ）に示すように、半導体装置４はダイ２にセ
ットされ、リード４ａはダイ２に設けた保護薄板５例え
ば０．０５ｆｌの鋼板の上に載せられている。As shown in FIG. 1(a), the semiconductor device 4 is set on the die 2, and the leads 4a are placed on a protective thin plate 5 provided on the die 2, for example, a 0.05 fl steel plate.
クランパ３にも保８３１ｉ板５が取りつけられており、
クランパ３が降下して保Ｗ１薄板５が半導体装置４のリ
ード４ａに当たり、更にパンチ１が降下してリード４ａ
を上下の保８１！薄板５と共に折り曲げ加工し、第１図
［ｂ）に示すような状態で加工を終わる。A retainer 831i plate 5 is also attached to the clamper 3,
The clamper 3 descends and the holding W1 thin plate 5 hits the lead 4a of the semiconductor device 4, and the punch 1 further descends and hits the lead 4a.
The upper and lower parts are 81! The thin plate 5 is bent together with the thin plate 5, and the process is completed in the state shown in FIG. 1 [b].
加工が終わると先ずパンチ１がリード４ａから離れ、保
８Ｗ薄板５のついたクランパ３と共に更に上昇して第１
図（ａｌに示す初期状態に復帰する。When the machining is finished, the punch 1 first separates from the lead 4a and further rises together with the clamper 3 with the 8W thin plate 5 attached to the first
It returns to the initial state shown in Figure (al).
この時点では、保護薄板５はリード４ａと共に折り曲げ
られたので、最初のように完全に真っ直ぐな状態では無
いが、次の半導体装置４のセツティングに対しては支障
なく、数十回繰り返し使用可能である。At this point, the protective thin plate 5 has been bent together with the leads 4a, so it is not in a completely straight state as it was at the beginning, but it can be used repeatedly dozens of times without any problem when setting the next semiconductor device 4. It is.
尚、保護薄板５は上記のように金型に設けるのでなく、
個々の半導体装置４のリード４ａに設けて実施すること
も可能である。Note that the protective thin plate 5 is not provided on the mold as described above, but
It is also possible to implement it by providing it on the leads 4a of individual semiconductor devices 4.
以上説明したように本発明によれば、極めて一般的に使
用されている通常の金型を使用しても、簡単な保護薄板
を使用することにより、リードの損傷を防止して半田メ
ッキ層の剥離を無くすことができるので、剥離した半田
メッキ層が金型へ付かないようにすることが可能となる
。As explained above, according to the present invention, even if a very commonly used ordinary mold is used, damage to the leads can be prevented by using a simple protective thin plate, and the solder plating layer can be prevented from being damaged. Since peeling can be eliminated, it is possible to prevent the peeled solder plating layer from adhering to the mold.
第１図は本発明による一実施例を示す側面図、第２図は
従来技術を示す側面図、
である。
図において、
１はパンチ、
２はダイ、
３はクランパ、
４は半導体装置、
４ａはリード、
５保護薄板、
を示す。FIG. 1 is a side view showing an embodiment of the present invention, and FIG. 2 is a side view showing a conventional technique. In the figure, 1 is a punch, 2 is a die, 3 is a clamper, 4 is a semiconductor device, 4a is a lead, and 5 is a protective thin plate.
Claims (1)
のリード（４ａ）の間及びパンチ（１）と該電子部品（
４）の該リード（４ａ）の間に保護薄板（５）を挟み込
み該保護薄板（５）を介して成形加工することを特徴と
する電子部品リードの成形方法。Using a mold for molding, die (2) and electronic component (4)
between the lead (4a) of the punch (1) and the electronic component (
4) A method for molding an electronic component lead, characterized in that a protective thin plate (5) is sandwiched between the leads (4a) and molding is performed through the protective thin plate (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61131616A JPS62287656A (en) | 1986-06-05 | 1986-06-05 | Formation of lead for electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61131616A JPS62287656A (en) | 1986-06-05 | 1986-06-05 | Formation of lead for electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62287656A true JPS62287656A (en) | 1987-12-14 |
Family
ID=15062227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61131616A Pending JPS62287656A (en) | 1986-06-05 | 1986-06-05 | Formation of lead for electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62287656A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01273341A (en) * | 1988-04-26 | 1989-11-01 | Nec Corp | Lead forming apparatus for ic |
| US5034350A (en) * | 1987-09-23 | 1991-07-23 | Sgs Thomson Microelectronics S.R.L. | Semiconductor device package with dies mounted on both sides of the central pad of a metal frame |
-
1986
- 1986-06-05 JP JP61131616A patent/JPS62287656A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5034350A (en) * | 1987-09-23 | 1991-07-23 | Sgs Thomson Microelectronics S.R.L. | Semiconductor device package with dies mounted on both sides of the central pad of a metal frame |
| JPH01273341A (en) * | 1988-04-26 | 1989-11-01 | Nec Corp | Lead forming apparatus for ic |
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