JPH01181223A - Buffer circuit - Google Patents
Buffer circuitInfo
- Publication number
- JPH01181223A JPH01181223A JP63005754A JP575488A JPH01181223A JP H01181223 A JPH01181223 A JP H01181223A JP 63005754 A JP63005754 A JP 63005754A JP 575488 A JP575488 A JP 575488A JP H01181223 A JPH01181223 A JP H01181223A
- Authority
- JP
- Japan
- Prior art keywords
- level
- potential
- vdd
- terminal
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000007704 transition Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract 3
- HCUOEKSZWPGJIM-IYNMRSRQSA-N (e,2z)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N\O)\C(N)=O HCUOEKSZWPGJIM-IYNMRSRQSA-N 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910016094 MPO2 Inorganic materials 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 101000742346 Crotalus durissus collilineatus Zinc metalloproteinase/disintegrin Proteins 0.000 description 5
- 101000872559 Hediste diversicolor Hemerythrin Proteins 0.000 description 5
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Inorganic materials O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 description 5
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 5
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 3
- 229910015818 MPO4 Inorganic materials 0.000 description 3
- 229910015814 MPO5 Inorganic materials 0.000 description 3
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101100113576 Arabidopsis thaliana CINV2 gene Proteins 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002085 enols Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳトランジスタによる出力バッファ回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit using MOS transistors.
従来、この棟のバッファ回路としては、第５図に示し九
ような回路がある。Ｖｄｄは電源端子、Ｖｓｓは接地端
子、Ｉｌｌは入力端子、０１１は出方端子、Ｎｌｔは接
点、ＭＰＩＩはソースがＶｄｄに、ゲートがＩｌｌに、
ドレインがＮｉｌに接続さ散Ｐ形ＭＯ８トランジスタ、
ＭＮ １１はソース力Ｖｓｓに、ゲートが１１１ｒｌｃ
１ ドレインがＮｉｌに接続されたへ形ＭＯ８トランジ
スタ、ＭＰ１３はソースがＶｄｄに、ゲートがＮｉｌに
、ドレインが端子０１１に接続され２ｐ形ＭＯ８トラン
ジスタ、ＭＮ１３ｔｉソースがＶｓｓに、ゲートがＮｉ
ｌに、ドレインが端子０１１に接続されたＮ形ＭＯ８）
う／ジスタ、Ｃ１ｌはＮｉｌの寄生容量である。Conventionally, as a buffer circuit for this building, there is a circuit as shown in FIG. 5. Vdd is a power supply terminal, Vss is a ground terminal, Ill is an input terminal, 011 is an output terminal, Nlt is a contact, MPII has a source connected to Vdd, a gate connected to Ill,
Distributed P-type MO8 transistor, whose drain is connected to Nil
MN 11 has source power Vss and gate 111rlc
1 Hemform MO8 transistor with drain connected to Nil, MP13 has source connected to Vdd, gate connected to Nil, 2p type MO8 transistor with drain connected to terminal 011, MN13ti source connected to Vss, gate connected to Ni
l, the drain is connected to terminal 011 (N-type MO8)
The resistor C1l is a parasitic capacitance of Nil.
次に動作について述べる。Next, we will discuss the operation.
（１）先ず入力Ｉｌｌがロクレベルの場合にはＭＰＩＩ
は導通状態、ＭＮＩＩは遮断の状態にあるから、Ｃ１ｌ
はＭＰＩＩを介して完全に充電されて、Ｎ１１はハイレ
ベルとなっている。従ってＭＰ１社遮断状態、ＭＮ１３
は導通状態となっており、出力荷電流がシンクされて、
出方は士〒ｒレベルトナって安定な状態となっている。(1) First, if the input Ill is at the rock level, the MPII
is in a conductive state and MNII is in a cutoff state, so C1l
is fully charged via MPII, and N11 is at a high level. Therefore, MP1 company is cut off, MN13
is in a conducting state, and the output load current is sunk,
The situation is stable, with level 1.
（２）次に入力レベルが覧つレベルから反転してハイレ
ベルとなるとＭＰｌｌは遮断状態、ＭＮｌｌは導通状態
となるからＭＮ １１ ｔ−介して７１１の蓄積電荷放
電が起こ、り、Ｎｉｌのレベルは徐々に下がる。(2) Next, when the input level is reversed from the visible level and becomes high level, MPll is in the cutoff state and MNll is in the conductive state, so that the accumulated charge of 711 is discharged through MN11t-, and the level of Nil gradually decreases.
こ仁でＭＰ１３が導通状態となるために必要なソース・
ゲート間電圧１＜Ｖ とすると、？？１Ｂ
ＮｉｌのレベルがＶｄｄに対してＶ だけ？Ｐ１３
低い値となった時点からＭＰ１３は導通状態となるＯ
更にＭＮ１３が導通状態となるために必要なソース・ゲ
ート間電圧を■□、３とすると、ＮｉｌのレベルがＶｓ
ｓに対してＶ だけ高い値をＮ１３
過ぎて降下した時点からＭＮｓｓは遮断状態となる。The source and source necessary for MP13 to become conductive at this time
If the voltage between gates is 1<V, then ? ? 1B Is the Nil level only V compared to Vdd? When P13 becomes a low value, MP13 becomes conductive.O Furthermore, assuming that the source-gate voltage required for MN13 to become conductive is □, 3, the level of Nil becomes Vs.
MNss enters the cut-off state from the time when it drops past a value N13 higher than V by s.
従ってＭＰ１３ｔ−介して負荷は充電され、端子０１１
はハイレベルとなる。Therefore, the load is charged through MP13t-, and the terminal 011
is at a high level.
Ｃ１ｌはＭＮＩＩを介して絶えず蓄積電荷の放ね
電が行なかれて、Ｎｌｌの電位は−Ｖｓａと等しくなり
、全体は安定状態となる。Accumulated charges in C1l are constantly discharged via MNII, and the potential of Nll becomes equal to -Vsa, resulting in a stable state as a whole.
（３）更に入力レベルがハイレベルからロウレベルに反
転するとＭＰＩＩは導通状態、ＭＮｌｌは遮断状態とな
って端子０１１はＭＰｌｌを介して充電されてＮｉｌの
電位が上昇する。ＭＮ ｌ ３１ｊ、 Ｎ １１の電位
が■ を上回った時点で導通状態とな？Ｎ１３
シ、−万、ＭＰ１３ｔ！、ＮＮ１１Ｄ１位、１ｚＶｃｌ
ａ−Ｖア、□、金上回った時点で遮断状態となって、Ｍ
Ｐ１３ｔ−介した負荷への電流供給が停止し、ＭＮ１３
を介しｔ負荷からの電流シ／りによプ、端子０１１のレ
ベルは下がってロウレベルとなる。(3) When the input level is further inverted from high level to low level, MPII becomes conductive and MNll becomes cut off, terminal 011 is charged via MPll and the potential of Nil rises. When the potential of MN l 31j and N 11 exceeds ■, it becomes conductive. N13 shi, -10,000, MP13t! , NN11D 1st place, 1zVcl
a-V A, □, it becomes a cutoff state when it exceeds gold, and M
The current supply to the load via P13t stops, and MN13
The level of terminal 011 decreases to a low level due to the current leakage from the load through the terminal 011.
Ｃ１ｌはＭＰＩＩによる充電が続いて、完全光電状態と
なって、ＶｄｄＫ＃Ｌい電位となる。これによって全体
は（１］の状態に戻ル安定する。C1l continues to be charged by MPII, becomes completely photoelectric, and has a potential of VddK#L. As a result, the entire system returns to state (1) and becomes stable.
以降は入力信号の変化によシ、一連の動作を繰シ返し行
なう。Thereafter, the series of operations is repeated depending on changes in the input signal.
上述し九従米のパフ７７回路は、出力を駆動するトラン
ジスタのゲート電位が、ゲートに寄生す執
る容量の完全放電ないしは、完全ｊ電の状態により、Ｖ
ｄｄ電位ないしｄＶｓｓ電位となって安定状態となって
いるので、入力信号変化時点から出力ｔ−！に動するト
ランジスタが状態遷移に達する迄の時間が大きく、動作
速度の低下ｔ１ｉ九すという欠点が有る。In the above-mentioned Puff 77 circuit, the gate potential of the transistor that drives the output becomes V due to the complete discharge or complete discharge of the capacitance parasitic to the gate.
dd potential or dVss potential and is in a stable state, so from the time the input signal changes, the output t-! The disadvantage is that it takes a long time for a transistor that operates to reach a state transition, resulting in a reduction in operating speed.
本発明のバッファ回路は、出力ＩｇＫｐＪＪ用の落１の
ＮＯ８トランジスタと、該第１のＮＯ８）う／ジスタの
ゲートｔ−駆動する第２のＮＯ８トランジスタと、該′
ｇ２のＮＯ８）う／ジスタのゲートｔ−駆動する論理回
路を有し、該論理回路は、バッファの大力信号と、バッ
ファ出力の帰還信号が加わる構成を有している。The buffer circuit of the present invention includes a drop-in NO8 transistor for the output IgKpJJ, a second NO8 transistor for driving the gate of the first NO8 transistor, and the
g2 NO8) A logic circuit for driving the gate t of the register is provided, and the logic circuit has a configuration in which the large output signal of the buffer and the feedback signal of the buffer output are added.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図をよ本発゛明の一実施例の回路図である。Ｖｄｄ
は電源端子、Ｖｓｓ４ｄ接地端子、工Ｏ１は入力端子、
００１は出力端子、Ｎｏ １． Ｎｏ ２． ＮＯ３，
ＮＯ４，ＮＯ５゜ＮＯ６’ｔｉ各に’Ｉｎ点、ＩＮＶｌ
ｆｌ ＩＯ１’に入力、ＮＯＩ金出刃出力るインバータ
論理回路、ＮＡＮＤＩはＮ）１並びに００１を入力とし
、ＰＪＯ５ｔ−出力とする２人力ＮＡＮＤ論理回路、Ｎ
０ＲＩはＮＯＩ並びに端子００１を入力とし、Ｎ０６ｉ
出力とする２人力ＮＯＲ論理回路、ＭＰＯ１ｔ！ソー、
ｘがｖｄｄＫ、グー）カＮＯ５に、ドレインがＮＯ３に
接続されたＰ形ＭＯ８トランジスタ、ＭＮＯＩはソース
がＷａｓに、ゲートがＩｏｌに、ドレインがＮＯ３に接
続され７ｊＮ形ＭＯ８ト２ンジスｐ、ＭＰＯ２ｅｌ／−
スがＶｄｄＫ、ゲートが工０１に、ドレインがＮＯ４に
接続されｑＰ形ＭＯ８トランジスタ、ＭＮＯ２はソース
がＷａｓに、ゲートがＮＯ６に、ドレインがＮＯ４に接
続され九Ｎ形ＭＯ８トランジスタ、ＭＰＯ３はソースが
Ｖｄｄに、ドレインが端子００１に接続されｔＰ形ＭＯ
８トランジスタ、ＭＮＯ３はソースがＶｓｓに、ＮＯ４
に、ドレインが端子００１に接続され［Ｎ形ＭＯ８）２
ンジスタ、Ｃｏ１ｔ！ＮＯ３とＶｓｓ間の寄生容量、Ｃ
Ｏ２はＮＯ４とＶｓｓ間の寄生容量である。FIG. 2 is a circuit diagram of an embodiment of the present invention based on FIG. 1; Vdd
is the power supply terminal, Vss4d is the ground terminal, O1 is the input terminal,
001 is the output terminal, No. 1. No. 2. NO3,
'In point, INVl for NO4, NO5゜NO6'ti each
fl Inverter logic circuit that inputs to IO1' and outputs NOI, NANDI is NAND logic circuit that uses N)1 and 001 as input, and outputs PJO5t-, N
0RI uses NOI and terminal 001 as input, and N06i
Two-person NOR logic circuit for output, MPO1t! Thor,
P-type MO8 transistor with x connected to vddK, goo) cap NO5, drain connected to NO3, MNOI has source connected to Was, gate connected to Iol, drain connected to NO3, 7j N-type MO8 transistor p, MPO2el/ −
MPO3 has a source connected to Was, a gate to NO6, and a drain to NO4. MPO3 has a source connected to Vdd. , the drain is connected to terminal 001 and the tP type MO
8 transistors, the source of MNO3 is Vss, NO4
, the drain is connected to terminal 001 [N-type MO8)2
Njista, Co1t! Parasitic capacitance between NO3 and Vss, C
O2 is a parasitic capacitance between NO4 and Vss.
次に、本実施例の動作について述べる。Next, the operation of this embodiment will be described.
（１１入力Ｉ０１にロウレベルの信号が印加されている
場合、ＭＮＯＩは遮断状態、ＭＰＯ２は導通状態、ＮＯ
Ｉはハイレベルであシ、Ｎｏａｉは端子００１のレベル
によらずロウレベルを出力するからＮＯ６はロウレベル
であ、！ｌ）、ＭＮＯ２は遮断状態である。(When a low level signal is applied to the 11 input I01, MNOI is in the cutoff state, MPO2 is in the conduction state, and NO
I is at high level, and Noai outputs low level regardless of the level of terminal 001, so NO6 is at low level. l), MNO2 is in a blocked state.
従ってＣＯ２はＭｐ０２ｆ、介して充電され、ＮＯ４の
電位Ｊｄ Ｖｄｄとなってお５、ＭＮＯ３は導通状態と
なる。ここで、ＮＡＮＤＩの出力であるＮＯ５のレベル
は端子００１のレベルによシ定まるが、仮シにＭＰＯＢ
が導通状態であるとするならば、ＭＮ ０３も導通状態
であるから端子００１はＶｄｄとＶｓｓの中間レベルと
なυ、Ｎ０５も又、中間レベルとなって、ＭＰＯＩは僅
かながら、コンダクタンスを持ち、ＶｄｄよｐｃＯｌを
充電して、００１の電位が上昇する。Therefore, CO2 is charged through Mp02f, becomes the potential Jd Vdd of NO4, and MNO3 becomes conductive. Here, the level of NO5, which is the output of NANDI, is determined by the level of terminal 001.
If is in a conductive state, MN03 is also in a conductive state, so the terminal 001 is at an intermediate level between Vdd and Vss, υ, N05 is also at an intermediate level, and MPOI has a small conductance. By charging pcOl to Vdd, the potential of 001 rises.
ＭＰＯＢに導通状態を与えるソース・ゲート間なる。端
子００１のレベルは下がシロウレペルとなる。ＮＯ５の
レベルは上がジノ１イレペルとなってＭＰＯＩは遮断状
態となる。ＣＯＩへの充電電流はなくなシ、ＮＯ３のレ
ベルはＶｄｄ−ＶＴＰＯ３を僅かに超えた点で留ま夛、
Ｖｄｃｌに至ることはない。この状態で各々のレベルは
安定する。即ち八１Ｐｏ３が導通状態を保持することは
あ）えない０
（２）次に入力レベルがハイレベルに遷移すると、ＭＮ
ＯＩは導通状態、ＭＰＯ２は遮断状態となシ、ＮＯＩは
ロウレベルとなる。従って、ＮＡＮＤＩの出力ＮＯ５は
端子００１のレベルによらずハイレベルを保ち、ＭＰＱ
Ｉは遮断状態のままである。It is between the source and gate that gives conduction to MPOB. The lower level of the terminal 001 is the lower level. The level of NO5 becomes 1 level and the MPOI is cut off. There is no charging current to COI, and the NO3 level remains at a point slightly above Vdd-VTPO3.
It never reaches Vdcl. In this state, each level becomes stable. In other words, it is impossible for 81Po3 to maintain a conductive state.0 (2)When the input level transitions to high level next, MN
OI is in a conductive state, MPO2 is in a cut-off state, and NOI is at a low level. Therefore, the NANDI output NO5 maintains a high level regardless of the level of the terminal 001, and the MPQ
I remains blocked.
この時点に２いて端子００１のレベルはロウのままであ
るからＮＯＲ＋１は反転して、ＮＯ６はハイレベルとな
シ、ＭＮＯ２は導通状態となる。ＣＯ２の蓄積電荷はＭ
ＮＯ２を介して放電されて、ＮＯ４のレベルが下がる。At this point in time, the level of terminal 001 remains low, so NOR+1 is inverted, NO6 becomes high level, and MNO2 becomes conductive. The accumulated charge of CO2 is M
It is discharged through NO2 and the level of NO4 decreases.
ＭＮＯ３に導通状態を与えるノースゲート間電位ｔ−■
とすると、ＮＯ４’１’ＮＱ３
のレベルがＶ を下回った時点でＭＮＯ３はＮＱ
３
遮断状態となる。−万、Ｃ０１の蓄積電荷もＭＮＯＩを
介して放電され、Ｎ０３０レベルが下がる。North gate potential t-■ that gives conduction to MNO3
Then, when the level of NO4'1'NQ3 falls below V, MNO3 becomes NQ
3 Becomes a cut-off state. -10,000, the accumulated charge of C01 is also discharged through MNOI, and the N030 level decreases.
ＮＯ３のレベルはＶｄｄ−Ｖ よシ僅かに高い？
ｒ０３
電位であっｔ几め、ｖｄｄ−ｖＴＰｏ３を下回るレベル
に述する迄に要する時間は短＜、ＭＰＯＢは導通状態に
なる。従ってＭＰＯＢを介してＶｄｄから負荷へ電流が
流れ００１０レベルが上昇する。Is the NO3 level slightly higher than Vdd-V?
When the r03 potential decreases to a level below vdd-vTPo3, the time required is short, and MPOB becomes conductive. Therefore, current flows from Vdd to the load via MPOB and the 0010 level rises.
ここで端子００１のレベルがＮ０Ｒ１０入力閾値電圧を
超えて上昇するとＮｏａｉは反転してＮＯ６はロウレベ
ルとなｐ、ＭＮ０２は遮断状態となってＣＯ２の蓄積電
荷放電は停止し、ＮＯ４はＶｓｓｔ位迄下がることはな
い。更に００１のレベルは上昇し、Ｖｄｄと等しくなる
迄上昇して出力はノ・イレベルとなる。ＣＯＩの蓄積電
荷はＭＮＯＩによシ完全に放電されて、ＮＯ３０レベル
はＶｓｓと等しくなる。以上で全体のレベルは安定して
いる。Here, when the level of terminal 001 rises above the N0R10 input threshold voltage, Noai is inverted, NO6 becomes low level, MN02 is cut off, the discharge of the accumulated charge of CO2 is stopped, and NO4 falls to the level of Vsst. Never. Further, the level of 001 rises until it becomes equal to Vdd, and the output becomes the NO level. The accumulated charge in COI is completely discharged by MNOI, and the NO30 level becomes equal to Vss. Above all, the overall level is stable.
（３）入力電位がハイレベルよシロウレベルに反ＩＥし
た場合、ここで更に入力電位がロウレベルに転じると、
ＮＯＩはハイレベル、ＭＮＯＩは遮断状態、ＭＰＯ２は
導通状態となる。Ｎ０Ｒｘの出力ＮＯ６は００１０レベ
ルによらずロウレベルとなシ、ＭＮＯ２は遮断状態のま
まであるからＭＰＯ２と介してＣＯ２は充電されてＮＯ
４のレベルが上昇し、ｖＴＮｏｊを超えて上昇するとＭ
ＮＱ３は導通となるＯ
尚、本動作は、ＮＯ４のレベルが（２）の最終状態時に
おいてＶ よシ僅かながら低い電位ＮＱ ３
シ、ＮＡＮＤＩは反転してＮＯ５はロウレベルとなるか
ら、ＭＰＯＩは導通状態となシ、ｃｏ Ｉ ＦｉＭＰｏ
１を介して充電されてＮＯ３の電位が上昇する。ＮＯ
３の電位がＶｄｄ−Ｖ賛ｏ３を超えて上昇すると、らの
蓄積電荷放電によシ端子００１のレベＡＧＥ下がるＯ
ｉ子００１のレベルが、ＮＡＮ＃２の閾値電圧を下回る
と％ＮＯ５は反転してハイレベルとなり、ＭＰＯＩは遮
断状態となって、ＣＯｌへの充電動作は停止するから、
ＮＯ３のレベルはＶｄｄ−Ｖ、ｒｐＱ３よシ僅かげかシ
高い電位迄の上昇に留まｆｉ、Ｖｄｄ電位となることは
ない。(3) When the input potential changes from high level to low level, if the input potential further changes to low level,
NOI is at a high level, MNOI is in a cut-off state, and MPO2 is in a conductive state. The output NO6 of N0Rx is low level regardless of the 0010 level, and since MNO2 remains in the cut-off state, CO2 is charged via MPO2 and NO
When the level of 4 increases and exceeds vTNoj, M
In this operation, when the level of NO4 is in the final state of (2), the potential NQ3 is slightly lower than V, NANDI is inverted and NO5 becomes low level, so MPOI becomes conductive. state and nasi, co I FiMPo
1 and the potential of NO3 increases. NO
When the potential of terminal 001 rises above Vdd-Vo3, the level of terminal 001 decreases due to the discharge of the accumulated charges. When the level of terminal 001 falls below the threshold voltage of NAN#2, %NO5 is reversed. becomes high level, MPOI becomes cut off, and charging operation to COl stops.
The level of NO3 remains at Vdd-V, which is slightly higher than rpQ3, and never reaches the fi, Vdd potential.
ＣＯＩはＭＰＯ２を介して更に充電されつづけて、ＮＯ
４の電位はＶｄｄ迄上昇し、負荷に蓄積されて−た電荷
ｔｆＭＮＯ３により放電されつづけて端子００１はロウ
レベルとなシ、全体のレベルは（１）の最終状態と等し
くなって安定な状態となる。COI continues to be further charged via MPO2 and NO
The potential of 4 rises to Vdd, continues to be discharged by the charge tfMNO3 accumulated in the load, and the terminal 001 becomes low level. The overall level becomes equal to the final state of (1) and becomes stable. .
以降は入力レベルの変化によ〕上述の一連の動作を繰シ
返し行なう。Thereafter, the above-described series of operations is repeated depending on changes in the input level.
第２図は本発明の第２の実施例としての３−ステート出
力のバフ７７回路を示す。Ｖｄｄは電源端子Ｖｓｓは接
地端子、ＩＯＩはＥＮＯＩは入力端子、００２は出力端
子、Ｎｏ １． Ｎｏ ２． Ｎｏ ３゜ＮＯ４，Ｎｏ
５． Ｎｏ ６． ＮＯ７，Ｎｆｌ ８は各々節点、
ＩＮｖｌはＩＯＩを入力、Ｎ０１ｅ出力とするインバー
タ論理回路、Ｎ０ＲＩ ＦｉＮｏｌ並びＫＯＯＩを入力
とし、ＮＯ６’Ｊｉ出力とする２人力ＮＯＲ論理回路、
ＮＡＮＤＩ ＦｉＮＯｌ並びに端子００１を入力、ＮＯ
Ｉを出力とする２人力ＮＡＮＤ論理回路、ＩＮ−■２は
ＥＮＯｌを入力、ＮＱ７＠出力とするインバータ論理回
路、ＭＰＯ４はソースがＶｄｄがゲートがＥＮＯＩＫ、
ドレインがＮＯ３に接続されたＰ形Ｍ０８トランジスタ
、ＭＰＯＩはソースがＶｄｄに、ゲートがＮＯ５にドレ
イ／がＮＯ３に接続されｔＰ形ＭＯ８）？ンジスタ、Ｍ
ＰＯ３はソースがＶｄｄに、ゲートがＮＯ３に、ドレイ
ンが端子００１に接続されたＰ形ＭＯ８トランジスタ、
ＭＰＯ５はソースがＶｄｄに、ゲートがＮｏ７ｒｃ、
ドレインがＮＯ９に接続されｔＰ形ＭＯＢ トランジ
スタ、ＭＰＯ２はソースがＮＯ９に、ゲートがＩＯＩに
、ドレインがＮＯ４に接続されたＰ形ＭＯ８トランジス
タ、ＭＮｇｌはソースが１’１０８に、ゲートがＩＯＩ
に、ドレインがＮＯ３に接続されたＮ形ＭＯ８トランジ
スタ、ＭＮ Ｑ ４はソースがＶｓｓに、ゲートがＢＮ
ＯＩに、ドレインがＮＯ８に接続されたＮ形ＭＯ８トラ
ンジスタ、ＭＮＯ５は、ソースがＷａｓに、ゲートがＮ
Ｏ７に、ドレインがＮＯ４に接続され７ｊＮ形ＭＯ８ト
ランジスタ、ＭＮＱ２ｆ−ｊ：、７−スがＶｓｓに、ゲ
ートがＮ０６Ｋ。FIG. 2 shows a 3-state output buff 77 circuit as a second embodiment of the invention. Vdd is a power supply terminal, Vss is a ground terminal, IOI is an input terminal, ENOI is an input terminal, 002 is an output terminal, No. 1. No. 2. No 3゜NO4, No
5. No. 6. NO7 and Nfl 8 are nodes,
INvl is an inverter logic circuit that inputs IOI and outputs N01e, a two-person NOR logic circuit that inputs N0RI, FiNol, and KOOI, and outputs NO6'Ji;
Input NANDI FiNOl and terminal 001, NO
A two-person NAND logic circuit with I as the output, IN-■2 is an inverter logic circuit with ENOl as input and NQ7 @ output, MPO4 has a source of Vdd and a gate of ENOIK,
P-type M08 transistor with drain connected to NO3, MPOI has source connected to Vdd, gate connected to NO5, drain/tP-type MO8) connected to NO3? Nzista, M.
PO3 is a P-type MO8 transistor whose source is connected to Vdd, gate is connected to NO3, and drain is connected to terminal 001;
The source of MPO5 is Vdd, the gate is No7rc,
tP type MOB transistor with drain connected to NO9, MPO2 is a P type MO8 transistor with source connected to NO9, gate connected to IOI, drain connected to NO4, MNgl has source connected to 1'108, gate connected to IOI
, an N-type MO8 transistor with its drain connected to NO3, MN Q4 has a source connected to Vss and a gate connected to BN
An N-type MO8 transistor with its drain connected to OI and NO8, MNO5 has its source connected to Was and its gate connected to N
7j N-type MO8 transistor with drain connected to NO4, MNQ2f-j:, 7-sse connected to Vss, gate N06K.
ドレインがＮＯ４に接続され［Ｎ形ＭＯ８トランジスタ
、ＭＮｏａはソースがＶｓｓに、ゲートがＮＯ４に、ド
レインが端子００１に接続されたＮ形ＭＯ８）？ｙジｘ
／、Ｃ０ＩｔｉＮＯ３とＶｓｓ間の寄生容量、Ｃ０２は
ＮＯ４とＶｓｓ間のを生容量である。The drain is connected to NO4 [N-type MO8 transistor, MNoa is an N-type MO8 transistor whose source is connected to Vss, gate is connected to NO4, and drain is connected to terminal 001)? yji x
/, C0Iti is the parasitic capacitance between NO3 and Vss, and C02 is the raw capacitance between NO4 and Vss.
次に本実施例の動作について述べる。Next, the operation of this embodiment will be described.
（１）ＥＮＯＩがロウレベルの場合、ＭＰＯ４は導通状
１ＭＮＯ４は遮断状７ａ、Ｎｏ ７ ハＩＮＶ２ ＫＪ
：ｌ）ハ４レベルとな、り、ＭＰＯ５は遮断状態、州０
５は導通状態となるから、他の節点、入力端子のレベル
によらずＭＰＯ３，ＭＮＯ３は遮断状態となル、端子０
０１はハイ−インピーダンス状態となる。(1) When ENOI is low level, MPO4 is conductive 1MNO4 is disconnected 7a, No. 7 high INV2 KJ
:l) Level 4, MPO5 is blocked, state 0
5 becomes conductive, MPO3 and MNO3 are cut off regardless of the levels of other nodes and input terminals, and terminal 0
01 is in a high-impedance state.
（２）ＥＮＯＩがハイレベルの場曾、ＭＰＯ４は遮断状
態、ＭＮＯ４ｔ−１導通状ｍ、Ｎ０７ｔ：ｔ ＩＮＶ２
ＫＪ Ｃロウレベルとなｊ）ＭＰＯ５は導通状態、Ｍ
ＮＯ５は遮断状態となり、結果としてＮＯ８はＶｓｓ電
位、ＮＯ９はＶｄｄ電位とな９、遮断状態にあるＭ−Ｐ
Ｇ ４． ＭＮＯ５を無視すると、第１図の実施例と同
一の回路となるから入力端子Ｉ０１のレベルによシ、第
１図の実施例と全く同じ動作を行う。(2) When ENOI is at high level, MPO4 is cut off, MNO4t-1 is conductive, N07t:t INV2
KJ C low level j) MPO5 is in conduction state, M
NO5 is in the cut-off state, and as a result, NO8 is at the Vss potential and NO9 is at the Vdd potential.9, M-P in the cut-off state
G4. If MNO5 is ignored, the circuit becomes the same as the embodiment shown in FIG. 1, and therefore operates exactly the same as the embodiment shown in FIG. 1, depending on the level of the input terminal I01.
第３図は本発明の第３の実゛施例としてのＰ形ル・ダウ
ン抵抗であ）、他の節点、端子、素子は、前述の第１図
のものと同一でるる。FIG. 3 shows a P-type pull-down resistor as a third embodiment of the present invention, and other nodes, terminals, and elements are the same as those in FIG. 1 described above.
回路動作においては、第１図中のＭＮＯ３ｔ−ＲＩＫ置
き換え、ＭＰＯ２，ＭＮＯ２，Ｎ０ＲＩ ｔ−削除して
あり、第１図の回路動作に準する。In the circuit operation, MNO3t in FIG. 1 is replaced with RIK, and MPO2, MNO2, N0RI t- are deleted, and the circuit operation is similar to that in FIG.
第４図は本発明の第４の実施例としてのＮ形ＭＯ８オー
プン・ドレイン回路を示す。Ｒ＋２はプル・アップ抵抗
で、ｉＳｎ、他の節点、端子、素子は前述の第１図のも
のと同一である。FIG. 4 shows an N-type MO8 open drain circuit as a fourth embodiment of the present invention. R+2 is a pull-up resistor, iSn, and other nodes, terminals, and elements are the same as those in FIG. 1 described above.
回路動作に訃いては第１図中のＭＰＯ３’１ｉＲ２に置
ａｇ、ｔ、ＭＰＯＩ、 ＭＮＯＩ、 ＮＡＮＤＩ ｔ’
ＭＩＩ除ＬテあシしＷＥ１図の回路動作に準する。Regarding circuit operation, ag, t, MPOI, MNOI, NANDI t' are placed in MPO3'1iR2 in Figure 1.
The circuit operation corresponds to the circuit operation shown in Figure WE1 except for MII.
以上説明した様に、本発明は、出力駆動ＭＯ８トランジ
スタのゲート電位の過剰な変化管抑えて、状態遷移時間
を短縮することにより■パッツァ動作装置の向上を図れ
、■バラ２ア動作の消費電力を小さくできるという効果
が有る。As explained above, the present invention suppresses excessive changes in the gate potential of the output drive MO8 transistor and shortens the state transition time. By doing so, it is possible to (1) improve the Pazza operating device; and (2) improve the power consumption of the two-channel operation. This has the effect of making it smaller.
第１図は本発明の出１の実施例の回路図、第２図は本発
明の第２の実施例の回路図１４３図は本発明の第３の実
施例の回路図、第４図は本発明の第４の実施例の回路図
、第５図は従来例の回路図である。
Ｖｄｄ・・・・・・電源端子、Ｖｓｓ・・・・・・接地
端子、ｌｏ−１１１、ＥＮＯＩ・・・・・・入力端子、
００１．０１１・・・・・・出力端子、ＮＯＩ、ＮＯ２
，ＮＯ３，ＮＯ４，Ｎ□５ｓＮＯ６，ＮＯ７゜ＮＯ８，
ＮＯ９，Ｎｌ １−−−・−接点、ＩＮＶＩ、ＩＮＶ２
−山−インバータ論理回路、Ｎ０Ｒ１１・・・・・・２
人力ＮＯＲ，論理回路、ＮＡＮＤＩ・・・・・・２人力
ＮＡＮＤ倫理回路、ＭＰＯＩ、ＭＰＯ２，ＭＰＯ３，Ｍ
ＰＯ４，ＭＰｌｌ、ＭＰ１３・・・・・・Ｐ形ＭＯ８ト
ランジスタ、ＭＮＯ１，ＭＮＯ２，ＭＮ−０３、ＭＮＯ
４，ＭＮＯ５，ＭＮＩ １． ＭＮ １３・・・・・・
Ｎ形ＭＯＳトランジスタ、ＣＯＩ、ＣＯ２，Ｃ１ｌ・・
・・・・寄生容量、Ｒ１・・・・・・プルダウン抵抗、
Ｒ２・・・・・・プルアップ抵抗。
代理人 弁理士 内 原 音
扇５図FIG. 1 is a circuit diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of the second embodiment of the present invention, and FIG. 4 is a circuit diagram of the third embodiment of the present invention. A circuit diagram of the fourth embodiment of the present invention, and FIG. 5 is a circuit diagram of a conventional example. Vdd...Power supply terminal, Vss...Ground terminal, lo-111, ENOI...Input terminal,
001.011...Output terminal, NOI, NO2
,NO3,NO4,N□5sNO6,NO7゜NO8,
NO9, Nl 1---Contact, INVI, INV2
- Mountain - Inverter logic circuit, N0R11...2
Human power NOR, logic circuit, NANDI...2 human power NAND ethical circuit, MPOI, MPO2, MPO3, M
PO4, MPll, MP13...P-type MO8 transistor, MNO1, MNO2, MN-03, MNO
4, MNO5, MNI 1. MN 13...
N-type MOS transistor, COI, CO2, C1l...
...Parasitic capacitance, R1...Pull-down resistance,
R2...Pull-up resistor. Agent Patent Attorney Uchihara Otoogi 5
Claims (1)
ＭＯＳトランジスタのゲートを駆動する第２のＭＯＳト
ランジスタと、該第２のＭＯＳトランジスタのゲートを
駆動する論理回路を有し、該論理回路にはバッファの入
力信号とバッファ出力の帰還信号が加わることを特徴と
するバッファ回路。The logic circuit includes a first MOS transistor for output driving, a second MOS transistor that drives the gate of the first MOS transistor, and a logic circuit that drives the gate of the second MOS transistor. is a buffer circuit characterized in that a buffer input signal and a feedback signal of the buffer output are added.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005754A JPH01181223A (en) | 1988-01-13 | 1988-01-13 | Buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005754A JPH01181223A (en) | 1988-01-13 | 1988-01-13 | Buffer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01181223A true JPH01181223A (en) | 1989-07-19 |
Family
ID=11619906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63005754A Pending JPH01181223A (en) | 1988-01-13 | 1988-01-13 | Buffer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01181223A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1211807A1 (en) * | 2000-11-29 | 2002-06-05 | Phoenix Contact GmbH & Co. KG | Digital level adaptation circuit |
| CN102518020A (en) * | 2011-12-20 | 2012-06-27 | 中联重科股份有限公司 | Asphalt mixture thermal regeneration equipment and combustion device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63153919A (en) * | 1986-09-30 | 1988-06-27 | テキサス インスツルメンツ インコーポレイテツド | Cmos logic circuit with improved noise characteristics |
-
1988
- 1988-01-13 JP JP63005754A patent/JPH01181223A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63153919A (en) * | 1986-09-30 | 1988-06-27 | テキサス インスツルメンツ インコーポレイテツド | Cmos logic circuit with improved noise characteristics |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1211807A1 (en) * | 2000-11-29 | 2002-06-05 | Phoenix Contact GmbH & Co. KG | Digital level adaptation circuit |
| US6552568B2 (en) | 2000-11-29 | 2003-04-22 | Phoenix Contact Gmbh & Co. Kg | Level shifter circuit for level adjustment |
| CN102518020A (en) * | 2011-12-20 | 2012-06-27 | 中联重科股份有限公司 | Asphalt mixture thermal regeneration equipment and combustion device |
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