JPH01180128A - Level reduction detecting circuit - Google Patents

Level reduction detecting circuit

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Publication number
JPH01180128A
JPH01180128A JP63004130A JP413088A JPH01180128A JP H01180128 A JPH01180128 A JP H01180128A JP 63004130 A JP63004130 A JP 63004130A JP 413088 A JP413088 A JP 413088A JP H01180128 A JPH01180128 A JP H01180128A
Authority
JP
Japan
Prior art keywords
level
output
alarm
input signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63004130A
Other languages
Japanese (ja)
Inventor
Shingo Okamoto
岡本 眞吾
Shinji Tanabe
信二 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63004130A priority Critical patent/JPH01180128A/en
Publication of JPH01180128A publication Critical patent/JPH01180128A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To detect accurately the reduction of a reception input signal level by squaring and summing a real component and an imaginary component of an output signal of a correlation device respectively, comparing the summing output with a prescribed level and raising an alarm. CONSTITUTION:The real component and the imaginary component of an output signal of a correlation device used for a diversity synthesizing circuit of a receiver are inputted respectively to a real port 1 and an imaginary port 2 respectively, squared by square circuits 3a, 3b and added by an adder circuit 4. The addition output is given to one input terminal of a signal level comparator 5a and an alarm level designated by a level designation device 6a is given to the other input terminal of the comparator 5a. The result of comparison is outputted to an alarm output terminal 7. Thus, the level reduction of the reception input signal level only is detected independently of the frequency difference and phase difference between the two signals fed to the correlation device in this way.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ダイバーシティ合成回路等に用いられる相関
器の出力レベルの低下により受信入力信号のレベル低下
を検出するレベル低下検出器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level drop detector that detects a drop in the level of a received input signal due to a drop in the output level of a correlator used in a diversity synthesis circuit or the like.

〔従来の技術〕[Conventional technology]

見通し外通信においては、ダイパシティ信号合成制御や
、自動等化のために7ダプテイブマツチドフイルタ及び
フォアワードイコライザが使われている。これらに使わ
れる相関器は、受信入力信号がアンテナ、ダウンコンバ
ーダ及び自動利得制御アンプを経た後の信号すなわちI
P(中間周波)信号、及び基準信号が与えられ、これら
2信号の相関をとっている。ここでIP倍信号レベルは
受信入力信号レベルに対応しており、さらに相関器の出
力レベルも受信入力信号レベルに対応している。この相
関器の出力レベル低下を検出することにより受信入力信
号のレベル低下を検出する装置がある。さらにこの種の
装置のうち相関器の出力レベルのリアル成分及びイマジ
ナリ成分について、それぞれ独立にレベル検出を行うこ
とによって受信入力信号のレベル低下を検出する装置が
ある。
In non-line-of-sight communications, seven adaptive matched filters and forward equalizers are used for dipacity signal synthesis control and automatic equalization. The correlator used in these applications is a signal after the received input signal has passed through an antenna, a down converter, and an automatic gain control amplifier, that is, I
A P (intermediate frequency) signal and a reference signal are given, and the correlation between these two signals is taken. Here, the IP multiplied signal level corresponds to the received input signal level, and furthermore, the output level of the correlator also corresponds to the received input signal level. There is a device that detects a decrease in the level of a received input signal by detecting a decrease in the output level of this correlator. Furthermore, among these types of devices, there is a device that detects a drop in the level of a received input signal by independently detecting the levels of the real component and the imaginary component of the output level of the correlator.

第4図に、従来のレベル低下検出器のブロック図を示す
。相関器からの出力のリアル成分及びイマジナリ成分は
、それぞれリアルポート1及びイマジナリポート2を介
して、信号レベル比較器5b、5c、5d及び5eの一
方の入力端子に供給されている。信号レベル比較器5b
、5c、5d及び5eの他方の入力端子には、レベル指
定器6c及び6dからそれぞれ予め定めた所定のレベル
が供給されている。レベル指定器6C及び6dは、上述
のリアル成分及びイマジナリ成分のレベル低下を検出す
る際の警報レベルrを検出したい受信入力信号レベルに
指定しており、たとえば6cで上限値、6dで下限室を
設定する。この警報レベルrで設定されたR’−I平面
上での警報範囲を第5図に示す。図中実線で囲まれた斜
線を施した範囲が警報範囲9である。この範囲9に相関
器からの出力が入る場合警報出力端子7から例えば“工
”を出力し、警報出力とする。
FIG. 4 shows a block diagram of a conventional level drop detector. The real component and imaginary component of the output from the correlator are supplied to one input terminal of signal level comparators 5b, 5c, 5d, and 5e via real port 1 and imaginary port 2, respectively. Signal level comparator 5b
, 5c, 5d and 5e are supplied with predetermined levels from level designators 6c and 6d, respectively. The level designators 6C and 6d designate the received input signal level to be detected as the alarm level r when detecting the decrease in the level of the real component and the imaginary component described above. For example, 6c is the upper limit value, and 6d is the lower limit chamber. Set. The alarm range on the R'-I plane set at this alarm level r is shown in FIG. The hatched range surrounded by solid lines in the figure is the alarm range 9. When the output from the correlator falls within this range 9, the alarm output terminal 7 outputs, for example, "work" as an alarm output.

ところで、検出したい受信入力信号レベルなA1相関器
へ供給される2信号すなわちIF倍信号び基準信号間の
周波数差をf1移送差をθとすると相関器から出力され
るリアル成分RはR=Acos(ft+θ)イマジナリ
成分工はI=Asin(f t+θXtは任意の時刻)
と表される。従って、入力信号レベルAはR−I平面上
でA”=R1+I”(原点中心、半径Aの円)となる。
By the way, if the frequency difference between the two signals supplied to the A1 correlator at the received input signal level to be detected, that is, the IF multiplied signal and the reference signal, is the f1 transfer difference, then the real component R output from the correlator is R = Acos (ft + θ) Imaginary component work is I = Asin (f t + θXt is any time)
It is expressed as Therefore, the input signal level A becomes A''=R1+I'' (a circle centered at the origin and radius A) on the RI plane.

いま、入力信号レベルAが警報レベルrより少し大きい
場合について第5図を使って説明する。
Now, the case where the input signal level A is slightly higher than the alarm level r will be explained using FIG.

図中点線で示した円10が入力信号レベルを示している
。図かられかるように、円10上のa点とb点はそれぞ
れ警報範囲9の内及び外に存在する。
A circle 10 indicated by a dotted line in the figure indicates the input signal level. As can be seen from the figure, points a and b on the circle 10 are located inside and outside the warning range 9, respectively.

すなわち、周波数差f=oであっても位相差θが00場
合、(a点)とπ/4の場合(b点)では警報範囲の内
と外に別れ、周波数差f≠0だと相関器からの出力は点
線の円10上を前述の周波数差fの周波数で円運動する
。このため、入力信号レベルは警報範囲9の内外を往復
することになる。
In other words, even if the frequency difference f=o, if the phase difference θ is 00, there will be a difference between inside and outside the alarm range for (point a) and π/4 (point b), and if the frequency difference f≠0, there will be a correlation. The output from the device moves circularly on the dotted circle 10 at a frequency equal to the frequency difference f described above. Therefore, the input signal level will go back and forth within and outside the alarm range 9.

従って、相関器に供給される2信号間に周波数差f及び
位相差がある場合には、従来の装置による警報範囲では
、入力信号レベルAのレベル低下を正確に検出できない
という欠点が生じる。
Therefore, when there is a frequency difference f and a phase difference between the two signals supplied to the correlator, a drawback arises in that a decrease in the level of the input signal level A cannot be accurately detected within the alarm range of the conventional device.

そこで本発明は、正確に受信入力信号レベルの低下の検
出ができるレベル低下検出器を提供することを目的とし
ている。
SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a level drop detector that can accurately detect a drop in the received input signal level.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記目的を達成するために本発明によれば、受信装置の
ダイバーシティ合成回路等に用いられる相関器の出力信
号のレベル低下により受信入力信号のレベル低下を検出
するレベル低下検出器において、相関器の出力信号のリ
アル成分及びイマジナリ成分をそれぞれ2乗する2乗回
路と、これら2乗回路の出力を加算する加算器と、この
加算器の出力と所定レベルとを比較し警報信号を発生す
る回路とを含むことを特徴とするレベル低下検出回路が
得られる。
In order to achieve the above object, the present invention provides a level drop detector for detecting a drop in the level of a received input signal due to a drop in the level of the output signal of a correlator used in a diversity combining circuit or the like of a receiving device. A squaring circuit that squares the real component and imaginary component of the output signal, an adder that adds the outputs of these squaring circuits, and a circuit that compares the output of this adder with a predetermined level and generates an alarm signal. A level drop detection circuit is obtained, which is characterized in that it includes the following.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の実施例を示すブロック図である。リア
ルポート1及びイマジナリポート2に入力される相関器
からの出力のリアル成分R=Acos(f十〇)及びイ
マジナリ成分I=Asin (f t+θ)は、それぞ
れ2東回路3a及び3bで2乗された後、加算器4で加
算され、出力A2(=I”+−R”)として信号レベル
比較器5aの一方の入力端子に与えられる。信号レベル
比較器5aの他方の入力端子には、レベル指定器6aに
より指定された警報レベル、たとえばr2が与えられて
いる。
FIG. 1 is a block diagram showing an embodiment of the present invention. The real component R = Acos (f 10) and the imaginary component I = Asin (f t + θ) of the output from the correlator input to the real port 1 and the imaginary port 2 are squared by the 2 east circuits 3a and 3b, respectively. After that, they are added by an adder 4, and are applied as an output A2 (=I"+-R") to one input terminal of a signal level comparator 5a. The other input terminal of the signal level comparator 5a is given an alarm level designated by the level designator 6a, for example r2.

このレベルr2と前述の出力A2の比較により、出力A
2がレベルr2より小さい場合警報出力端子7から例え
ば“l”を出力し、警報出力とする。
By comparing this level r2 and the above-mentioned output A2, the output A
2 is smaller than the level r2, the alarm output terminal 7 outputs, for example, "l" as an alarm output.

第3図に加算器の出力と警報範囲を示す。加算器からの
出力A” (=I”十R”)は点線で示すようにR−I
平面原点を中心とする半径Aの円10で表される。すな
わち、出力A2とレベルr2の比較は、R−I平面上で
円A”=R2+I 2が円r2=R2+I”で示される
警報範囲8内に入っているか否かを検出していることに
なる。
Figure 3 shows the output of the adder and the alarm range. The output A” (=I”10R”) from the adder is R-I as shown by the dotted line.
It is represented by a circle 10 with a radius A centered at the plane origin. In other words, the comparison between the output A2 and the level r2 detects whether or not the circle A''=R2+I2 is within the alarm range 8 indicated by the circle r2=R2+I'' on the R-I plane. .

従って、相関器へ供給される2信号間の周波数差f及び
位相差θとは無関係に受信入力信号レベルAのみのレベ
ル低下検出ができる。
Therefore, a level drop in only the received input signal level A can be detected regardless of the frequency difference f and phase difference θ between the two signals supplied to the correlator.

第2図は本発明の他の実施例を示すブロック図である。FIG. 2 is a block diagram showing another embodiment of the invention.

この例は第1図の加算器4の後段に平方根回路8を備え
境界値レベルをrとしている。平方根回路8からの出力
は、検出したい受信入力信号レベルと同等になり、この
レベルに従って警報レベルを定めることが可能である。
In this example, a square root circuit 8 is provided after the adder 4 shown in FIG. 1, and the boundary value level is r. The output from the square root circuit 8 will be equal to the level of the received input signal that is desired to be detected, and it is possible to determine the alarm level according to this level.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、相関器へ供給され
る2信号の周波数及び位相差の影響を受けずに受信入力
信号のレベル低下を正確に検出することができる。
As described above, according to the present invention, a drop in the level of a received input signal can be accurately detected without being affected by the frequency and phase difference between two signals supplied to a correlator.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すブロック図、第2図は本
発明の他の実施例を示すブロック図、第3図は第1図の
回路の警報範囲を示す図、第4図は従来例を示すブロッ
ク図、第5図は第4図の従来例の回路の警報範囲を示す
図である。 1・・・・・・リアルボート、2・・・・・・イマジナ
リポート、3a、3b・・・・・・2乗回路、4・・・
・・・加算器、5a。 5b、5c、5d・・・・・・信号レベル比較器、6a
。 6b、6c、6d・・・・・・レベル指示器、7・・・
・・・警報出力端子、8,9・・・・・・警報範囲。 代理人 弁理士  内 原   音 躬1図 袷2図 躬3図 第4図 第5図
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, Fig. 3 is a diagram showing the alarm range of the circuit in Fig. 1, and Fig. 4 is a block diagram showing an embodiment of the present invention. FIG. 5, a block diagram showing a conventional example, is a diagram showing an alarm range of the conventional example circuit of FIG. 1... Real boat, 2... Imaginary report, 3a, 3b... Square circuit, 4...
... Adder, 5a. 5b, 5c, 5d... Signal level comparator, 6a
. 6b, 6c, 6d...Level indicator, 7...
...Alarm output terminal, 8, 9...Alarm range. Agent Patent Attorney Hara Uchihara Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 受信装置のダイバーシティ合成回路等に用いられる相関
器の出力信号のレベル低下により受信入力信号のレベル
低下を検出するレベル低下検出器において、前記相関器
の出力信号のリアル成分及びイマジナリ成分をそれぞれ
2乗する2乗回路と、これら2乗回路の出力を加算する
加算器と、この加算器の出力と所定レベルとを比較し警
報信号を発生する回路とを含むことを特徴とするレベル
低下検出回路。
In a level drop detector that detects a drop in the level of a received input signal due to a drop in the level of an output signal of a correlator used in a diversity synthesis circuit of a receiving device, the real component and the imaginary component of the output signal of the correlator are squared, respectively. 1. A level drop detection circuit comprising: a squaring circuit for squaring, an adder for adding the outputs of these squaring circuits, and a circuit for comparing the output of the adder with a predetermined level and generating an alarm signal.
JP63004130A 1988-01-11 1988-01-11 Level reduction detecting circuit Pending JPH01180128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63004130A JPH01180128A (en) 1988-01-11 1988-01-11 Level reduction detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63004130A JPH01180128A (en) 1988-01-11 1988-01-11 Level reduction detecting circuit

Publications (1)

Publication Number Publication Date
JPH01180128A true JPH01180128A (en) 1989-07-18

Family

ID=11576201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63004130A Pending JPH01180128A (en) 1988-01-11 1988-01-11 Level reduction detecting circuit

Country Status (1)

Country Link
JP (1) JPH01180128A (en)

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