JP3364828B2 - Diversity receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver having two or more antennas and performing combined diversity in a receiver used for wireless communication.

[0002]

2. Description of the Related Art FIG. 9 shows an ER Performance of QDPSK wi.
th Postdetection Diversity Reception in Mobile Rad
io Channels *, (IEEE TRANSACTIONS VEHICULAR TECNOLO
GY, VOL.40.NO.1, FEBRUARY 1991), etc., is a block diagram illustrating the configuration of a conventional diversity receiver. In FIG. 9, 1a is an antenna, 2a is a BPF (Band Pass Filter) that passes only the reception band of the input signal of the antenna 1a, and 3a is a limiter amplifier that amplifies the output signal of the BPF 2a and outputs it with a constant amplitude. Reference numeral 4a is a delay detection circuit for detecting a phase shift between symbols from the output signal of the limiter amplifier 3a, and 5a is a coordinate conversion circuit for converting the phase Δθi detected by the delay detection circuit 4a into rectangular coordinates.

Reference numeral 6a designates an envelope detection circuit for outputting a voltage (RSSI voltage) corresponding to a signal received by the antenna 1a, and 7a designates the RS.
This is a multiplication circuit that multiplies the SI voltage by the output voltage of the coordinate conversion circuit 5a and outputs the result. These antennas 1a, B
PF2a, limiter amplifier 3a, delay detection circuit 4a, coordinate conversion circuit 5a, envelope detection circuit 6a, and multiplication circuit 7
a is a 1-system configuration. The diversity receiver has a plurality of similar configurations, and the antenna 1b and BPF of FIG.
2b, the limiter amplifier 3b, the differential detection circuit 4b, the coordinate conversion circuit 5b, the envelope detection circuit 6b, and the multiplication circuit 7b have a two-system configuration, and the antenna 1a and the BPF 2 are provided, respectively.
a, limiter amplifier 3a, delay detection circuit 4a, coordinate conversion circuit 5a, envelope detection circuit 6a, and multiplication circuit 7a.

Reference numeral 8 is a vector adder for vector-adding the outputs of the above-mentioned two multiplication circuits 7a and 7b and outputting them.
A maximum likelihood sequence determination unit 9 determines which of the phase shifts the output vector phase of the vector adder 8 may possibly transmit, and decodes the data in the reception signals of the antennas 1a and 1b. Reference numeral 10 is a bit synchronization circuit (Bit Timing Recovery; BTR) that reproduces the clock of a transmitter (not shown) that has transmitted the signal received by the antenna 1a.
Is.

Next, the operation will be described. First, the operation of the 1-system will be described. The signal received by the antenna 1a, that is, the antenna input becomes a signal only in the reception band by passing through the BPF 2a, and further, by passing through the limiter amplifier 3a, becomes a signal whose amplitude is constant regardless of the size of the antenna input. Is output. The differential detection circuit 4a detects the phase shift Δθi between the symbols from the output signal of the limiter amplifier 3a and outputs the detected phase shift Δθi. This phase shift Δθi is converted by the coordinate conversion circuit 5a into the rectangular coordinates Xi + j · Yi. Where X
i = cos (Δθi) and Yi = sin (Δθi).

On the other hand, the signal received by the antenna 1a is input to the envelope detection circuit 6a via the BPF 2a, and the RSSI signal voltage Ri corresponding to the received signal is output. The characteristic of this RSSI voltage is shown in FIG. The multiplication circuit 7a multiplies the RSSI voltage Ri by the output signal of the coordinate conversion circuit 5a, that is, the signal of the Cartesian coordinates Xi + j.Yi, and outputs as Ri.Xi + j.Ri.Yi.

In the 2-system, the 2-system configuration corresponding to the 1-system configuration operates in the same manner, and the multiplication circuit 7b outputs the same signal. This output signal is Rj · Xj + j · Rj · Yj.

Next, the vector adder 8 outputs a signal Ri.Xi + j.Ri.Yi obtained from the 1-system multiplication circuit 7a and a signal Rj.Xj + j obtained from the 2-system multiplication circuit 7b.・ Vector addition of Rj and Yj as shown in FIG.

In this way, the same bit error rate can be obtained as compared with the selection diversity in which the received signals of the 1st and 2nd systems are vector-synthesized and demodulated, and the one with the larger input of the two antennas is selected and demodulated. There is an advantage that the required C / N to be obtained is low.

[0010]

As described above, the conventional diversity receiver uses only the RSSI voltage as reliability information, and the signal input from the antenna has a magnitude proportional to this reliability information. The output of the differential detection circuit 4a is replaced with a vector having that direction. Then, since it is configured to combine the vectors of the signals received by the two antennas, estimate the transmitted phase shift, and demodulate,
Noise in the RSSI voltage is a major factor in the occurrence of errors. However, when the antenna input is low, that is, when the received signal is weak, the magnitude of the thermal noise component generated in the diversity receiver cannot be ignored compared to the received signal component at the antenna input, and therefore the envelope detection circuit The envelope of only the signal component cannot be detected. Figure 2
As is also shown, when the antenna input is low, even if the input level is changed, the RSSI voltage does not change so much and is not proportional to the antenna input, so the reliability of the RSSI voltage itself becomes low. For the above reasons, the conventional diversity receiver has a problem that a sufficient diversity effect cannot be obtained when the antenna input is low.

The present invention has been made to solve the above problems, and an object thereof is to obtain a sufficient diversity effect even when the antenna input is low.

[0012]

In the diversity receiver according to the present invention, first magnitude detecting means for detecting the magnitude of the signal received by the first antenna and outputting it as the first magnitude signal. And a first suppressing means for suppressing and outputting the first magnitude signal output by the first magnitude detecting means based on the magnitude of the signal received by the first antenna, and the first Direction detecting means for detecting the direction of the vector of the signal received by the second antenna and outputting it as the first direction signal, and detecting the magnitude of the signal received by the second antenna to obtain the second magnitude. Second output as a signal
Size detecting means, second direction detecting means for detecting the direction of the vector of the signal received by the second antenna and outputting it as a second direction signal, and first direction outputting means for the first suppressing means. 1 magnitude signal, the first direction signal output by the first direction detecting means, the second magnitude signal output by the second magnitude detecting means, and the second direction detecting means Signal synthesizing means for synthesizing the output second direction signal
And the first suppressing means receives the first antenna.
Noise squelch means for detecting noise in the signal and this noise
The noise detected by the Isquelch means is converted into the first magnitude signal.
Noise removal means for removing and outputting the noise .

The signal synthesizing means generates a vector signal from the first magnitude signal output from the noise removing means and the first direction signal output from the first direction detecting means. Generating means, second vector signal generating means for generating a vector signal from the second magnitude signal output by the second suppressing means and the second direction signal output by the second direction detecting means; A vector signal generated by the first vector signal generating means and a vector signal generated by the second vector signal generating means are combined with each other.

Further, there is provided a discriminating means for discriminating the data contained in the signals received by the first antenna and the second antenna on the basis of the result of the combination by the combining means.

Further, there is provided a third suppressing means for suppressing and outputting the first magnitude signal outputted by the envelope detecting means on the basis of the noise detected by the noise squelch means, and the first vector signal generating means. Is to generate a vector signal from the first magnitude signal output by the third suppressing means and the first direction signal output by the first direction detecting means.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Next, a first embodiment of the present invention will be described. Figure 1
FIG. 3 is a functional block diagram of the diversity receiver according to the first embodiment. In FIG. 1, reference numeral 1a denotes an antenna serving as a first antenna, and 2a denotes a BPF (Band Pass) that passes only a reception band of a reception signal of the antenna 1a.
Filter), the output signal of this BPF 2a is transmitted to the circuit in the subsequent stage as a signal received by the first antenna. 3a is a limiter amplifier that amplifies the output signal of the BPF 2a and outputs it with a constant amplitude, 4a is a delay detection circuit that detects a phase shift between symbols from the output signal of the limiter amplifier 3a, and 5a is this delay detection circuit 4a. Phase Δθi detected at
It is a coordinate conversion circuit that converts the coordinates into rectangular coordinates.

Reference numeral 6a denotes an envelope detection circuit for outputting a voltage (RSSI voltage) corresponding to the received signal of the antenna 1a, and 11a denotes B
The noise squelch circuit detects a noise component in the signal received by the first antenna 1a output from the PF 2a, and outputs a noise squelch voltage as shown in FIG. 12a
Is an adder that outputs reliability information Ri obtained by subtracting the noise squelch circuit voltage R2i output by the noise squelch circuit 11a from the RSSI voltage R1i output by the envelope detection circuit 6a. A multiplication circuit 7a multiplies the reliability information Ri by the output voltage of the coordinate conversion circuit 5a and outputs the product.

These antenna 1a, BPF 2a, limiter amplifier 3a, differential detection circuit 4a, coordinate conversion circuit 5
a, the envelope detection circuit 6a, the multiplication circuit 7a, the noise squelch circuit 11a, and the adder 12a have a one-system configuration.
The diversity receiver has a plurality of similar configurations, and the antenna 1b, BPF 2b, limiter amplifier 3b, delay detection circuit 4b, coordinate conversion circuit 5b, envelope detection circuit 6b, multiplication circuit 7b, noise squelch circuit 11 of FIG.
b and the adder 12b have a two-system configuration.
Antenna 1a, BPF 2a, limiter amplifier 3a, delay detection circuit 4a, coordinate conversion circuit 5a, envelope detection circuit 6
a, the multiplication circuit 7a, the noise squelch circuit 11a, and the adder 12a.

Reference numeral 8 is a vector adder for vector-adding the outputs of the above-mentioned two multiplication circuits 7a and 7b and outputting them.
The maximum likelihood sequence 9 is for determining whether the output vector phase of the vector adder 8 is closest to the phase shift that may be transmitted, and decoding the data in the signals received by the antennas 1a and 1b. The determination unit 10 is a bit synchronization circuit (BTR) that reproduces a clock of a transmitter (not shown) that has transmitted a reception signal.

Here, the antenna 1a is the first antenna,
The delay detection circuit 4a and the coordinate conversion circuit 5a are the first direction detecting means, and hereinafter, the envelope detection circuit 6a is the envelope detection means, the noise squelch circuit 11a is the noise squelch means, the addition circuit 12a is the noise removal means, and the multiplication. The circuit 7a is a first vector signal generating means, the vector adder 8 is a synthesizing means, and the maximum likelihood sequence judging section 9 is a judging means. The antenna 1b is the second antenna, and the output of the BPF 2b is transmitted to the subsequent circuit as a signal received by the second antenna. The differential detection circuit 4b and the coordinate conversion circuit 5b are second direction detection means, the multiplication circuit 7b is second vector signal generation means, and the noise squelch circuit 11b is second suppression means.

Next, the operation will be described. First, the operation of the 1-system will be described. The signal received by the antenna 1a, that is, the antenna input becomes a signal only in the reception band by passing through the BPF 2a, and further, by passing through the limiter amplifier 3a, becomes a signal whose amplitude is constant regardless of the magnitude of the received signal. Is output. The differential detection circuit 4a detects the phase shift Δθi between the symbols from the output signal of the limiter amplifier 3a and outputs the detected phase shift Δθi. This phase shift Δθi is the coordinate conversion circuit 5
It is converted into the form of the rectangular coordinate Xi + j · Yi at a and output to the multiplication circuit 7a as the first direction signal. Where Xi = cos (Δ
θi) and Yi = sin (Δθi).

On the other hand, the signal received by the antenna 1a is B
The signal is input to the envelope detection circuit 6a via the PF 2a, and the RSSI signal voltage Ri corresponding to the antenna input is output as the first magnitude signal. The characteristic of this RSSI voltage is shown in FIG. FIG. 2 shows the RSSI voltage R1i or R1j with respect to the antenna input level, that is, the level of the received signal of the antenna 1a or 1b.
Is a graph showing, when the antenna input level is low, due to the thermal noise generated in the diversity receiver,
Since the signal is not proportional to the antenna input, the signal is not sufficiently reliable.

The signal received by the antenna 1a is B
The noise squelch circuit 11a is also input via the PF 2a, and the noise squelch circuit 11a detects noise in the signal received by the antenna, that is, the above-mentioned thermal noise and the like.
FIG. 3 shows the noise squelch voltage R2i output by the noise squelch circuit 11a or 11b with respect to the antenna input level.
Or R2j. Here, the noise squelch circuit 11a
Outputs a signal corresponding to the ratio of thermal noise to the antenna input level, and when the antenna input level is low, the output of the noise squelch circuit 11a becomes high, and when the antenna input level is high, the noise squelch circuit 1
The output of 1a becomes low. The adder 12a obtains a voltage obtained by subtracting the noise squelch voltage R2i output from the noise squelch circuit 11a from the RSSI voltage R1i output from the envelope detection circuit 6a, that is, reliability information Ri. FIG. 4 is a graph showing the characteristic of the reliability information Ri or Rj with respect to the antenna input level. When the antenna input level is low, the thermal noise component is removed and the reliability information Ri or Rj proportional to the antenna input level is shown. Rj is obtained. Therefore, in the conventional diversity receiver that uses only the output of the envelope detector 6a, highly reliable reliability information Ri and Rj can be obtained even in a low antenna input level region where sufficient accuracy cannot be obtained. be able to. Therefore, errors in the determination result output by the maximum likelihood sequence determination unit 9 are reduced, and high quality communication can be realized.

In the multiplication circuit 7a, the reliability information Ri and
Output signal of the coordinate conversion circuit 5a, that is, Cartesian coordinates Xi + j · Y
It is multiplied by the signal of i and output as Ri · Xi + j · Ri · Yi. Two
In the system as well, the configuration of the two systems corresponding to each configuration of the first system operates in the same manner, and the multiplication circuit 7b outputs the same signal. At this time, the noise squelch circuit 11b operates similarly to the above noise squelch circuit 11a, and outputs highly reliable reliability information Rj even when the antenna input level is low. Then, the output signal Rj.Xj + j.Rj.Yj is output from the multiplication circuit 7b.

Next, the vector adder 8 outputs the signal Ri * Xi + j * Ri * Yi obtained from the 1-system multiplication circuit 7a and the signal Rj * Xj + j obtained from the 2-system multiplication circuit 7b.・ Vector addition of Rj and Yj. The result of this vector addition is shown in FIG. The result of this addition is input to the maximum likelihood sequence determination unit 9 and the BTR 10. As shown in FIG. 5, the maximum likelihood sequence determination section 9 determines the most probable phase shift that may be transmitted, demodulates the corresponding data, and outputs the demodulated data. Figure 5
Is an example in the case of four-level phase modulation represented by π / 4 shift QPSK, and the phase shift on the transmitting side is ± 1 / 4π,
There are four types of ± 3 / 4π. In the maximum likelihood sequence determination unit 9,
The transmitted data is demodulated by determining which of the four phase shifts the output vector of the vector adder 8 is closest to. Where signals Ri ・ Xi + j ・ Ri ・ Y
i and signals Rj, Xj + j, Rj, and Yj are antennas 1a and 1b, respectively.
Since it is a vector of a size that is more faithful to the antenna input level and the influence of thermal noise is suppressed, the determination result determined by the maximum likelihood system determination unit 9 also becomes stronger against thermal noise. Error rate is reduced. As described above, according to the first embodiment, since highly reliable reliability information can be obtained even when the antenna input is low, the diversity effect can be obtained in a wide range for the size of the antenna input. effective.

Example 2. FIG. 6 is a functional block diagram showing the diversity receiver according to the second embodiment. 6, the same reference numerals as those in FIG. 1 represent the same or corresponding parts. In the second embodiment, gain variable amplifiers 13a and 13b, which are third suppressing means, are added to the first embodiment to further improve the reliability of reliability information when the antenna input level is low. Is.

In FIG. 6, the variable gain amplifier 13a is
It is inserted between the envelope detection circuit 6a and the adder 12a. Then, as shown in FIG. 7, the noise squelch circuit 1
When the noise squelch voltage output by 1a is high, the RSSI voltage output by the envelope detection circuit 6a is amplified with a low gain. When the noise squelch voltage is low, the RSSI voltage output by the envelope detection circuit 6a is increased by a high gain. It is amplified by and output to the adder 12a. Variable gain amplifier 13
b is also similar to the variable gain amplifier 13a. Here, the variable gain amplifiers 13a and 13b strongly suppress the magnitude of the RSSI voltage output by the envelope detection circuit 6a when the noise squelch voltage is high, and the envelope detection circuit when the noise squelch voltage is low. The magnitude of the RSSI voltage output by 6a may be weakly suppressed or may not be suppressed and may be output to the adder 12a.

Next, the operation will be described. Antenna 1a
When the signal received by is input to the noise squelch circuit 11a as described in the first embodiment, the noise squelch circuit 11a detects noise in the signal received by the antenna 1a by the noise squelch circuit 11a. The noise squelch voltage output from the noise squelch circuit 11a is shown in FIG. FIG. 8 shows the noise squelch voltage for the antenna input and the variable gain amplifier 1 for the antenna input.
It is a graph which shows the gain of 3a or 13b.

This noise squelch voltage is input to the variable gain amplifier 13a as a signal for determining the gain.
The variable gain amplifier 13a amplifies the RSSI voltage of the envelope detector 6a with a gain based on this noise squelch voltage and outputs it to the adder 12a. The gain of the variable gain amplifier at this time is shown in FIG. Therefore, when the antenna input is low, the RSSI voltage is relatively low, and when the antenna input is high, the RSSI voltage is relatively high. Therefore, when the antenna input is low, the thermal noise component included in the RSSI voltage is large, and a voltage higher than the actual antenna input envelope is output. According to the variable gain amplifier 13a, the increased RSSI voltage is suppressed to a low value according to the noise level based on the noise squelch voltage of the noise squelch circuit 11a, so that a highly reliable voltage proportional to the antenna input, That is, highly reliable reliability information can be output to the addition circuit 12a.

The output voltage of the variable gain amplifier 13a is input to the adder 12a, the adder 12a operates as described in the first embodiment, and the maximum likelihood sequence determination section 9 finally outputs the data. 2 system variable gain amplifier 13b
It operates in the same manner as the 1-system variable gain amplifier 13a, and produces highly reliable reliability information. The diversity receiver of the second embodiment is characterized in that the variable gain amplifiers 13a and 13b can suppress the influence of thermal noise more strongly than the diversity receiver of the first embodiment. As described above, according to the second embodiment, since highly reliable reliability information can be obtained even when the antenna input is low, the diversity effect can be obtained in a wide range for the size of the antenna input. effective.

[0031]

Since the present invention is constructed as described above, it has the following effects.

First magnitude detecting means for detecting the magnitude of the signal received by the first antenna and outputting it as the first magnitude signal, and the magnitude of the signal received by the first antenna. Output from the first size detecting means
And a first direction detecting unit that detects the direction of the vector of the signal received by the first antenna and outputs the first direction signal. Second magnitude detecting means for detecting the magnitude of the signal received by the second antenna and outputting it as the second magnitude signal; and detecting the vector direction of the signal received by the second antenna, Second direction detecting means for outputting as a second direction signal, a first magnitude signal output by the first suppressing means, a first direction signal output by the first direction detecting means, the first direction signal A second magnitude signal output from the second magnitude detecting means and a signal synthesizing means that synthesizes the second direction signal output from the second direction detecting means .
Means for suppressing the noise of the signal received by the first antenna.
Noise squelch means for detecting
Removing the noise detected by the means from the first magnitude signal
Since the noise removal means for outputting is provided,
The effect of noise components contained in the signal can be minimized.
The diversity effect even when the antenna input is small.
You can get the fruit.

The signal synthesizing means produces a vector signal from the first magnitude signal output from the noise removing means and the first direction signal output from the first direction detecting means.
Vector signal generating means, and second vector signal generating means for generating a vector signal from the second magnitude signal output by the second suppressing means and the second direction signal output by the second direction detecting means. Noise included in the first magnitude signal, since the vector signal generated by the first vector signal generating means and the vector signal generated by the second vector signal generating means are combined. Since the influence of the component is reduced, the diversity effect can be obtained even when the antenna input is small.

Further, since the discrimination means for discriminating the data contained in the signals received by the first antenna and the second antenna based on the result of the combination by the combining means is provided, even if the antenna input is small, the diversity is obtained. The effect can be obtained.

Further, there is provided third suppressing means for suppressing and outputting the first magnitude signal outputted by the envelope detecting means on the basis of the noise detected by the noise squelch means, and the first vector signal generating means. Generates a vector signal from the first magnitude signal output from the third suppressing unit and the first direction signal output from the first direction detecting unit, and therefore, even when the antenna input is small, the diversity effect can be obtained. Obtainable.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a diversity receiver according to a first embodiment of the present invention.

FIG. 2 is a diagram showing output characteristics of the envelope detection circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing output characteristics of the noise squelch circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing reliability information characteristics output by the adder according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a method of estimating a phase shift of a received signal by performing vector synthesis according to the first embodiment of the present invention.

FIG. 6 is a functional block diagram of a diversity receiver according to the second embodiment of the present invention.

FIG. 7 is a diagram showing input / output characteristics of the variable gain amplifier according to the second embodiment of the present invention.

FIG. 8 is a diagram showing characteristics of antenna input vs. gain when the gain of the variable gain amplifier according to the second embodiment of the present invention is controlled by the noise squelch voltage.

FIG. 9 is a functional block diagram of a diversity receiver in the related art.

[Explanation of symbols]

1a, 1b antenna, 2a, 2b BPF, 3a,
3b limiter amplifier, 4a, 4b differential detection circuit,
5a, 5b coordinate conversion circuit, 6a, 6b envelope detection circuit, 7a, 7b multiplication circuit, 8 vector adder, 9 maximum likelihood sequence determination unit, 10-bit synchronization circuit, 11a, 11b noise squelch circuit 12a,
12b adder, 13a, 13b variable gain amplifier

Claims (4)

(57) [Claims] 1. A first magnitude detecting means for detecting a magnitude of a signal received by a first antenna and outputting the signal as a first magnitude signal, and a magnitude of a signal received by the first antenna. Based on the first magnitude signal output by the first magnitude detection means is suppressed, the first suppression means for outputting, and the direction of the vector of the signal received by the first antenna is detected, The first direction detecting means for outputting as the first direction signal and the second antenna for detecting the magnitude of the signal received by the second antenna,
A second magnitude detecting means for outputting as a magnitude signal, second direction detecting means for detecting a direction of a vector of a signal received by the second antenna, and outputting as a second direction signal, A first magnitude signal output by the first suppressing means, a first direction signal output by the first direction detecting means, a second magnitude signal output by the second magnitude detecting means, and And a signal synthesizing means for synthesizing the second direction signal output from the second direction detecting means , wherein the first suppressing means includes a signal which is received by the first antenna.
Noise squelch means to detect noise and this noise
Removes the noise detected by the latch means from the first magnitude signal
And a noise removing means for outputting the
Diversity receiver to do. 2. The signal synthesizing means generates a vector signal from the first magnitude signal output from the noise removing means and the first direction signal output from the first direction detecting means. A second vector signal generating means for generating a vector signal from the second magnitude signal output by the second suppressing means and the second direction signal output by the second direction detecting means; diversity receiver according to claim 1, characterized by comprising synthesizing means for synthesizing the vector signal vector signal and the second vector signal generating means is a vector signal generating means to generate generated, the. 3. Based on the combination result of the combining means, to claim 2, further comprising a determination means for determining data included in the received signal by the first antenna and the second antenna Diversity receiver described. 4. A first vector signal generating means, comprising a third suppressing means for suppressing and outputting the first magnitude signal outputted by the envelope detecting means on the basis of the noise detected by the noise squelch means. 4. The diversity according to claim 3 , wherein the vector signal is generated from the first magnitude signal output by the third suppressing unit and the first direction signal output by the first direction detecting unit. Receiving machine.