JPH01179425A - Mounting process of semiconductor chip - Google Patents

Mounting process of semiconductor chip

Info

Publication number
JPH01179425A
JPH01179425A JP135688A JP135688A JPH01179425A JP H01179425 A JPH01179425 A JP H01179425A JP 135688 A JP135688 A JP 135688A JP 135688 A JP135688 A JP 135688A JP H01179425 A JPH01179425 A JP H01179425A
Authority
JP
Japan
Prior art keywords
chip
pads
pad
semiconductor chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP135688A
Other languages
Japanese (ja)
Inventor
Takao Kagii
鍵井 孝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP135688A priority Critical patent/JPH01179425A/en
Publication of JPH01179425A publication Critical patent/JPH01179425A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

PURPOSE:To augment the alignment precision enabling the high density mounting process to be performed by a method wherein the semiconductor chip side pad is formed with the shape and space thereof specified smaller than those of the substrate side pad while the central positions of those pads are shifted from each other. CONSTITUTION:The shape and space of a semiconductor chip 11 side pad 12 are formed smaller than those of a substrate 13 side pad 14. The central positions of the pads 12 and 14 are shifted from each other. Reflow is effected in the state wherein the central line 16 of the pad 12 of chip 11 abuts against the other central line 17 of the pad 14 of substrate 13 making a fine shift of d in the long direction of respective pads 12, 14. At this time, the reflow in respective bumps stops on the central positions but when the pads 12, 14 are arranged at the position slightly distant from adjacent bumps making a shift in the opposite directions, two forces repel each other. Through these procedures, the alignment precision can be augmented enabling the high density amounting process to be performed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、IC等の半導体チップの実装方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting semiconductor chips such as ICs.

(従来の技術) 従来、半導体チップ、例えば、ICを基板へ接続する場
合には、パッケージ(D I P、チップキャリア、ピ
ングリッド等)によるものと、ペアチップで行われるワ
イヤボンディング、テープキャリア及びフリップチップ
ボンディングがある。
(Prior Art) Conventionally, when connecting a semiconductor chip, such as an IC, to a substrate, there are two methods: one using a package (DIP, chip carrier, pin grid, etc.), the other using wire bonding, tape carrier, and flip bonding performed on paired chips. There is chip bonding.

以下、ここではフリップチップボンディングについて説
明する。
Hereinafter, flip chip bonding will be explained here.

第4図はかかるフリップチップボンディングによる半導
体チップの実装状態を示す断面図である。
FIG. 4 is a sectional view showing a state in which a semiconductor chip is mounted by such flip-chip bonding.

図中、1は半導体(S+)チップ、2a、2bはこのチ
ップ1例のパッド、3は基板、4a、4bは基板3側の
パッド、5a、5bは溶融半田バンブである。
In the figure, 1 is a semiconductor (S+) chip, 2a and 2b are pads of one example of this chip, 3 is a substrate, 4a and 4b are pads on the substrate 3 side, and 5a and 5b are molten solder bumps.

このように、従来のフリップチップは、半導体チップ1
のボンディングバンド(主にAI金金属2a、  2b
にCr −Cuの金属を介して^Uを厚く付け、更に、
半球上に半田を形成する、所謂半田バンブを形成する。
In this way, the conventional flip chip
bonding bands (mainly AI gold metal 2a, 2b)
A thick layer of ^U is attached to the Cr-Cu metal, and further,
Solder is formed on the hemisphere, so-called solder bumps.

一方、チップを取り付けようとする基板側にも同様、導
体配線の一部にチップの半田バンブに対向する位置にバ
ンブの中心が合致するように半田バンプを形成する。
On the other hand, similarly, solder bumps are formed on a part of the conductor wiring on the side of the substrate to which the chip is to be attached so that the center of the bump coincides with the position opposite to the solder bump of the chip.

そして、基板側の半田バンプに、チップの半田バンプを
突き合わせて、加熱溶融(リフロー)すると、相互に溶
は合い溶融半田バンプ5a、5bが形成され、接続が行
われる。また、リフローにおいて、位置合わせは、更に
、精度が上がり、所謂セルフアライメント効果があられ
れている。
Then, when the solder bumps of the chip are brought into contact with the solder bumps on the substrate side and heated and melted (reflowed), they are melted together to form molten solder bumps 5a and 5b, thereby establishing a connection. Furthermore, in reflow, the precision of positioning has further improved, and a so-called self-alignment effect has been achieved.

このようにして、第4図に示されるように、半導体チッ
プの実装が行われる。
In this way, as shown in FIG. 4, the semiconductor chip is mounted.

(発明が解決しようとする問題点) しかしながら、上記した従来の半導体チップの実装にお
けるセルフアライメント効果は、バンプ位置はチップと
基板が共に中心が合致するように、図形上に既に決めら
れており、その位置決め精度は、特に基板側が厚膜配線
で形成される時、スクリーン印刷の平均的位置決め精度
に止まる。また、その精度はりフロー中に(頃きが生じ
た場合、更に、劣化することが考えられる。
(Problems to be Solved by the Invention) However, the self-alignment effect in the conventional semiconductor chip mounting described above is such that the bump positions are already determined on the figure so that the centers of both the chip and the substrate coincide. The positioning accuracy remains at the average positioning accuracy of screen printing, especially when the substrate side is formed of thick film wiring. In addition, if a fluctuation occurs during the flow, the accuracy may further deteriorate.

一方、今後の技術発展をみる時、バンドのピッチが60
〜100 μmと微細化される場合、現行のセルファラ
イン精度±50μm程度では不十分である。
On the other hand, when looking at future technological developments, the pitch of the band will be 60.
When miniaturizing to ~100 μm, the current self-line accuracy of about ±50 μm is insufficient.

本発明は、上記問題点を除去し、セルファラインの効果
を活用して、従来の厚膜印刷による方法を変えることな
く、位置決め精度の向上を図り、しかも、高密度実装が
可能な半導体チップの実装方法を提供することを目的と
する。
The present invention eliminates the above problems and utilizes the effect of Selfa Line to improve positioning accuracy without changing the conventional thick film printing method. The purpose is to provide an implementation method.

(問題点を解決するための手段) 本発明は、上記問題点を解決するために、フリップチッ
プ方式による半導体チップの実装方法において、半導体
チップ側のパッドの形状面積を基板側のパッドの形状面
積より小さく形成し、前記半導体チップ側のパッドと基
板側のパッドの中心位置を互いにずらして実装するよう
にしたものである。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a semiconductor chip mounting method using the flip-chip method, in which the shape area of the pads on the semiconductor chip side is replaced by the shape area of the pads on the substrate side. The semiconductor chip is formed smaller, and the pads on the semiconductor chip side and the pads on the substrate side are mounted with their center positions shifted from each other.

(作用) 本発明によれば、フリップチップ方式による半導体チッ
プの実装方法において、フリソプチ・71例の半田バン
プパターンを、基板の半田バンプパターンに比較して、
小さく形成し、かつ、基板のバンプ中心と5〜20μm
の微小ズレを作る。基板側のバンプはフリップチップ側
のバンプに比較して大きく形成し、長手方向には十分大
きいものとする。フリップチップと基板を突き合わせる
場合、ズレを起こさせる方向の中心線に沿って合わせる
(Function) According to the present invention, in the semiconductor chip mounting method using the flip-chip method, the solder bump pattern of Frisopti 71 is compared with the solder bump pattern of the board.
Form small and 5 to 20 μm from the center of the bump on the board.
Create a slight misalignment. The bumps on the substrate side are formed larger than the bumps on the flip chip side, and are sufficiently large in the longitudinal direction. When butting the flip chip and the board, align them along the center line in the direction that causes misalignment.

しかる後、リフローを行うと、溶解した半田の表面張力
の働きによって、チップ側のバンドと基板側のパッドは
相互に中心を合致させる方向に移動する。しかし、ここ
で、微小5〜20μmのズレが設定されているため、相
互の中心は合致することができない。このズレ量による
力がチップを一定方向に向かせることができる。従って
、2つの方向に力を生じるように、パッドの相互配列を
作ることによって、任意の方向にチップを固定すること
ができる。
After that, when reflow is performed, the band on the chip side and the pad on the substrate side move in a direction to align their centers with each other due to the surface tension of the melted solder. However, since a slight deviation of 5 to 20 μm is set here, the mutual centers cannot match. The force due to this amount of deviation can direct the chip in a certain direction. Therefore, the chip can be fixed in any direction by creating a mutual arrangement of pads that produces forces in two directions.

(実施例) 以下、本発明の実施例について図面を参照しながら詳細
に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の半導体チップのパッドの配置を示す平
面図であり、第2図は本発明の半導体チップの実装状態
を示す一部破断断面図である。
FIG. 1 is a plan view showing the arrangement of pads of the semiconductor chip of the present invention, and FIG. 2 is a partially cutaway sectional view showing the mounting state of the semiconductor chip of the present invention.

第2図に示すように、チップ11のパッド12の中心線
16と基板13のパッド14の中心i17は各パッドの
長手方向に微小ズレ△dを作って突き合わせた状態で、
リフローを行うと、第2図に示すように、バンプ15a
、15bが形成される。この場合、各バンプにおけるリ
フローの状態は、中心に停止するが、隣のバンプがある
距離離れたところに、ズレ量を反対方向に持つようにパ
ッド配設すると2つの力が反撥し合う。また、引き合う
方向に形成すると、釣り合った位置で停止し、バンプを
形成することができる。
As shown in FIG. 2, the center line 16 of the pad 12 of the chip 11 and the center i17 of the pad 14 of the substrate 13 are butted against each other with a slight deviation Δd in the longitudinal direction of each pad.
When reflow is performed, bumps 15a are formed as shown in FIG.
, 15b are formed. In this case, the reflow state of each bump stops at the center, but if a pad is arranged at a certain distance from the adjacent bump so that the amount of deviation is in the opposite direction, the two forces will repel each other. Furthermore, when formed in the direction of attraction, they can stop at a balanced position and form a bump.

第3図は多数のパッドを形成したチップに所望の力を作
用させて任意の方向へチップを固定する例を示す図であ
り、第3図(a)においては、チップ21に設けられる
多数のパッド218〜21pの中心は、基板のパッド(
図示なし)の中心との位置ズレの関係で、チップ21の
各パッドは矢印方向に引かれ、それらの合成力はチップ
21の横方向(右方向)に発生し、横方向に移動した位
置で固定される。第3図(b)においは、チップ22に
設けられる多数のバンド22a〜22pの中心は、基板
のパッド(図示なし)の中心との位置ズレの関係で、チ
ップ22の各パッドは矢印方向に引かれ、各パッドはチ
ップ22の中心に求心的に集中し、チップ22はバラン
スがとれて移動することなく固定される。第3図(C)
においては、チップ23に設けられる多数のパッド23
a〜23pの中心は、基板のパッド(図示なし)の中心
との位置ズレの関係で、チップ23の各パッドは矢印方
向に引かれ、各パッドはチップ23の中心から放射状に
向かう方向に引かれ、チップ23はバランスがとれて移
動することなく固定される。第3図(d)においては、
チップ24に設けられる多数のパッド24a〜24pの
中心は、基板のパッド(図示なし)の中心との位置ズレ
の関係で、チップ24の各パッドは矢印方向に引かれ、
パッド24a乃至24d、パッド24e乃至24h、バ
ッド24i乃至24i1バッド24m乃至24pのそれ
ぞれのグループは矢印のように異なった方向に引かれ、
その合成力により、チップ24は回転方向に移動した位
置で固定される。
FIG. 3 is a diagram showing an example of fixing a chip in an arbitrary direction by applying a desired force to a chip on which a large number of pads are formed. The centers of the pads 218 to 21p are located at the pads (
Due to the positional deviation from the center of the chip 21 (not shown), each pad of the chip 21 is pulled in the direction of the arrow, and their combined force is generated in the lateral direction (rightward direction) of the chip 21, and at the position moved in the lateral direction. Fixed. In FIG. 3(b), the centers of the many bands 22a to 22p provided on the chip 22 are misaligned with the centers of the pads (not shown) on the substrate, and each pad of the chip 22 is moved in the direction of the arrow. As a result, each pad is centered centripetally at the center of the chip 22, and the chip 22 is balanced and fixed without movement. Figure 3 (C)
, a large number of pads 23 provided on the chip 23
The centers of a to 23p are misaligned with the centers of pads (not shown) on the substrate, so each pad of the chip 23 is pulled in the direction of the arrow, and each pad is pulled in a direction radial from the center of the chip 23. As a result, the chip 23 is balanced and fixed without movement. In Figure 3(d),
The centers of the many pads 24a to 24p provided on the chip 24 are misaligned with the centers of pads (not shown) on the substrate, so each pad on the chip 24 is pulled in the direction of the arrow.
Each group of pads 24a to 24d, pads 24e to 24h, pads 24i to 24i1, pads 24m to 24p are pulled in different directions as shown by arrows,
Due to the resultant force, the chip 24 is fixed at the position moved in the rotational direction.

上記実施例においては、パッドの形状は長方形の例を示
したが、例えば、円形や楕円形を用いても同様の効果が
得られる。
In the above embodiment, the shape of the pad is rectangular, but the same effect can be obtained by using a circular or oval shape, for example.

なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。
Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(発明の効果) 以上、詳細に説明したように、本発明によれば、チップ
側のパッドの形状より基板側のパッドの形状を大きくす
ることができ、基板側に形成するパターンの微細化への
厳しい要求を回避することができる。結局、基板側のパ
ッド面積が数倍大きいにもかかわらず、アライメント精
度は、セルフアライメント効果と全く同一である。
(Effects of the Invention) As described above in detail, according to the present invention, the shape of the pad on the substrate side can be made larger than the shape of the pad on the chip side, which contributes to miniaturization of the pattern formed on the substrate side. strict requirements can be avoided. After all, even though the pad area on the substrate side is several times larger, the alignment accuracy is exactly the same as the self-alignment effect.

また、製造に際しては、スクリーン印刷によるパターン
形成を行うことができ、通常のホトリソ技術を用いる場
合も、ドライフィルムなど10〜30μmの解像を有す
る感光材料を利用することができ、コストを低減するこ
とができる。
In addition, during manufacturing, patterns can be formed by screen printing, and even when using normal photolithography technology, photosensitive materials with a resolution of 10 to 30 μm such as dry film can be used, reducing costs. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体チップのパッドの配置を示す平
面図、第2図は本発明の半導体チップの実装状態を示す
一部破断断面図、第3図は多数のパッドを形成したチッ
プに力を作用させチップを任意の位置に固定させる例を
示す図、第4図は従来の半導体チップの実装状態を示す
一部破断断面図である。 11、21.22.23.24=・・チップ、12.2
1 a 〜2i p 。 22a〜22p、23a〜231)、24a〜24p・
・・チップのバンド、13・・・基板、14・・・基板
のパッド、15a、15b・・・バンプ。 特許出願人 沖電気工業株式会社
FIG. 1 is a plan view showing the arrangement of pads of a semiconductor chip of the present invention, FIG. 2 is a partially cutaway cross-sectional view showing the mounting state of the semiconductor chip of the present invention, and FIG. FIG. 4 is a partially cutaway cross-sectional view showing a state in which a conventional semiconductor chip is mounted. 11, 21.22.23.24=...chip, 12.2
1a to 2ip. 22a-22p, 23a-231), 24a-24p・
... Band of chip, 13... Board, 14... Pad of board, 15a, 15b... Bump. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】  フリツプチップ方式による半導体チップの実装方法に
おいて、 (a)半導体チップ側のパッドの形状面積を基板側のパ
ッドの形状面積より小さく形成し、 (b)前記半導体チップ側のパッドと基板側のパッドの
中心位置を互いにずらして実装するようにしたことを特
徴とする半導体チップの実装方法。
[Claims] In a semiconductor chip mounting method using a flip-chip method, (a) the shape area of a pad on the semiconductor chip side is formed to be smaller than the shape area of a pad on the substrate side, and (b) the shape area of the pad on the semiconductor chip side is A method for mounting a semiconductor chip, characterized in that the center positions of pads on a substrate are shifted from each other.
JP135688A 1988-01-08 1988-01-08 Mounting process of semiconductor chip Pending JPH01179425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP135688A JPH01179425A (en) 1988-01-08 1988-01-08 Mounting process of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP135688A JPH01179425A (en) 1988-01-08 1988-01-08 Mounting process of semiconductor chip

Publications (1)

Publication Number Publication Date
JPH01179425A true JPH01179425A (en) 1989-07-17

Family

ID=11499214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP135688A Pending JPH01179425A (en) 1988-01-08 1988-01-08 Mounting process of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH01179425A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170548A (en) * 1988-12-23 1990-07-02 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
CN103066053A (en) * 2011-10-18 2013-04-24 台湾积体电路制造股份有限公司 Connector structures of integrated circuits

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170548A (en) * 1988-12-23 1990-07-02 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
CN103066053A (en) * 2011-10-18 2013-04-24 台湾积体电路制造股份有限公司 Connector structures of integrated circuits
US9373598B2 (en) 2011-10-18 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits
US9659903B2 (en) 2011-10-18 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing connector structures of integrated circuits
US9991218B2 (en) 2011-10-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits

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