JPS6049638A - Construction of electronic parts - Google Patents

Construction of electronic parts

Info

Publication number
JPS6049638A
JPS6049638A JP15674783A JP15674783A JPS6049638A JP S6049638 A JPS6049638 A JP S6049638A JP 15674783 A JP15674783 A JP 15674783A JP 15674783 A JP15674783 A JP 15674783A JP S6049638 A JPS6049638 A JP S6049638A
Authority
JP
Japan
Prior art keywords
bonding
terminals
lsi
parts
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15674783A
Other languages
Japanese (ja)
Inventor
Kazuhito Ozawa
小沢　一仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP15674783A priority Critical patent/JPS6049638A/en
Publication of JPS6049638A publication Critical patent/JPS6049638A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To attain rapidly positioning of an electronic parts by a method wherein spherical bumps are formed to the bonding terminals of an LSI, and pin holes are formed to a corresponding wiring substrate. CONSTITUTION:Recess shapes 15 are formed previously at the bonding positions of wiring terminals 13. To form the shapes thereof, after the terminals 13 are formed, an etching mask is covered thereon, and windows are opened in a pin hole type in the mask only at the parts corresponding to the bonding positions. Etching is performed, and semispherical recess parts 15 are formed only at the parts opened with the windows according to half etching. The bumps 12 of an LSI11 formed in a semispherical type are positioned to be bonded to the terminals 13 formed in such a way.

Description

【発明の詳細な説明】 く技術分野〉 本発明はＬＳｉを回路配線基板にフリップチップボンデ
ィングして成る電子部品の構成方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method of constructing an electronic component by flip-chip bonding an LSi to a circuit wiring board.

〈従来技術〉　・ 従来は第１図に示すように、（Ａ）の状態にＬＳｉｌと
配線端子３を離した位置でｆＢｌの様に位置合わせを光
学的に行ない、（Ｃ１のようにボンディングする。なお
、図に於て、２はバンプ、４は基材である。<Prior art> - Conventionally, as shown in Fig. 1, positioning is optically performed as fBl at a position where the LSil and wiring terminal 3 are separated from each other in the state (A), and bonding is performed as shown in C1. In the figure, 2 is a bump and 4 is a base material.

ＬＳｉと配線基板端子との位置合わせは、複雑な装置を
使えば、自動的に位置合わせを行なうことも可能である
が、非常に高価な装置を必要とし装置の帆風性も問題に
なる。Although it is possible to automatically align the LSi and the wiring board terminals by using a complicated device, this requires a very expensive device and there is a problem in the performance of the device.

〈発明の目的〉 本発明は、そういった装置を用いずに簡単な光学装置を
使って位置精度と位置合わせスピードを向上させようと
したものである。<Objective of the Invention> The present invention attempts to improve position accuracy and alignment speed by using a simple optical device without using such a device.

〈発明の概要〉 すなわち、第２図（Ａ＋に示す様に、バンプ１２の凸形
状に合わせて回路基板上の配線端子１３に凹部１５を設
けることにより、位置合せ精度の許容差を大きくする。<Summary of the Invention> That is, as shown in FIG. 2 (A+), by providing a recess 15 in the wiring terminal 13 on the circuit board in accordance with the convex shape of the bump 12, the tolerance of alignment accuracy is increased.

これにより、簡単な操作で位置合わせすることができ、
場合によってはチップ毎に位置合せする必要を無くし、
自動的に位置合せすることを可能とする。This allows for easy alignment,
In some cases, eliminating the need to align each chip,
Allows for automatic alignment.

〈実施例〉 本発明は、第２図（Ａｌに示すように、あらかじめ配線
端子１３のボンディング位置に凹部形態１５を作る。こ
の作り方は第１図（Ａｌの３のように配線端子を形成し
た後、エツチングマスクをかぶせ、ボンディング位置に
相当する部分のみピンホール状にマスクに窓開けを行な
う。これをエツチングして窓開けされた部分のみハーフ
エツチングで半円球状に凹部１５を形成する。このよう
にして作られた配線端子にＬＳｉｌｌの半円球状に形成
されたバンプ１２（普通円盤状に半田メッキを施しリフ
ローして半田を溶融させることにより半田バンプとして
形成できる）を位置合わせし、第２図（Ｃ１のようにボ
ンディングする。なお、図に於て、１４は基材である。<Example> In the present invention, as shown in Fig. 2 (Al), a recessed part 15 is made in advance at the bonding position of the wiring terminal 13. After that, an etching mask is placed on the mask, and a window is opened in the mask in the form of a pinhole only in the portion corresponding to the bonding position.This is etched, and only the opened portion is half-etched to form a concave portion 15 in the shape of a semicircle. The semicircular bumps 12 of the LSill (usually can be formed as solder bumps by applying solder plating to a disk shape and reflowing the solder to melt the solder) are aligned with the wiring terminals made in this way. Bonding is performed as shown in Figure 2 (C1). In the figure, 14 is the base material.

凹部を形成するためのエツチング方法は湿式エツチング
或いはスパッタエツチング法を用いることができる。As the etching method for forming the recesses, wet etching or sputter etching can be used.

〈効　果〉 以」二詳細に説明したように、本発明によれば、以下の
各効果を奏する、きわめて有用な電子部品の構成方法を
得ることができるものである。<Effects> As described in detail below, according to the present invention, it is possible to obtain an extremely useful method of configuring electronic components that exhibits the following effects.

１、ＬＳｉと配線基板とのボンディング位置合わせを作
業者がマニュアルで光学的に行なう場合、配線基板端子
のボンディング位置がピンホールとして表わされるため
、位置合わせの迅速化をはかることができる。1. When an operator optically performs the bonding alignment between the LSi and the wiring board manually, the bonding position of the wiring board terminal is represented as a pinhole, so the alignment can be speeded up.

２・　ＬＳｉバンプの凸部と配線基板の凹部とのボンデ
ィングにより位置ずれがなくなり、作業者がマニュアル
で位置合わせを行なった場合の位置のバラツキが吸収さ
れる。2. Bonding between the protrusions of the LSi bumps and the recesses of the wiring board eliminates positional deviations, and the positional variations that occur when an operator performs manual alignment are absorbed.

３、ＬＳｉバンプと配線基板端子との接着面積が広くな
り、ボンディング部分の接着強度が向上し、信頼性が向
上する。3. The bonding area between the LSi bump and the wiring board terminal is increased, the bonding strength of the bonding portion is improved, and reliability is improved.

４、余裕のある広いピッチの場合には、これら凹凸部を
大きく設けて、ＬＳｉを配線基板上にある程度粗雑に配
置してから、適切な振動条件をＬＳｉに与えて凹凸部の
かん合として、精密自動位置合わせを行なうことができ
る。4. In the case of a wide pitch with plenty of room, these uneven parts are made large, the LSi is arranged somewhat roughly on the wiring board, and then appropriate vibration conditions are applied to the LSi to connect the uneven parts. Precise automatic positioning can be performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａｌ　、　ｆＢｌ　、　（Ｃ１は従来方法の説
明ζこ供する図、第２図（Ａｌ　、　ｆＢｌ　、　（Ｃ
１は本発明の一実施例の説明に供する図である。 符号の説明 １１：ＬＳｉ、１２：バンプ、１３：配線端子、１４：
基材、１５：凹部。 代理人　弁理士　福　士　愛　彦（他２名）第１図Figure 1 (Al, fBl, (C1) provides an explanation of the conventional method; Figure 2 (Al, fBl, (C
1 is a diagram for explaining one embodiment of the present invention. Explanation of symbols 11: LSi, 12: Bump, 13: Wiring terminal, 14:
Base material, 15: recess. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1

Claims (1)

【特許請求の範囲】[Claims] １、ＬＳｉを回路配線基板にフリップチップボンディン
グする際に、ＬＳｉのボンディング端子に、それぞれ略
円すい状の丸型バンプを構成しそれに対応する配線基板
の回路上には同一形状のピンホールを構成し、これらＬ
Ｓｉの丸型バンプと配線基板のピンホールとを位置合わ
せしてボンディングすることを特徴とする電子部品の構
成方法。1. When flip-chip bonding an LSi to a circuit wiring board, approximately conical round bumps are formed on the bonding terminals of the LSi, and pinholes of the same shape are formed on the corresponding circuits of the wiring board. , these L
A method for configuring an electronic component, which comprises aligning and bonding Si round bumps and pinholes on a wiring board.
JP15674783A 1983-08-26 1983-08-26 Construction of electronic parts Pending JPS6049638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15674783A JPS6049638A (en) 1983-08-26 1983-08-26 Construction of electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15674783A JPS6049638A (en) 1983-08-26 1983-08-26 Construction of electronic parts

Publications (1)

Publication Number Publication Date
JPS6049638A true JPS6049638A (en) 1985-03-18

Family

ID=15634427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15674783A Pending JPS6049638A (en) 1983-08-26 1983-08-26 Construction of electronic parts

Country Status (1)

Country Link
JP (1) JPS6049638A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5168346A (en) * 1989-08-28 1992-12-01 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5363277A (en) * 1991-12-20 1994-11-08 Rohm Co., Ltd. Structure and method for mounting semiconductor device
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
EP1391922A2 (en) * 2002-08-21 2004-02-25 Seiko Epson Corporation Semiconductor device mounting method, semiconductor device mounting structure, electro optical device, electro-optical device manufacturing method and electronic device
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5168346A (en) * 1989-08-28 1992-12-01 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5347162A (en) * 1989-08-28 1994-09-13 Lsi Logic Corporation Preformed planar structures employing embedded conductors
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5410805A (en) * 1989-08-28 1995-05-02 Lsi Logic Corporation Method and apparatus for isolation of flux materials in "flip-chip" manufacturing
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5363277A (en) * 1991-12-20 1994-11-08 Rohm Co., Ltd. Structure and method for mounting semiconductor device
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6452260B1 (en) 1997-09-02 2002-09-17 Silicon Light Machines Electrical interface to integrated circuit device having high density I/O count
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
EP1391922A2 (en) * 2002-08-21 2004-02-25 Seiko Epson Corporation Semiconductor device mounting method, semiconductor device mounting structure, electro optical device, electro-optical device manufacturing method and electronic device
EP1391922A3 (en) * 2002-08-21 2006-04-19 Seiko Epson Corporation Semiconductor device mounting method, semiconductor device mounting structure, electro optical device, electro-optical device manufacturing method and electronic device
US7180196B2 (en) 2002-08-21 2007-02-20 Seiko Epson Corporation Semiconductor device mounting method, semiconductor device mounting structure, electro-optical device, electro-optical device manufacturing method and electronic device
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

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