JPH01179291A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize construction where an image processing system is simplified by performing the generation and control of an address in the inside of a device with respect to readout from a serial port to read out storage data synchronizing with the raster scan of a CRT. CONSTITUTION:It is essential to read out serial data output 15 successively in synchronism with the raster scan timing of the CRT. Therefore, it is also essential to perform parallel data transfer from a storage part 1 to a serial register 2 successively at a constant cycle at the time of completing serial readout. The cycle is equivalent to (n) serial clocks, and a transfer timing can be controlled by the output of an n-ary counter 3. Also, since it is enough to increase the row address of the storage part 1 which performs the parallel data transfer sequentially corresponding to the raster scan, it is possible to set the output of an m-ary counter 4 as the address, and a selection circuit 5 is switched by a data transfer signal DT that is the output of the counter 3, and the output of the counter 4 is supplied to the storage part 1 as a row address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and in particular,
The present invention relates to a technology that is effective for use in dual baud (Dual Baud) RAM for image processing.

Conventional technology RAM for image processing that displays figures, characters, etc. on the screen of a CRT (cathode ray tube) is, for example, as described in "Nikkei Electronics JP 195-P219" published by Nikkei McGraw-Hill on June 20, 1986. To, the third
A dual port RAM shown in the figure is known. In FIG. 3, 3o is a data storage section having a memory cell array of m rows and n columns. 31 is any 1 in the data storage unit 1
This is a serial register for reading out the captured data serially by capturing row storage data in parallel and sequentially transferring it to the serial clock 38. 32 to 37 are signals for random ports, respectively address, data, RAS, CAS, DTlo.
E, WB/WE signal.

In this way, by having a serial port that can read serial data in addition to the random port, C
Pixel data can be easily read out in synchronization with the RT rask scan timing. FIG. 4 shows the timing at which data in an arbitrary row of a memory cell array of m rows and n columns is transferred in parallel to the serial register 31. At the falling edge of the RAS signal (f), the data transmission signal D
T10E(h) is set to LOW to set the transfer mode, and the row address A I ((J) to be transferred is given.

By transferring data at the rising edge of the transfer signal DT10E, a serial data output (j) is obtained as a continuous signal in synchronization with the serial clock (i).

Address A2 is the row address in the next cycle.

Problem to be Solved by the Invention Serial data output must be read out in synchronization with the rask scan timing of CI%T. Therefore, when configuring an image processing system using such a dual port RAM, the serial A circuit that generates a parallel data transfer signal D T 10 E every n clocks (a circuit that generates a transfer row address in synchronization with parallel data transfer) ζ Writes from a random port during parallel data transfer. Complicated external circuits such as stop circuits are required, and the system becomes enormous. In order to obtain a continuous orange serial output, strict timing regulations are imposed on the relationship between the parallel data transfer signal DT10E and the serial clock (Figure 4, 2.12), and a highly accurate signal is required. be done.

Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and counts the serial clock by an n-ary counter to generate a parallel data transfer signal DT. T f: Counts with an m-ary counter, generates a row address to be transmitted from the data storage section, switches the address signal from the address input terminal and the output signal of the m-ary counter with the data transfer signal DT, and also outputs the data transfer signal DT. The configuration is such that it outputs to the outside and controls writing and reading from the random boat.

Function: With the above-described configuration, the present invention generates and controls addresses within the multi-port RAM for reading data from a serial port that continuously reads stored data in synchronization with the CRT rask scan timing. Therefore, the external circuit is simple and an image processing system can be realized with a simple configuration.

Embodiment FIG. 1 shows a block diagram of a semiconductor memory device according to an embodiment of the present invention. Reference numeral 1 denotes a data storage section having a memory cell array of m rows and n columns. Reference numeral 2 designates a serial register for reading the stored data of any one row of the data storage unit 1 in parallel, sequentially transferring it using the serial clock 13, and serially reading out the taken data. ing. 3 is an n-ary counter that counts the serial clock 13, and 4 is an m-ary counter that counts the output of the n-ary counter 3. Here, the serial data output 16 must be read out continuously in synchronization with the CRT rask scan timing. Therefore, the parallel data transfer from the data storage unit 1 to the serial register 2 must also be performed continuously at a constant cycle JtJ] at the time when the serial readout of the serial register 2 is completed. This period corresponds to n serial clocks, and the transfer timing can be controlled by the output J of the n-ary counter 3. In addition, the row address of the data storage unit that performs parallel transfer can be sequentially increased according to the last scan of the CRT, so the output of the m-ary counter 4 can be used as the address, so the output of the n-ary counter 3 can be used as the address. The selection circuit 6 is switched by the data transfer signal DT, and the output of the m-adic counter 4 is applied to the data storage section as a row address.

FIG. 2 is a diagram showing the timing of parallel data transfer. A reset signal terminal 14 is connected to the n-ary counter 3 and the m-ary counter 4, and is reset by a signal synchronized with the vertical signal of the CRT.

7 The data transfer signal DT shown in (C) is obtained by counting the real clock (d) with the n-ary counter 3.
As the address signal (b) to the data storage unit 1, the selection circuit 6 provides the output signal A1 of the m-ary counter 4 in synchronization with the falling edge of the RAS signal (a) during parallel data transfer, and In the cycle , a signal from the address input terminal 6 is applied.

As a result, a continuous signal synchronized with the CRT rask scan timing is read out from the serial data output (e) as shown in the figure.

The data transfer signal D T (c) from the n-ary counter 3 is applied to the data storage section 1 via the AND gate 16, and only the OE multiplied signal needs to be applied from the random port. Further, the data transmission signal DT is outputted to the output terminal 12, and writing and reading of the circundum port can be controlled by this signal.

Effects of the Invention By having the above-described configuration, the present invention generates a parallel data transfer signal, a transfer row address signal, and a transmission control signal within the dual port RAM for serial data reading synchronized with the rask scan timing of the CRT. This simplifies the external circuit and eliminates the need for input signals that require timing accuracy, making it possible to realize an image processing system with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a timing diagram of the device, and FIG.
The figure is a block diagram of a conventional semiconductor memory device, and FIG. 4 is a timing explanatory diagram of the conventional device. 1...Data storage unit, 2...Serial register, 3...n [counter, 4...
・m-ary counter, 5...selection circuit, 13...
... Serial clock, 15 ... Serial data output. Name of agent: Patent attorney Toshio Nakao et al. 16th
1 Figure 3--7
1 Dori Unta Figure 2 (2) Ordinary 1 (bl A+
AZ (c+ -7 (revised) 3rd r3 f Figure 4

Claims (1)

[Claims] A semiconductor memory device having a data storage section consisting of a memory cell array arranged in m rows and n columns, a serial register for serial reading, and an address input signal and a data input signal for writing and reading from a random port. an n-ary counter that counts the serial clock; an m-ary counter that counts the output of the n-ary counter; and one of the address input signal and the output of the m-ary counter depending on the output signal of the n-ary counter. What is claimed is: 1. A semiconductor memory device comprising: a selection circuit for selecting an n-ary counter; and an output terminal for outputting an output signal of the n-ary counter to the outside.