JPH03222184A - Asic for video ram - Google Patents

Abstract

PURPOSE:To increase access speed, and simultaneously, to attain miniaturization by reducing an occupied area at time of fitting by installing an address generator in the inside. CONSTITUTION:The address generator 3 generates the selection signal of a line/row on a memory cell 6 at the timing of a clock signal CLK in conformity to an access ready signal from an arbiter 5, and sends it to an address comparator 4 and the memory cell 6. Besides, a status code STC to show an operating state is outputted from the generator 3 to the outside. The comparator 4 compares the address signal generated by the generator 3 with address data ADD, and when the both coincide with each other, it sends a coincidence detection signal to a decoder 1 and the arbiter 5. Thus, the access speed is not restricted by the driving timing of an address bus, and access is speeded up, and the miniaturization can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a video RAM display device used in image display devices such as televisions, personal computers, and displays for EWS (engineering work stations).

[Conventional technology]

In a conventional VRAM that exclusively stores image data, when accessing image data, an externally connected CPU or an external circuit replacing the CPU generates address designation signals one by one and supplies them to an address bus.

[Problem to be solved by the invention]

Therefore, the access speed of the VRAM is limited by the drive timing of the address bus, which has been an obstacle to increasing the speed.

Furthermore, conventional VRAMs have had disadvantages such as complicated wiring for driving CPtJ connections, which increases the occupied area and goes against the trend of miniaturization.

Therefore, the present invention has been made to solve the above-mentioned problems, and its purpose is to increase the access speed, reduce the area occupied at the time of installation, and make it possible to downsize the video. The objective is to provide a memory block for RAM.

[Means to solve the problem]

To achieve the above object, the present invention provides a dual-port memory, an address input pin, a sequential access data input/output pin, a random access data input/output pin, a sequential access read/write signal input pin, , a random access read/write signal input pin, and an address generator that generates an address signal for accessing the dual-port memory based on address data input from the address input pin; When a read/write signal is input from the read/write signal input pin, the memory cell in the dual-port memory corresponding to the address specified by the address generator and the sequential access
A sequential access circuit that reads/writes sequential access data between data input/output pins, and when a read/write signal is input from the random access read/write signal input pin, input from the address input pin. a random access circuit that reads/writes random access data between a memory cell in the dual-port memory specified by the external address specified by the external address and the random access data input/output pin; It features an arbiter that arbitrates access timing in the event of duplicate accesses, an internal address generator that enables data access without the use of external circuits or CPUs, and a monolithic structure. shall be.

[For production]

According to the present invention, the address generator generates an address signal for accessing the dual-port memory based on address data input from the address input pin. Sequential access read/
When a read or write signal is input from the write signal input pin, the sequential access circuit
Reads or writes sequential access data between the memory cell in the dual-port memory corresponding to the address specified by the generator and the sequential access data input/output pin. Similarly, when a read or write signal is input from the random access read/write signal input pin, the random access circuit selects the dual port signal corresponding to the address specified by the external address input from the address input pin.
Read or write random access data between memory cells in memory and random access data input/output pins. Furthermore, when accesses to the dual port overlap to the same address, the arbiter adjusts the timing by delaying one access timing.

〔Example〕 Next, embodiments of the present invention will be described based on the drawings.

The drawing is a block diagram showing the configuration of a video RAM NICK according to the present invention, in which a decoder 1 inputs address data input from an address input pin (ADD) to a memory cell 6 according to a coincidence detection signal from an address comparator 7. A selection signal for the upper row and column is generated and sent to the memory cell 6. Here address input pin (AD
D) is an address for random access.

The access timing generator generates a predetermined access timing signal based on the clock signal input from the clock input pin (CLK), and
Send to cell 6.

Address generator 3 has a clock input pin (CL
According to the access ready signal from the arbiter 5 at the timing of the clock signal input from the memory cell 6
Upper row and column selection signals are generated and sent to address comparator 4 and memory cell 6.

Further, the address generator 3 outputs a 2-bit status code indicating the operating state from the status code output pin (STC) to the outside.

Address comparator 4 connects the address signal generated by address generator 3 and the address input pin (AD
D) is compared with the address data input from D), and if the two match, a match detection signal is sent to the decoder 1 and the arbiter 5.

At the timing of the input clock signal, the arbiter 5
Sequential access write signal input pin (WE
-A), random access enable input pin (R
ND), the input signal from the random access read/write signal input pin (R/WE-B) is determined, and when the random access enable input signal is enabled during sequential access, the address comparator outputs the random access signal. The address input from the address input pin for access is compared with the address automatically generated from the internal address generator, and if the addresses match, an access ready signal is sent to the address input pin.
It is output to the generator 3, I10 controller 7, and access ready signal output pin (ACC-RDY).

Memory cell 6 is a dual-port type DRAM
According to the timing signal from the access timing generator 2, the address designated by the decoder 1 and the address generator 3 is accessed, and data is read or written to/from the I10 controller 7.

■/○ The controller 7 has a built-in buffer that temporarily stores access data, and according to the access ready signal from the arbiter 5, the controller 7 connects the memory cell 6, external pins, sequential access data output pins (D, ・A>, Sequential access data input pin (DI・A), random access data input/output pin (DIlo-B)
) to exchange access data. Note that if the sequential access write and random access write overlap with respect to the memory cell 6, one of the data is transferred to the I10 controller 7.
Once stored in the buffer, write processing is performed at the next timing.

Note that the horizontal and vertical synchronization signals input to the address generator 3 via the horizontal synchronization signal input pin (H3YC) and vertical synchronization signal input pin (YSYC) are synchronized when reading the image data in the memory cell 6. This eliminates jitter that occurs on the display screen, allowing you to obtain clear images.

In addition, an enable signal that enables operation is input from the chip enable signal input pin (CE), and a memory clear signal is input from the memory clear signal input pin (CLR) to clear the stored data all at once. A signal is input.

With the above configuration, the input signal of the random access enable input pin (RND) is turned OFF.
(L level), only sequential access is performed, and when the sequential access write signal input pin (WE-A) is ON (L level), it is written to 0.
It becomes a lead at FF (H level). The input signal of the random access enable input pin (RND) is ON (
H level), both sequential and random access are possible, and random access read/
When the write signal input pin (R/WE-B) is at L level, it is write, and when it is H level, it is read.

In addition, the address /
Since a generator is installed, there is an external C for address generation.
There is no need for a PU or an external circuit to replace it, and image data can be written and read by the video NIC by itself, making it possible to reduce the area occupied when attached to an image display device.

Furthermore, by incorporating an address generator, the data access speed can be set to high speed.

〔Effect of the invention〕

As described above, in the present invention, by providing an internal address generator, an external CPU for generating addresses is provided.
Alternatively, an address signal corresponding to a predetermined area of the display screen is generated, and image data in the memory can be accessed without providing a replacement external circuit.

In addition, by making the video RAM memory chip monolithic and configuring it as a single chip, it is possible to reduce the size.
Furthermore, since the number of connected buses is reduced, the number of output pins can be reduced to facilitate the wiring process, and a low-cost image display device can be provided.

[Brief explanation of drawings]

The figure is a block diagram showing the internal structure of a video RAM NICK according to the present invention. 1...Decoder 2...Access timing generator 3...Address generator 4...
・Address comparator 5...Arbiter 6...
・Memory cell...I10 controller RND
... Random access enable input pin ADD ... Address input pin D0・A ...
- Sequential access data output pins D, -A... Sequential access data input pin DIlo-B... Random access data input/output pin WE-A... Sequential access write signal input pin R/WE-B...Random access read/write signal input pin

Claims (1)

[Claims] (1) Dual port memory, address input pin, sequential access data input/output pin, random access data input/output pin, sequential access read/write signal input pin, and random access read/write signal input an address generator that generates an address signal for accessing the dual-port memory based on the address data input from the address input pin, and a read/write signal input from the sequential access read/write signal input pin. When a write signal is input, sequential access data is read between the memory cell in the dual port memory corresponding to the address specified by the address generator and the sequential access data input/output pin. When a read/write signal is input from the sequential access circuit to write and the above random access read/write signal input pin, the data in the dual port memory specified by the external address input from the address input pin is A random access circuit that reads/writes random access data between the memory cell and the random access data input/output pin, and arbitrates access timing when accesses to the dual port memory overlap. ASIC for video RAM is characterized by being equipped with an arbiter and an internal address generator to enable data access without using an external circuit or CPU, and having a monolithic structure as a whole.