JP2003005948A - Display controller and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the deterioration of a plotting access speed from a CPU to a display memory due to access from a display control circuit to the display memory, and to maximize the performance of the plotting access from the CPU. SOLUTION: A CPU I/F 11, a plotting control circuit 12, a display control circuit 13, a panel I/F 14, a VRAM memory access arbitrating circuit 17, a VRAM 18, a display timing control circuit 19, a CPU bus arbitrating circuit 15, and a display control setting circuit 16 are integrated on one semiconductor chip, and the CPU I/F 11 outputs a bus release request signal 101 to a CPU 2 in response to an access request from the display control circuit 13 to the VRAM 18 without requesting any additional time or clock to the bus access to the CPU 2, and performs the memory access to the VRAM 18 for display while approving the bus release at the time of receiving a bus release approval signal 102 from the CPU 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display device which are used in a display unit of, for example, an information device and which access a display memory from a CPU (central processing unit) at high speed.

[0002]

2. Description of the Related Art Conventionally, as a method of constructing a display device,
Two methods have been implemented: a dedicated display memory method in which a main memory and a display memory are realized by separate memory devices, and a unified memory method in which a main memory and a display memory are realized by a single memory device.

3A and 3B are block diagrams showing a main structure of a conventional display device. FIG. 3A is a block diagram of a dedicated display memory system, and FIG. 3B is a block diagram of a unified memory system.

In the dedicated display memory system, as shown in FIG. 3A, basically, the access right to the display memory (hereinafter referred to as VRAM) is held by the display control circuit (hereinafter referred to as LCDC) and the CPU When accessing the VRAM for drawing, arbitration is performed when the display memory access from the LCDC and the display memory access from the CPU via the LCDC coincide with each other.
There is a method of giving priority to the display memory access from DC, or a method of giving priority to the display memory access for which an access request is generated earlier in time. Depending on the access timing, it is common practice to generate a wait signal (Wait) for the CPU to add a CPU bus cycle. This technology is
-32390 gazette "video RAM writing control device" and Japanese Patent Publication No. 3-74415 "video RAM access method" and the like are widely adopted.

In the unified memory system, the CPU has an LC
This is a method often used in LSI systems with a built-in DC, and the RAM of the main memory usually has the access right of the CPU, and the bus is released in response to the bus access request from the LCDC. The LCDC reads display data from the area of the display memory (VRAM) in the main memory space and sends the display data to the display panel (LCD PANEL). If the RAM of the main memory has sufficient capacity, the LCDC as a whole. There are advantages in terms of cost and mounting area. Incidentally, JP-A-8-28700
In Japanese Unexamined Patent Publication No. 1 "Display Circuit", as a unified memory system, as shown in FIG. 3B, a case where a CPU and an LCDC are configured by different devices is shown.

[0006]

In the conventional dedicated display memory system described above, when the CPU accesses the VRAM through the LCDC for drawing access, if the display memory access from the LCDC for display coincides with the timing. , L
There is a problem that it takes a long time for one bus access due to a wait signal (Wait) output from the CDC to the CPU.

In addition, an EDO DRAM (Extended Datum) that can be accessed at high speed in memory access from the CPU
ta Out Dynamic RAM) interface and SDRAM (Sync
The hronous Dynamic RAM) interface cannot accept an additional wait signal (Wait), and since it is connected by the SRAM interface, there is also a problem that the number of access cycles per one time inevitably increases.

In order to solve these problems, there is a technique in which a CPU interface circuit is provided with a multi-stage buffer to reduce the frequency of outputting a wait signal (Wait), but there is a technique to deal with it. The higher the speed, the less effective even with multiple buffers. Further, there is a device that does not output a standby signal (Wait) by providing a delay reading mechanism, but the maximum frequency of the bus clock is limited because of the delay reading. This limits the minimum display memory access time.

On the other hand, in the unified memory system, since the RAM of the main memory usually requires a large capacity,
Drawing control circuit and display control circuit (LCD including RAM)
C) cannot be integrated on one semiconductor chip.
For this reason, an external standard SRAM (Static R
AM), EDO DRAM, SDRAM, etc. are used. Therefore, the width of the data signal of the display memory is
The width of the data signal of the RAM of the main memory is the same as the width of the data signal of the RAM of the main memory. For example, the CPU data bus is 32
In the case of bits, the width of the data bus of the RAM of the main memory is selected from 8 bits, 16 bits and 32 bits.

When the data bus width of the display memory is 32 bits, the display screen size is 320 × 240, the number of colors that can be expressed by one pixel is 65,536 colors, and the number of frames per second of the display screen is 60, one second The number of times the display memory is accessed is (320 × 240 × 16 × 60) ÷ 32 =
2,304,000 times. The number of times increases as the screen size increases and the number of color representations of one pixel increases, and there is a problem that the access performance of the RAM of the main memory decreases and the current consumption increases.

The present invention has been made in view of the above circumstances, and minimizes the speed reduction at the time of drawing access from the CPU to the display memory due to the access from the display control circuit to the display memory, and at the same time, from the CPU. An object of the present invention is to provide a display control device and a display device capable of maximizing the performance of drawing access of the display device.

[0012]

A display control device according to the present invention includes a memory access from a data processing means for processing display data to a display storage means via a drawing control means for memory control, and a display means. Bus control means for switching between display access means and memory access to the display storage means for displaying on the display control means is provided, and the display data of the display storage means read by the display control means is output to the display means. In the display control device for performing the above, the drawing interface means between the information processing means and the display storage means via the drawing control means is SDRAM (Synchronous Dynamic R).
AM) interface, and at least the drawing interface means, the bus control means, the drawing control means, the display control means and the display storage means are the same in order to make the data bus width of the display storage means larger than the data bus width of the information processing means. Integrated on a semiconductor chip, this bus control means
A bus release request signal is output from the display control means to the display storage means in response to an access request to the display storage means, and a bus release approval signal is received from the information processing means. There, the above object is achieved thereby.

Further, the display device of the present invention comprises an information processing means for processing the display data, a display means for displaying the display data, a display storage means for storing the display data, and a display data from the information processing means. Drawing control means for controlling writing of the display data to the display storage means and reading of display data from the display storage means, drawing interface means for interfacing between the information processing means and the drawing control means, and display data from the display storage means. Display control means for reading, panel interface means for interfacing between the display control means and the display means, memory access control for controlling access from the drawing control means to the display storage means and access from the display control means to the display storage means Means and a bus release request signal to the information processing means, and a bus release approval signal from the information processing means. A display device having a bus arbitration means for taking only these drawing interface means, drawing control means, display control means, a panel interface unit,
The memory access control means, the display storage means, and the bus arbitration means are integrated into one semiconductor chip, and the drawing interface means is provided by the display control means without requiring additional time or clock for bus access of the information processing means. In response to an access request to the display storage means, the bus arbitration means outputs a bus release request signal to the information processing means, and the bus arbitration means receives the bus release approval signal from the information processing means. The memory access for display is performed to the storage means, and the above-mentioned object is achieved thereby.

With this configuration, the display control device including the drawing control means and the display control means and the display storage means have been separated from each other in the past, but by integrating these into one semiconductor chip, information can be obtained as in the conventional case. The data bus width of the display storage means can be increased without being limited by the width of the data signal on the processing means side. Therefore, it is possible to reduce the number of times the display control unit accesses the display storage unit, and at the same time, reduce the power consumption when the display memory is accessed to the display storage unit. Further, when the display storage means is accessed from the information processing means, the bus is opened in the information processing means, and the direct connection between the information processing means and the display storage means is operated in synchronization with the system bus clock to transfer data. SDR that can reduce waiting time
It becomes possible to use the AM interface, high-speed memory processing becomes possible, and the bus occupancy rate of the information processing means can be reduced by increasing the data bus width of the display storage means as described above. Becomes As described above, in the memory access to the display storage means of the information processing means, the display storage means is connected to the SDRAM interface that cannot accept an additional wait cycle by an external signal, so that performance and power consumption are reduced. Is also an advantageous display control device. Therefore, the performance of the drawing access from the information processing means to the display storage means is minimized while the speed decrease at the time of the drawing access from the information processing means to the display storage means due to the access from the display control means to the display storage means is minimized. Can be maximized, improving system performance.

Further, preferably, in the display control device or the display device of the present invention, there is provided a display control setting means for setting an operation mode of the entire display control, and the display control setting means is configured such that the information processing means processes information. The bus release request signal from the bus control means is enabled during the period, and the bus release request signal from the bus control means is disabled when the information processing means is not processing information.

With this configuration, when the information processing means does not read or write to the display storage means, it does not request the bus access right to the information processing means, so that the information processing means simply performs arithmetic processing for drawing and other arithmetic operations. System bus access performance degradation due to bus release during processing is eliminated. This makes it possible to further improve the performance of the entire system.

Further, preferably, in the display control device or the display device of the present invention, a display timing control means for performing timing control of the entire display control is provided, and the information processing means is not in the process of information processing, and the bus control means operates. When the bus release request signal is invalid, the display timing control unit controls at least the operation clocks of the display control unit and the display storage unit to be switched to a frequency low enough for the operation.

With this configuration, when the information processing means does not read or write to the display storage means, the clock frequency can be switched so that the display control means, the display storage means, etc. are operated at a frequency as low as necessary and sufficient. For example, when the system is performing only the display operation, it is possible to reduce the power consumption.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments 1 to 3 in the case where a display device of the present invention is applied to a display section of an information device will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a basic configuration of an information device provided with a display device according to Embodiment 1 of the present invention. In FIG. 1, a display device of an information device includes a liquid crystal display controller 1 (hereinafter referred to as LCDC1) as a display control device that performs display control, display data drawing processing (drawing calculation, etc.), and other calculation processing. CPU 2 as an information processing means for performing the information processing of, and a liquid crystal display panel 3 as a display means for displaying the display data (hereinafter referred to as L
A CD panel 3), a control program such as a calculation program, and a RAM 4 and a ROM 5 as main storage means for storing various data necessary for the control program.
Although not specifically shown in FIG. 1, various I / O devices are also provided as a matter of course.

The LCDC 1 includes a CPU I / F 11 as drawing interface means, a drawing control circuit 12 as drawing control means, and a display control circuit 1 as display control means.
3 and panel 1 / F as panel interface means
14 and a CPU bus arbitration circuit 15 as bus arbitration means
And a display control setting circuit 16 as display control setting means.
And a VRAM access arbitration circuit 17 as a memory access control unit, a VRAM 18 as a display storage unit (display memory), and a display timing control circuit 19 as a display timing control unit, which are the same semiconductor chip. Accumulated on top.

The CPU I / F 11 serves as an interface between the CPU 2 and the drawing control circuit 12. C
The PUI / F11 allows the CPU2 to access the bus without requiring additional time or clock for the CPU2.
Using the high-speed SDRAM interface function of
The display memory (VRAM 18) in the DC 1 can be accessed.

The drawing control circuit 12 receives the access signal input from the CPU I / F 11 and controls the drawing / writing of the VRAM 18. That is, the drawing control circuit 12 controls writing of display data from the CPU 2 to the VRAM 18 and reading of display data from the VRAM 18.

The display control circuit 13 reads the display data from the VRAM 18 and transfers the read display data to the panel 1 / F14.

The panel 1 / F 14 serves as an interface between the display control circuit 13 and the LCD panel 3.

When the display control circuit 13 requests access to the VRAM 18, the CPU bus arbitration circuit 15 gives the CPU 2 a bus release request signal 101 so that the display control circuit 13 can obtain an access right necessary for reading display data from the VRAM 18. (Hereinafter referred to as BREQ101) is output,
Bus release approval signal 102 from CPU2 (hereinafter referred to as BACK1
02) is received, V
Display control circuit 1 by instructing RAM access arbitration circuit 17
The bus is opened to the third side, and the display control circuit 13 is instructed to access the VRAM 18 from the memory.

The display control setting circuit 16 is for setting the operation modes of various display controls of the LCDC1. The operation modes include, for example, a single access mode and a page access mode.

The VRAM access arbitration circuit 17 performs read / write access from the drawing control circuit 12 to the VRAM 18.
It arbitrates the read access from the display control circuit 13 to the VRAM 18. The VRAM access arbitration circuit 17 and the CPU bus arbitration circuit 15 constitute a bus control means.

The VRAM 18 stores display data.

The display timing control circuit 19 generates a timing clock and controls the timing of the entire LCDC 1 based on the timing clock.

The types of memory access from the CPU 2 will be described below.

The general-purpose CPU 2 of recent years usually supports various types of memory interfaces, and RO
M interface, SRAM interface, EDO
It corresponds to a DRAM interface, an SDRAM interface, and the like.

In the case of the ROM interface and the SRAM interface, they are interfaced by a chip select signal, an address signal, a data signal, a read command signal or a write command signal, and in the minimum case, they can be accessed by two clocks of the bus clock, Higher frequencies require additional weights, for example a bus clock of 30 MHz,
And the access time of SRAM is 100 nSec,
3 clocks are required for additional weight, totaling 5
Become a clock.

In case of EDO DRAM interface,
Interfaced by row address strobe signal, column address signal, address signal, data signal, read / write status signal, single access mode (mode to read / write one data in one access)
Sometimes, like ROM and SRAM, it requires a total of 5 clocks, but page access mode (1
In the mode of reading and writing multiple consecutive data in one access), the second and subsequent accesses are
High-speed access with 2 clocks can be realized.

In the case of the SDRAM interface, a chip select signal, a row address command signal, a column address command signal, an address signal, a data signal, a write command signal, a data input / output mask signal, a bus clock, a bus clock enable signal are used for the interface, and a single signal is used. In access mode, ROM or SRA
As with M, it requires a total of 5 clocks, but in the page access mode, the second and subsequent accesses are 1
Higher speed access of 1 clock per data can be realized.

The SDRAM is compatible with 100 MHz and 133 MHz, and in portable information equipment,
Usually, the bus clock is often used at 100 MHz or less, so that even if the bus clock becomes high speed, 1 data / 1 clock can be realized. However, S of CPU
Since the DRAM interface is based on the assumption that the SDRAM is externally connected, if the SDRAM interface is used, no additional wait can be accepted during access.

In the first embodiment, as described above, the CPU
The purpose is to enable access to the display memory (VRAM18) in the LCDC1 by using the high-speed SDRAM interface function of the CPU2 with respect to the I / F11. It will be described in detail below with reference to FIG.

In the first embodiment, the CPU 2 and the LCDC 1
The bus width of the data bus signal between and is 16 bits,
Further, since the VRAM 18 is built in the LCDC 1, the bus width can be widened, and the bus width will be described as 256 bits. Since the LCD panel 3 displays 65536 colors, red (R), green (G), and blue (B) each require 6 bits, so the data bus width of the LCD panel 3 is 18 bits.

First, the case where the CPU 2 does not access the VRAM 18 and only the display operation on the LCD panel 3 is performed will be described.

The resolution displayed on the LCD panel 3 is 320.
(Horizontal) × 240 (vertical), including the blanking period, the number is 360 × 242, the number of colors to be expressed is 65536 colors (16 bits), and the number of frames per second is 6
When it is set to 0, the bus width of the VRAM 18 is 256 bits. Therefore, the number of times the display control circuit 13 accesses the VRAM 18 = 360 × 242 × 16 × 60/256 = 32
6,700 times. That is, 1/326700 = 3.0
An access request is generated once in 6 μSec, and its timing clock is generated by the display timing control circuit 19.
This is transmitted to the CPU bus arbitration circuit 15.

The CPU bus arbitration circuit 15 outputs the bus release request BREQ 101 to the CPU 2. On the other hand, the CPU 2 immediately sends a CP to the bus release approval BACK 102 after the end of the bus access cycle at that time.
It returns to the U bus arbitration circuit 15. CPU bus arbitration circuit 1
5 receives the BACK 102, instructs the VRAM access arbitration circuit 17 to send the VRAM from the drawing control circuit 12.
An access signal to 18 is sent from the display control circuit 13 to VRA.
The access signal to M18 is switched to, and then the display control circuit 13 is instructed to read the display data of the VRAM 18.

The display control circuit 13 has VRAMs 18 to 25
When the reading of the 6-bit display data is completed, the read completion information is transmitted to the CPU bus arbitration circuit 15, and the CPU bus arbitration circuit 15 deactivates the BREQ101 signal, and C
PU2 is B because BREQ101 became inactive
The ACK signal is deactivated and the display control circuit 13 ends the bus release.

The display control circuit 13 has a VRAM 18
The display data of 256 bits read out from is delivered to the panel 1 / F14 in 16-bit units. Panel 1 / F14
Is insufficient for 16-bit display data, 2
Data is output to the LCD panel 3 by adding bits.

In the above, the display control circuit 13 uses the VRAM1.
Although the display data read from 8 at a time is 256 bits, if the continuous reading is efficient, for example, when the VRAM 18 is the SDRAM, if page mode is used, only one clock is added to obtain continuous data. Since the data can be read out quickly, the bus occupation rate of the CPU 2 can be further reduced.

The display memory (VRA) described above with reference to FIG.
The actual timing waveform to M18) is shown, and the part A shown by the broken line corresponds to it.

Next, a case where the CPU 2 accesses the VRAM 18 will be described. At this time, the CPU 2
The width of the data bus connecting the LCDC1 and the LCDC1 is 16
Described as a bit.

The CPU 2 accesses the VRAM 18 as an SDRAM. Therefore, chip select signal 1
03 (hereinafter referred to as CS103), row address strobe command signal 104 (hereinafter referred to as RAS104), column address strobe command signal 105 (hereinafter referred to as CA).
S105), data input / output mask signal 106 (hereinafter DQM 106), clock signal 107 (hereinafter C)
LK107), clock enable signal 108
(Hereinafter referred to as CKE108), write enable signal 1
09 (hereinafter referred to as WE109), address bus signal 11
Data is transferred by each signal of 0 (hereinafter referred to as ADDRESS 110) and a data bus signal 111 (hereinafter referred to as DATAI 11).

When the CPU 2 reads the display data from the VRAM 18, the CPU 2 first outputs "Low" (active) to the CS 103 in synchronization with the CLK 107,
The RAS 104, the CAS 105, and other signals are made ready to be received.

Next, RAS104 is set to "Low", CAS
105 for "High", WE09 for "High", A
The "bank address" and the "row address" are output to the DDRESS 110, and a bank active command for activating a desired bank and row address line is issued.

Next, RAS104 is set to "High", CA.
Sl 05 is “Low”, WE 09 is “High”, A
The “column address” is output to the DDRESS 110, and a read command for reading data from the desired column address is issued.

The CPU I / F 11 transfers these signals to the drawing control circuit 12, and the VRAM access arbitration circuit 17
To the VRAM 18 via.

In the VRAM 18, the CAS latency is 2
In the case of 2, the data is output two clocks after CLK107 after the read command is received, and DATA111 is output to the CPU2 via the VRAM access arbitration circuit 17, the drawing control circuit 12, and the CPU I / F11.

At this time, the drawing control circuit 12 uses the VRAM.
ADDRESSl10 at the time of read command for 18
Since 256 bits including the 16-bit data of the column address designated by are accessed at a time, the data designated by the column address is selected from the 256 bits and returned to the CPU I / F 11.

When the read access from the CPU 2 to the VRAM 18 is a single access, the read is completed by this, and CS103 is set to "High" (inactive).

When the read access from the CPU 2 is burst access, A
A read command in which only the “column address” of DDRESS 110 is changed is issued again. However, the column address at this time must be an address included in 256 bits including the first data.

The drawing control circuit 12 has a data holding means for holding the first read 256-bit data, selects the data of the column address designated by the second read command, and selects the CPUI / Return to F11.

Further, when reading is repeated, the above read command is repeated, and finally CS103 is set to "Hi".
gh ”(inactive) to end the read access.

Next, when the CPU 2 writes display data to the VRAM 18, the CPU 2 first outputs "Low" (active) to the CS 103 in synchronization with the CLK signal 107, and outputs the RAS 104, CAS 105 and other signals. Put it in a state where it can be accepted.

RAS104 is "Low", CAS105
Is "High", WEL09 is "High", ADDR
"Bank address" and "row address" in ESS110
Is output and a bank active command for activating a desired bank and row address line is issued.

RAS104 is "High", CAS10
5 is "Low", WE09 is "Low", ADDRE
The "column address" is output to SS110, and a write command for writing data to a desired column address is issued. At the same time, data for writing to DATA111 is set.

The CPU I / F 11 transfers these signals to the drawing control circuit 12, and the VRAM access arbitration circuit 17
To the VRAM 18 via. The VRAM 18 is
When receiving the write command, fetch the data. At this time,
Data other than the column address for writing should not be rewritten.

When the write access from the CPU 2 is a single access, the write is completed by this, and CS103
To "High" (inactive). When the write access from the CPU 2 is a burst access, the write command in which only the “column address” of the ADDRESS 110 is changed is issued again following the above-mentioned write command. However, the column address at this time must be an address included in 256 bits including the first data.

Further, when the write is repeated, the above write command is repeated, and finally CS103 is set to "Hi".
gh ”(inactive) to end the write access.

FIG. 2 shows an actual timing waveform from the CPU 2 to the display memory (VRAM 18) described above, and a portion B shown by a solid line corresponds to it.

As described above, according to the first embodiment, by integrating at least the VRAM 18, the drawing control circuit 12 and the display control circuit 13 in one semiconductor chip, it is possible to reduce the power consumption at the time of accessing the display memory and to reduce the VR.
The data bus width of the AM 18 can be significantly increased. As a result, VRA by the display control circuit 13
It is possible to reduce the number of times M18 is accessed,
As a result, it is possible to reduce the performance deterioration in the drawing access from the CPU 2 and further reduce the power consumption during the display memory access. In addition to this, VRAM1 is added to the SDRAM interface that cannot accept an additional wait cycle by an external signal.
Since 8 can be connected, it is possible to provide a display control device which is more advantageous in terms of performance and power consumption.

In the first embodiment, when the drawing control circuit 12 writes data in the VRAM 18,
The write control circuit 12 temporarily latches the write data,
It goes without saying that there is a means of writing the data into the VRAM 18 when the 256-bit data is prepared, or writing into the VRAM 18 when the end of the write command is detected. (Second Embodiment) In the second embodiment, the CPU bus arbitration circuit 15 is controlled according to the setting of the display control setting circuit 16 in the first embodiment, and the bus is released from the CPU bus arbitration circuit 15 to the CPU 2. The request BREQ 101 is switched between valid and invalid, and its realization method is as follows.
When BREQ101 is a negative logic (active “Low”), it is always “High” by being gated by an OR gate, or by fixing the preset terminal of the flip-flop making BREQ101 to “Low”, A method of fixing the BREQ 101 at “High” can be considered.

By invalidating the BREQ 101 and simultaneously allowing the VRAM access arbitration circuit 17 to always accept the access from the display control circuit 13,
Although the PU2 cannot access for reading and writing, when accessing the VRAM 18 from the display control circuit 13, it is not necessary to issue a bus release request to the CPU 2, so that the bus efficiency is not lowered.

As described above, according to the second embodiment, the CP
When U2 does not read or write to VRAM 18, C
Since the bus access right request signal to the PU2 is not issued, the performance of the system bus access due to the release of the bus is simply reduced while the CPU2 is performing the arithmetic processing for drawing and other arithmetic processing. Therefore, the performance of the entire system can be further improved. (Third Embodiment) In the third embodiment, the CPU bus arbitration circuit 15 is controlled according to the setting of the display control setting circuit 16 in the second embodiment, and the bus is released from the CPU bus arbitration circuit 15 to the CPU 2. With the BREQ 101 for request switched to invalid, the display timing control circuit 19
On the other hand, the clock of the display system is switched to the minimum frequency necessary for display, and the frequency is determined by the display screen size, color depth, frame frequency and the like.

Actually, not only the case where the dedicated oscillator circuit is provided but also the case where the bus clock or the memory clock is divided can be considered, so that it may not be completely optimum.

As described above, according to the third embodiment, the CP
When the U2 does not read or write to the VRAM 18, the display control circuit 13, the VRAM 18, etc. can be operated at a clock frequency as low as necessary and sufficient for operation, so that when the system is performing only the display operation. Can reduce power consumption as much as the clock frequency is lowered.

[0070]

As described above, according to the present invention, the speed reduction at the time of drawing access from the information processing means to the display storage means by the access from the display control means to the display storage means is minimized. The performance of drawing access from the information processing means to the display storage means can be maximized, and the system performance can be improved.

Further, when the information processing means does not read or write to the display storage means, it does not request the bus access right to the information processing means, so that the information processing means simply performs the arithmetic processing for drawing and other arithmetic processing. System bus access performance will not be degraded due to bus release during the operation. Therefore, the performance of the entire system can be further improved.

Furthermore, when the information processing means does not read or write to the display storage means, the frequency is switched so that the display control means, the display storage means, etc. are operated at a frequency that is necessary and sufficiently low. Power consumption can be reduced when only the operation is performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an information device provided with a display device according to a first embodiment of the present invention.

FIG. 2 is an output waveform diagram showing access timing of each control signal between the CPU and LCDC of FIG.

FIG. 3 is a block diagram showing a main part configuration of a conventional display device, in which (a) is a block diagram of a dedicated display memory system,
(B) is a block diagram of a unified memory system.

[Explanation of symbols]

1 LCD controller 2 CPU 3 Liquid crystal display panel 4 Main memory (RAM) 5 Main memory (ROM) 11 CPU I / F circuit 12 Drawing control circuit 13 Display control circuit 14 panel I / F circuit 15 CPU bus arbitration circuit 16 Display control setting circuit 17 VRAM access arbitration circuit 18 VRAM (display memory) 19 Display timing control circuit 101 Bus release request signal 102 Bus release approval signal 103 Chip select signal 104 Row address strobe signal 105 Column address strobe signal 106 data mask signal 107 clock signal 108 Clock enable signal 109 Write enable signal 110 address bus signal 111 Data bus signal

Claims (4)

[Claims] 1. A memory access from an information processing means for processing display data to a display storage means via a drawing control means for memory control, and the display from the display control means for displaying on the display means. In a display control device, which is provided with a bus control means for controlling switching between memory access to a storage means and outputs display data of the display storage means read by the display control means to the display means to perform display control, The drawing interface means between the information processing means and the display storage means via the drawing control means is SDRAM (Synchro
nous Dynamic RAM) interface, and at least the drawing interface means, the bus control means, the drawing control means, the display control means and the display control means for making the data bus width of the display storage means larger than the data bus width of the information processing means. Display storage means is integrated on the same semiconductor chip, and the bus control means outputs a bus release request signal to the information processing means in response to an access request from the display control means to the display storage means. The display control device for opening the bus to the display control means during the bus release approval that receives the bus release approval signal. 2. A display control setting means for setting an operation mode of the entire display control, wherein the display control setting means receives a bus release request signal from the bus control means while the information processing means is processing information. The display control device according to claim 1, wherein the display control device is enabled, and the bus release request signal from the bus control means is disabled when the information processing means is not processing information. 3. A display timing control means for controlling the timing of the entire display control is provided, wherein the information processing means is not processing information and the bus release request signal from the bus control means is invalid. 3. The display control device according to claim 2, wherein the display timing control means controls the operation clocks of at least the display control means and the display storage means so as to switch to a frequency low enough for operation. 4. Information processing means for processing information of display data, display means for displaying the display data, display storage means for storing the display data, and display storage of the display data from the information processing means. Drawing control means for controlling writing to the means and reading of display data from the display storage means,
Drawing interface means for interfacing between the information processing means and the drawing control means, display control means for reading display data from the display storage means, panel interface means for interfacing the display control means with the display means, Memory access control means for controlling access from the drawing control means to the display storage means and access from the display control means to the display storage means, and a bus release request signal to the information processing means to output the information. A display device having a bus arbitration means for receiving a bus release approval signal from a processing means, the drawing interface means, drawing control means, display control means, panel interface means, memory access control means, display storage means and bus arbitration Means are integrated on one semiconductor chip, and the drawing interface means is the information processing means. A bus release request signal is output from the bus arbitration means to the information processing means in response to an access request from the display control means to the display storage means without requesting additional time or clock for bus access by the processing means. A display device in which the bus arbitration means performs memory access for display from the display control means to the display storage means during bus release approval receiving the bus release approval signal from the information processing means.