JPH01176921U - - Google Patents

Info

Publication number
JPH01176921U
JPH01176921U JP7356288U JP7356288U JPH01176921U JP H01176921 U JPH01176921 U JP H01176921U JP 7356288 U JP7356288 U JP 7356288U JP 7356288 U JP7356288 U JP 7356288U JP H01176921 U JPH01176921 U JP H01176921U
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
semiconductor integrated
recognition information
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7356288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7356288U priority Critical patent/JPH01176921U/ja
Publication of JPH01176921U publication Critical patent/JPH01176921U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の半導体ウエハーの平面図、第
2図は第1図の部分拡大図、第3図は従来例の半
導体ウエハーの平面図、第4図および第5図はチ
ツプ上に位置認識情報を付与する実現手段例であ
る。 第1図:1……半導体ウエハー、2……半導体
集積回路チツプ、3……チツプダイシング線、4
……位置認識情報、第2図:5……半導体集積回
路チツプ、6……チツプ切り出し線、7……位置
認識情報、第3図:8……半導体ウエハー、9…
…半導体集積回路チツプ、10……チツプダイシ
ング線、第4図:11……ボンデイングパツド開
孔用パターン、12……位置認識情報を示すマス
クパターン、第5図:13……マスクパターン、
14……液晶表示部。
Fig. 1 is a plan view of a semiconductor wafer of the present invention, Fig. 2 is a partially enlarged view of Fig. 1, Fig. 3 is a plan view of a conventional semiconductor wafer, and Figs. This is an example of an implementation means for adding recognition information. Figure 1: 1... Semiconductor wafer, 2... Semiconductor integrated circuit chip, 3... Chip dicing line, 4
...Position recognition information, Fig. 2: 5...Semiconductor integrated circuit chip, 6...Chip cutting line, 7...Position recognition information, Fig. 3: 8...Semiconductor wafer, 9...
...Semiconductor integrated circuit chip, 10... Chip dicing line, Fig. 4: 11... Pattern for bonding pad opening, 12... Mask pattern showing position recognition information, Fig. 5: 13... Mask pattern,
14...Liquid crystal display section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路チツプ上に半導体ウエハーでの
チツプ位置を示す認識情報を有することを特徴と
する半導体集積回路。
A semiconductor integrated circuit characterized in that the semiconductor integrated circuit chip has recognition information indicating the position of the chip on a semiconductor wafer.
JP7356288U 1988-06-01 1988-06-01 Pending JPH01176921U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7356288U JPH01176921U (en) 1988-06-01 1988-06-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7356288U JPH01176921U (en) 1988-06-01 1988-06-01

Publications (1)

Publication Number Publication Date
JPH01176921U true JPH01176921U (en) 1989-12-18

Family

ID=31298699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7356288U Pending JPH01176921U (en) 1988-06-01 1988-06-01

Country Status (1)

Country Link
JP (1) JPH01176921U (en)

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