JPH01175319A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain the coincidence of switching timing and to eliminate the waveform distortion of an output logic signal by adding a dummy FET and making a circuit into a symmetric structure. CONSTITUTION:The title circuit has plural circuits with a power source 41 common and plural circuits 31a-31c are switched in accordance with the combination of input logic signals D1 and D2. A current is supplied to the power source 41 through the switched circuit and a voltage generated at the load resistance of the switched circuit is outputted as the output logic signal. These plural circuits 31a-31c are respectively equipped with plural steps of FETs 34, 37 and 38 connected in series, the circuit is made a logic circuit in which the number of steps of FETs of at least one circuit is smaller than the number of steps of the other circuits, a dummy FET 35 is added in series to this circuit, the number of steps is made to coincide with the number of steps of the other circuits and when it is switched to the circuit to which the dummy FET 35 is added, the dummy FET is on-operated. Thus, the coincidence of the switching timing can be attained and the waveform distortion of the output logic signal can be eliminated.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figure 2.3) Problems to be Solved by the Invention (Figure 4) Implementation of Means and Actions to Solve the Problems Example One embodiment of the present invention (Fig. 1) Effects of the invention [Summary] Regarding logic circuits, especially 5CFL, the purpose of eliminating waveform distortion of output logic signals is to combine multiple circuits with a common current source. Switches the plurality of circuits according to the combination of input logic signals, causes current to flow into the current source through the switched circuit, and outputs the voltage generated in the load resistance of the switched circuit as an output logic signal. In the logic circuit, each of the plurality of circuits includes a plurality of stages of FETs connected in series, and the number of stages of FETs in at least one circuit is smaller than the number of stages of the other circuit. Among multiple circuits,
A gummy FET is added in series to a circuit with a small number of FET stages to match the number of stages in other circuits, and when the circuit is switched to a circuit with a gummy FET added, the gummy FET is turned on. .

[Industrial application field]

The present invention relates to logic circuits, and in particular to SCF L (Source Coup
This invention relates to a logic circuit intended to stabilize circuit operation.

In recent years, the processing speed of computers has been further increased by reducing the number of clock cycles per instruction or increasing the clock frequency. For this reason,
Electronic devices such as transistors that constitute the arithmetic unit of a computer are required to operate at higher speeds. Generally, electronic devices using compound semiconductors such as GaAs (
For example, a GaAs FET (GaAs FET) has an electron mobility that is about 6 times higher than that using Si. GaA
Of the logic circuits configured with s FETs, S CF L corresponds to the ECL of a Si bipolar transistor.
(Source Coupled F E T L
ologic) is a current switching type and high speed,
It has various features such as being compatible with ECL, and is seen as a promising logic circuit for constructing super-fast integrated circuits.

[Conventional technology]

Figure 2.3 shows a two-man power A constructed with a conventional 5CFL.
An example of ND is shown. In FIG. 2, a circuit 1 made up of 5CFLs has two input logic signals D2 and two input buffer sofa gates 2.3 and an AND gate circuit 4. , , and D2 are both logic "1", the output logic signal OUT is output as logic "1". Note that at this time, OUT becomes logic "0".

The input buffer sofa gate 2.3 uses each of the input logic signals A, D2 as complementary signals, shifts the level to a predetermined potential, and outputs the signal. For example, the input buffer gate 2 uses the input logic signal D1 as a complementary signal, shifts the level to the X potential, and
+xs DI In addition, X
The relationship is potential>X potential.

FIG. 3 is a diagram showing a specific configuration of the AND gate circuit 4. Note that in the following description, GaAs FET will be simply referred to as FET.

In FIG. 3, the AND gate circuit 4 includes one FET
5 and a load resistor 6 connected in series,
A second circuit 11 in which two FETs 8.9 and a load resistor 10 are connected in series, a circuit (n) in which this FET 8.21 and a load resistor 6 are connected in series, and the first circuit 7
It is configured to include an FET 12 that functions as a common current source for the second circuit 11 and the third circuit (n), and an output section 13. However, the load resistance 6 of the third circuit is common to the first circuit, and the FET 8 is common to the second circuit.

The output section 13 includes two FETs 16, 17 each forming a source follower, two diode groups 14, 15 in which three diodes are connected in series, and an FET 22, 23 functioning as a current source. 1st above
circuit 7 or third circuit (n) and second circuit 11
The potential generated across the load resistor 6.10 of the diode group 14.
The output logic signals 0LJTx, 0UTX, OUT, 0UTy,
Output as OUT, , OUT. In FIG. 3, 18 to 20 are resistors, 21 to 23 are FETs, the abbreviation VCS is a reference power source for current stabilization, and VsS is a negative constant voltage power source.

In the configuration shown in FIG. 2, the input logic signal is a logic "1".
If we consider the case where we input the input logic signal to D2 so that it changes from the logic "θ" to the logic "1", the input buffer gate 2.3 will have D 18% D 18%
Dzy and D2y are respectively output and input to the AND gate circuit 4. As a result, the FET5 shown in Fig.
While the source-drain current of FET8.9 decreases,
The source-drain current flowing through the FET 12 increases, and the path of the current flowing into the FET 12 changes from the first circuit 7 to the second circuit 1.
1 can be switched quickly. And the second circuit 11
The voltage generated across the load resistor 10 due to the current flowing through FE is
T16, level shifted via diode group 14;
Logic "0" OUT Tx - OU Ty , OUT
− is output. Note that at this time, diode group 1
From 5 onwards, logic “1” (7) OUTx, OUTy, O
UT2 is output.

In this way, GaAs is used in the switching devices constituting the first circuit 7, the second circuit 11, and the third circuit (n).
Since FETs are used and similar switching devices are used for other switching devices, it is possible to configure a logic circuit with extremely high signal transmission speed, and can meet the recent demands for higher speeds.

[Problem that the invention seeks to solve]

However, in such conventional 5CFL,
The first circuit 7 is composed of one stage of FET5, and the second circuit 1
1 is a two-stage FET8.9, and the third circuit (n) is a two-stage FET.
Since the configuration was asymmetrical, consisting of ET8.21, the difference in signal transmission speed due to the difference in the number of stages of these first circuit 7, second circuit 11, or third circuit (n) and the voltage applied to one stage of FET Due to the difference between There was a problem with the

The present invention was made in view of these problems, and
The purpose of adding a dummy FET is to make the circuit symmetrical, match the switching timing, and eliminate waveform distortion of the output logic signal.

[For production]

In the present invention, a plurality of circuits having the same number of stages and having a symmetrical configuration are switched according to a combination of input logic signals.

Therefore, the switching timings are matched, and waveform distortion of the output logic signal is eliminated.

[Means for solving problems]

In order to achieve the above object, the present invention has a plurality of circuits having a common current source, switches the plurality of circuits according to a combination of input logic signals, and supplies current to the current source via the switched circuit. , and outputs the voltage generated in the load resistance of the switched circuit as an output logic signal, the plurality of circuits each including a plurality of stages of FETs connected in series, and at least In a logic circuit in which the number of FET stages in one circuit is smaller than the number of stages in other circuits, a dummy FET is added in series to the circuit with a smaller number of FET stages among the plurality of circuits to match the number of stages in the other circuits. When the circuit is switched to a circuit including a dummy FET, the dummy FET is turned on.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a diagram showing an embodiment of a logic circuit according to the present invention, and is an example applied to 5CFL of AND logic. In addition,
The FET used in the following description refers to a GaAs FET.

First, the configuration will be explained. In Figure 1, 3o is 5CF
The gate circuit 30 receives signals D18% D +x, D from input buffer gates not shown.
ZX% D zyz D my is input. These signals are generated by two input logic signals at the input buffer gate, with ,D, being complementary signals, and the X potential and
The signal is level-shifted to a potential (where x>y), and the shifted potential is represented by subscripts x and y of each signal. Note that the subscripts 1 and 2 correspond to the subscripts of the input logic signals RI and D2.

The gate circuit 30 includes a logic conversion section 31 and an output section 33.
The logic converter 31 includes three circuits, namely a first circuit 31
a, a second circuit 31b, and a third circuit 31C. The first circuit 31a is FET34, Gummy-FE
The second circuit 31b is configured by connecting an FET 35 as T and a load resistor 36 in series, and the second circuit 31b includes an FET 37, an FE
It is configured by connecting T38 and load resistor 39 in series,
Further, the third circuit 31c is configured by connecting an FET 37, a FET 45, and a load resistor 36 in series. Here, the FET 37 is common to the second circuit 31b, and the load resistance 3
6 is common to the first circuit 31a. These first circuit 31a, second circuit 31b, and third circuit 31C
are connected to the ground potential G via a common load resistor 40 and to a common first constant current source circuit (current source) 41, and are connected to a combination of signals from the input buffer gates (i.e., an input logic signal ri, ,D, combination)
Accordingly, the first, second and third circuits 31a, 31b, 31
A constant current it is caused to flow from the ground potential G toward the first constant current source circuit 41 while switching c. In addition, 42
．． 43 is a connection point provided between the first circuit 31a or the third circuit 31c and the second circuit 31b, voltage V is taken out from the connection point 42, and voltage vl is taken out from the connection point 43. .

The first constant current source circuit 41 includes an FET 48 and a resistor 49, the second constant current source circuit 46 includes an FET 50 and a resistor 51, and the third constant current source circuit 47 includes an FET 48 and a resistor 49.
It is composed of an ET52 and a resistor 53.

These first constant current source circuit 41, second constant current source circuit 46, and third constant current source circuit 47 control the current lux IA flowing through the logic conversion section 31 and the output section 33 according to the current stabilization reference power supply VCS. % Works to keep tB constant.

The output section 33 includes FETs 54 and 55, and these FEs
The gates of T54.55 are each connected to the connection points 42.43 of the logic converter 31, and each source is connected to a diode group 56 consisting of three diodes D, -D.
．． 57 is connected. Diode group 56.57 is F
The current 11% IA from ET54.55 is fed into the second constant current source circuit 46 and the third constant current source circuit 47, and the current is applied according to the product of the current iB, iA and the diffused resistance of the diodes D, ~D3. A voltage of magnitude is generated at each connection point,
This voltage is output as the logic signal OTJ Tx -OUTx S
OUTy 10 UTy 10 UT, ,OUT, take out and output.

Next, the effect will be explained.

Now, let us consider two cases: when the input logic signal input to the input buffer gate (not shown) is logic "1" and D2 is logic "0", and when both are logic "1". , the signals from the input cover sofa gate (not shown) take the values shown in Table 1 below.

Table 1 However, X potential>X potential Therefore, if Dl is fixed at logic "1" and D2 is switched from logic "0" to logic "1", logic "0"
FET 34, with a logic "1" applied to its gate, rapidly decreases the source-drain current, while FET 37, with a logic "1" applied to its gate, rapidly increases the source-drain current. That is, the first circuit The current flowing through the second circuit 31b decreases while the current flowing through the second circuit 31a increases, so that the current flowing from the first circuit 31a to the second circuit 31b
A switch is made to.

At the time of such switching, the FETs 34, 35, 37 forming the first circuit 31a and the second circuit 31b
．． 38, a signal at the same X potential is applied to FET 34 and FET 37, and a signal at the same X potential is applied to FET 35 and FET 38. Therefore, the circuit conditions are the same between FETs of the same level, and if the gate circuit 30 is fabricated on the same substrate, the process environment is also the same, so the characteristics of these FETs are aligned and the first The switching timings of the circuit 31a and the second circuit 31b coincide.

As a result, in response to the switching timing of the first circuit 31a and the second circuit 31b, the voltage VA shows a potential corresponding to logic "1", while the voltage VIl shows a potential corresponding to logic "0", These voltages 6, VB from the output section 33
Output logic signal 0UTX -0UTx, OU corresponding to
T,,0UTy,0UT2,oUT,l are output. At this time, 0UTX, OUT,, OUT are logic "1"
″,0LJTX.

Level shift amounts indicated by subscripts x, y, and z (where x>y>x) are attached to these signals.

That is, the logic is changed corresponding to the switching timing of oUTX~a outputted from the output section 33 and the second circuit 31b, and the logic of the first circuit 3La and the second circuit 31b is changed.
Since the switching timings of the circuits 31b coincide with each other, waveform distortion does not occur.

Therefore, it is possible to avoid an adverse effect on the next-stage circuit, etc., and to prevent malfunctions.

On the other hand, when the input logic signal D2 remains at logic "1" and only Dl changes from logic "1" to logic "0", DIX becomes logic "0", Dlx becomes logic "1", and the second circuit 31
The source-drain current flowing through the FET 38 of circuit 31b rapidly decreases, while the source-drain current flowing through the FET 45 of the third circuit 31c rapidly increases. As a result, the current flow is switched from the third circuit 31C to the second circuit 31b.

changes from 1'' to 0'', ■ changes from '0'' to "1" and is output from the output section 33.○u'r'x~O
The logic of U Tz , OU Tx −OU Tz is inverted.

Furthermore, when the input logic signal D2 changes from logic "1" to "0", "π" and "π change to logic "l", and the FET 35
and the source-drain current flowing through 34 increases rapidly. At this time, the source/drain current of FET37 is D2. ="0", the current 11 flowing into the first constant current source circuit 41 flows through the first circuit 31a, and the current 11 flows from the second circuit 31b to the first circuit 31a. Switching occurs quickly.

In this way, in this embodiment, the first circuit 31a is provided with a dummy F.
Adding FET35 as an ET in series, the first circuit 3
1a, the second circuit 31b, and the third circuit 31c have the same number of stages, and furthermore, a signal D2K having the same level shift amount as that of the FET 38 and FET 45 is applied to the gate of the FET 35 in order to match the circuit conditions. Therefore, the switching timings of these first, second, and third circuits 31a, 31b, and 31C can be matched, and the waveform distortion of 0UTX to 0UT2.0UTx and 0UTz outputted from the output section 33 can be eliminated. Can be done.

Note that, although AND logic is used as an example in this embodiment, the present invention is not limited to this, and OR logic may be used. In this case, D IX% D +x-, D zy, Day and D in the above example
OR logic is obtained by inverting the logic of π.

Further, in this embodiment, three circuits, the first circuit 31a, the second circuit 31b, and the third circuit 31c, are considered as the plurality of circuits, but the present invention is not limited to this. Furthermore, the number of stages of FETs constituting each circuit may be two or more. The key is to add gummy FETs to the circuit that lacks the number of stages to create a symmetrical configuration, and
When switched to the added circuit, Gummy-F
All you have to do is turn on the ET.

〔Effect of the invention〕

According to the present invention, since dummy FETs are added to make the plurality of circuits have a symmetrical configuration, it is possible to match the switching timing when switching these plurality of circuits according to the combination of input logic signals, and output Waveform distortion of logic signals can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a logic circuit according to the present invention, FIGS. 2 to 4 are diagrams showing conventional logic circuits, FIG. 2 is a block diagram thereof, and FIG. 3 is an AND diagram thereof. FIG. 4 is a configuration diagram showing the gate circuit and a waveform diagram for explaining the problem. 34.37.38...FET. 35...FET (Gummy-FET), 36.
39... Load resistance, 41... First constant current source circuit (current source). 31a: First circuit 31b: Second circuit 31c: Third circuit'"°1"o*-aam Fig. 1 Block diagram showing a conventional logic circuit? Fig. 2: A configuration diagram showing an AND gate circuit of a conventional logic circuit Fig. 3: A waveform diagram to explain the problems of a conventional logic circuit Fig. 4:

Claims (1)

[Claims] A device comprising a plurality of circuits having a common current source, switching the plurality of circuits according to a combination of input logic signals, flowing a current into the current source via the switched circuit, and A logic circuit that outputs a voltage generated in a load resistance of a circuit as an output logic signal, the plurality of circuits each having a plurality of stages of FEs connected in series.
T, the number of FET stages in at least one circuit is
In a logic circuit with a smaller number of stages than other circuits, among the plurality of circuits, a dummy FET is added in series to the circuit with fewer stages of FETs to match the number of stages of the other circuits, and the circuit to which the dummy FET is added is A logic circuit characterized in that when switched, a dummy FET is turned on.