JPH01175064U - - Google Patents
Info
- Publication number
- JPH01175064U JPH01175064U JP6992188U JP6992188U JPH01175064U JP H01175064 U JPH01175064 U JP H01175064U JP 6992188 U JP6992188 U JP 6992188U JP 6992188 U JP6992188 U JP 6992188U JP H01175064 U JPH01175064 U JP H01175064U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- signal
- capacitors
- synchronization signal
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図乃至第２図はこの考案に係るクランプ回
路の実施例を示し、第１図は回路図、第２図は他
の実施例を示す回路図である。第３図は従来の実
施例を示す回路図である。
主な符号の説明、１，２，４：入力端子、３，
５，６，７：トランジスタ、４ａ，４ｂ：コンデ
ンサ、８：出力端子。
1 and 2 show an embodiment of the clamp circuit according to this invention, FIG. 1 is a circuit diagram, and FIG. 2 is a circuit diagram showing another embodiment. FIG. 3 is a circuit diagram showing a conventional embodiment. Explanation of main symbols, 1, 2, 4: input terminal, 3,
5, 6, 7: transistor, 4a, 4b: capacitor, 8: output terminal.
Claims (1)
してトランジスタからなる増幅器に導くようにし
た映像増幅回路において、 前記コンデンサを２つのコンデンサに分割しこ
の２つのコンデンサが接続する接続線路には前記
トランジスタとは別の極性の異なるトランジスタ
のコレクタを接続し、このトランジスタのエミツ
タは電源又はグランドに接続し、ベースには複合
同期信号を入力するように構成したことを特徴と
する同期信号のクランプ回路。 ２ ２つのコンデンサの接続線路に接続するトラ
ンジスタのベースにはスケルチ信号を入力するよ
うに構成したことを特徴とする請求項１記載の同
期信号のクランプ回路。[Claims for Utility Model Registration] 1. In a video amplification circuit in which a video signal and a composite synchronization signal are guided through a capacitor to an amplifier consisting of a transistor, the capacitor is divided into two capacitors, and the two capacitors are connected. The collector of a transistor having a different polarity from that of the transistor is connected to the connecting line, the emitter of this transistor is connected to the power supply or ground, and the base is configured to input a composite synchronization signal. Clamp circuit for synchronous signal. 2. The synchronization signal clamp circuit according to claim 1, wherein a squelch signal is input to the base of the transistor connected to the connection line of the two capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6992188U JPH01175064U (en) | 1988-05-28 | 1988-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6992188U JPH01175064U (en) | 1988-05-28 | 1988-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01175064U true JPH01175064U (en) | 1989-12-13 |
Family
ID=31295185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6992188U Pending JPH01175064U (en) | 1988-05-28 | 1988-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01175064U (en) |
-
1988
- 1988-05-28 JP JP6992188U patent/JPH01175064U/ja active Pending