JPH0117258B2 - - Google Patents
Info
- Publication number
- JPH0117258B2 JPH0117258B2 JP58007306A JP730683A JPH0117258B2 JP H0117258 B2 JPH0117258 B2 JP H0117258B2 JP 58007306 A JP58007306 A JP 58007306A JP 730683 A JP730683 A JP 730683A JP H0117258 B2 JPH0117258 B2 JP H0117258B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- thermal expansion
- silicon carbide
- substrate
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 53
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 28
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 13
- 239000005394 sealing glass Substances 0.000 claims description 12
- 238000001816 cooling Methods 0.000 claims description 11
- 229910052790 beryllium Inorganic materials 0.000 claims description 7
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 7
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052863 mullite Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052845 zircon Inorganic materials 0.000 claims description 4
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 4
- 150000001573 beryllium compounds Chemical class 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims 2
- 239000000919 ceramic Substances 0.000 description 31
- 239000011521 glass Substances 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 10
- 230000017525 heat dissipation Effects 0.000 description 9
- 230000008646 thermal stress Effects 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 230000005856 abnormality Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- -1 cap Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
Description
本発明は集積回路パツケージに係り、特にセラ
ミツクスパツケージ部材の熱膨張係数の整合と熱
放散性に特徴のある集積回路パツケージに関す
る。
セラミツクス系の絶縁基板、キヤツプおよび封
止材からなるパツケージによつて気密に囲われた
小室内に、半導体素子並びに外部から導入された
リード片の端部と両者を電気的に接続したワイヤ
とを収容した構造になる集積回路パツケージ(パ
ツケージされた集積回路製品を指す)は、今日広
く使われている。
そのようなセラミツクスのパツケージを用いた
際の難点として、半導体素子に生じた熱の放散特
性が極めて悪いという問題が指摘される。このこ
とは、半導体素子の大容量化、高集積化および小
型化を図るうえで、大きな障害となつている。従
つて、集積回路パツケージにおいて、半導体素子
をとりつける絶縁基板に使われるセラミツクスに
は、電気絶縁性とともに優れた熱伝導性を有する
ことが要求される。また、基板用材料としては、
熱膨張係数がケイ素半導体のそれに近似するこ
と、大きな機械的強度を有することなどの条件を
満すことも望まれる。
現在、これらの条件にある程度かなう絶縁基板
材料として、アルミナ焼結体が使用されている。
しかし、その熱伝導率は低く0.05cal/cm・s・
℃ほどである。従つて、アルミナ焼結体は、半導
体素子の熱放散特性の観点からは、好ましい材料
ではない。他方、セラミツク・パツケージを用い
ながら半導体素子の熱放散特性を構造面から改善
する提案として、第1図に示すように、絶縁基板
4を貫通してパツケージの外部に延びる銅スタツ
ド31の上に、半導体素子1を取り付ける方法が
知られている。基板4、キヤツプ5および封止材
6からなるパツケージ内において、半導体素子1
は銅スタツド31に、両者間の熱膨張の差に起因
する応力を緩和するためにモリブデン製支持板3
2を介して接着され、該素子1は、基板4上に接
着されたリード片3の端部にボンデイングワイヤ
2によつて電気的に接続されている。半導体素子
1に発生した熱は支持板32、銅スタツド31を
経てパツケージ外に伝わり、さらに、冷却フイン
9によつて放散される。このような構造にあつて
は、半導体素子1から冷却フイン9に至る伝熱路
が全て、熱伝導性に優れた金属から成るので、高
い熱放散特性をもつ集積回路パツケージが得られ
る。
しかし反面、この方式には(1)部品点数が増加
し、構造が複雑であるために組立て工数が多くな
ること、(2)銅、モリブテンなど比重の大きい部品
を使用するために製品が重くなり、プリント配線
板等への取付けが面倒になることなどの欠点があ
る。
このような状況を打開すべく、本発明者らは種
種研究を進め、既述の条件にそつて従来に勝る高
い熱伝導率とケイ素に近似した熱膨張係数を有す
る炭化ケイ素質セラミツクスを開発し、それを絶
縁基板に適用して、熱放散特性の良好な集積回路
パツケージの製作を可能にした(出願番号56−
195986)。
しかし、該炭化ケイ素質基板の適用に関する検
討の進行に伴い、該基板に従来のアルミナセラミ
ツクス製キヤツプを組合せたとき、それらを接着
封止したガラス層に亀裂が生ずるという問題が起
つた。これは炭化ケイ素質セラミツクスとアルミ
ナセラミツクスとの熱膨張の差に起因する。
本発明はそれらの知見に基づき、キヤツプ材料
の熱膨張係数を限定することによつて前記の提案
と補完し、熱放散特性に優れるとともに、一層高
い安定性と信頼性を有する集積回路パツケージを
提供することを目的にしている。すなわちその特
徴は、炭化ケイ素質絶縁基板、キヤツプおよび封
止ガラスによつて気密に囲われた小室内に、該基
板上に載置された半導体素子と該室外から導入さ
れたリード片の端部およびそれらを電気的に接続
するワイヤが収容されてなる集積回路パツケージ
において、キヤツプが熱膨張係数(20〜55)×
10-7/℃を有する材料からなることである。
さらに、本発明においては、封止材として熱膨
張係数(30〜55)×10-7/℃を有するガラス特に、
実際的には(40〜55)10-7/℃の熱膨張係数をも
つガラスが適応される。
本発明において、半導体素子がとり付けられる
絶縁基板は、ベリリウムおよびベリリウム化合物
のうちから選ばれた少なくとも1種をベリリウム
量にして0.05―5重量%含み炭化ケイ素を主成分
とする実質的に炭化ケイ素質セラミツクスであつ
て、かつ、理論密度の90%以上の相対密度を有す
る焼結体によつて構成されている。その熱膨張係
数は(35〜40)×10-7/℃であつてケイ素の熱膨
張係数値に近く、また、その熱伝導率は0.2cal/
cm・s・℃以上である。この熱伝導率0.2cal/
cm・s・℃という値は、炭化ケイ素質セラミツク
スが焼結によつて作られる場合に、電気絶縁性
(抵抗率107Ω・cm以上)と熱膨張係数とに悪影響
を与えることなく、良好な再現性をもつて得られ
る熱伝導率の下限を意味し、しかもそれは従来の
アルミナセラミツクス基板の熱伝導率の約4倍の
値である。また、該炭化ケイ素質セラミツクスの
熱膨張係数がケイ素のそれに近いので、半導体素
子が絶縁基板に接着剤層を介してとりつけられた
場合に、両者の熱膨張の差によつて生ずる熱応力
は小さい。従つて、第1図のような応力緩衝材を
基板・素子間に挿入することも要しない。このよ
うな特性をもつセラミツクスを絶縁基板の構成材
料とすることは、本発明において半導体素子の熱
放散性を高める基礎的条件である。
その条件のうえにたつて本発明においては、絶
縁基板上の半導体素子や配線等を覆い封入するた
めのキヤツプが、熱膨張係数(20〜55)×10-7/
℃をもつ材料で構成されることが、特徴をなして
いる。そのような材料として、絶縁基板の材料と
同じ炭化ケイ素質セラミツクス、ムライト質セラ
ミツクス、ジルコン質セラミツクス、窒化ケイ素
質セラミツクスなどが使用できる。前記熱膨張係
数値をもつキヤツプ材を使用すると、従来のアル
ミナセラミツクス(熱膨張係数約65×10-7/℃)
使用に比較して、炭化ケイ素質絶縁基板との間の
膨張差は20〜60%縮減され、従つてそれだけ基
板・キヤツプ間に起り得る熱応力は軽減される。
封止用ガラス材についても、理想的には絶縁基
板に使われた炭化ケイ素質セラミツクスの熱膨張
係数に近い熱膨張係数をもつことが望ましく、そ
の値として(30〜55)×10-7/℃が適当である。
なお、ガラス封止が、絶縁基板上に半導体素子を
接着してのちに行なわれるため、高融点のガラス
は使用に適しない。最高でも500℃以下の温度で
封止可能なガラスが選定されねばならない。
絶縁基板、キヤツプおよび封止材にそれぞれ前
記した特性を有するセラミツクスおよびガラスを
使用することによつて、封止温度から室温までの
冷却においても、また、−55〜+150℃の間の冷熱
サイクルを反復した際にも、封止部に亀裂を生じ
たり、電気特性に異常を生ずることのない安定性
と、高い信頼性をもち熱放散特性にすぐれた集積
回路パツケージが得られる。
次に、本発明を実施例によつて説明する。
実施例 1
第2図に本発明の集積回路パツケージの断面を
例示する。同図において炭化ケイ素質セラミツク
スからなる絶縁基板4の一方の面4a上の中央部
に半導体素子1が金属ソルダ層7によつて接着さ
れ、同面上に封止ガラス層6によつて接着された
複数個のリード片3の一端3aと該素子1との間
は、ボンデイングワイヤ2によつて電気的に接続
されている。リード片3の他端3bは、基板4の
周縁から外方に延びている。素子1、ボンデイン
グワイヤ2およびリード片3の端部3aは、絶縁
基板4とキヤツプ5とによつて囲われ、該キヤツ
プ5と基板4およびリード片3との間隙はソルダ
ガラス層6を介して気密に封着されている。
さて、このような構造において、封止に熱膨張
係数(50〜55)×10-7/℃をもつガラスが用いら
れた際に、封止温度から室温までの温度範囲で該
ガラスにかかる最大熱応力が、キヤツプ材の熱膨
張係数に依存してどう変るか、その関係を計算に
より求めた。
この計算はパツケージを中空円板にモデル化
し、要素分割を行ない、3次元軸対称問題用の有
限要素法解析プログラムを用いて行なつたもので
ある。
その結果は第3図に示される。ガラスの強度は
4Kg/mm2程度であるので、熱膨張係数55×10-7/
℃以上のセラミツクスは、ガラスに亀裂を生じ、
キヤツプ材として不適当である。
(20〜55)×10-7/℃の熱膨張係数(α)をも
つ材料として、前記炭化ケイ素質セラミツクス
(α=(35〜40)×10-7/℃)、ムライト質セラミツ
クス(α=(43〜55)×10-7/℃)、ジルコン質の
セラミツクス(α=(30〜40)×10-7/℃)、ある
種の窒化ケイ素質セラミツクス(α=(20〜35)×
10-7/℃)等が使用される。
ここで絶縁基板に使われた炭化ケイ素質セラミ
ツクスは、ベリリウム量にして0.05〜5重量%の
酸化ベリリウムを含むほかは実質的に炭化ケイ素
からなり、理論密度の90%以上の密度をもつ焼結
体である。それは抵抗率(室温)108Ω・cm以上
の電気絶縁性と、熱伝導率0.2〜0.7cal/cm・s・
℃、曲げ強さ30Kg/mm2以上という特性をもつてい
る。
上記のような材料構成で得られた集積回路パツ
ケージは、リード片とリード片との間で108Ω以
上の絶縁抵抗を有し、封止温度(460℃)〜室温
の冷却時、および−55〜150℃の冷熱サイクル
1000回の試験後も、破損などの事故や電気特性上
の異常を示さなかつた。
実施例 2
基本的には実施例1と同様にして集積回路パツ
ケージを作成した。
絶縁基板は、ベリリウム含量の重量%(酸化ベ
リリウム使用)のほかは、炭化ケイ素を不可避的
に混入する不純物からなり、理論密度の98%の密
度を有する焼結体で形成された炭化ケイ素質セラ
ミツクスで作られた。その特性として、比重約
3.2、抵抗率1013Ω・cm(室温)、熱膨張係数(25
〜300℃)35×10-7/℃前後、熱伝導率0.6cal/
cm・s・℃、曲げ強さ45Kg/mm2前後の値が得られ
た。
キヤツプは、熱膨張係数45×10-7/℃をもつム
ライト質セラミツクスから作成された。
上記絶縁基板とキヤツプに対し、種々の熱膨張
係数をもつガラスが封止に用いられたときに、ガ
ラスにかかる最大熱応力とその熱膨張係数との関
係を、実施例2の第3図の場合と同様にして、求
めた。結果は第4図に示されるとおりである。
ガラスの熱膨張係数が55×10-7/℃を越える
と、ガラスは過大な応力をうけて亀裂する。一
方、熱膨張係数55×10-7/℃未満のガラスは、小
さな熱応力を受けるにすぎない。しかし、30×
10-7/℃以下熱膨張係数をもち、しかも封止用と
して望まれるような低融点のガラスは得られない
ので、実質的には実施されない。したがつて、
(30〜55)×10-7/℃の熱膨張をもつガラスが望ま
しい。
前記された絶縁基板とキヤツプおよび熱膨張係
数(45〜48)×10-7/℃、封止温度450〜460℃の
封止用ガラスを用いて、集積回路パツケージが作
成された。
該集積回路パツケージは、リード片間の絶縁抵
抗108Ω以上、半導体素子と絶縁基板の表面との
間の熱抵抗12.5℃/Wの特性値を与えた。また、
該パツケージは−55〜150℃間の冷熱サイクルを
100回受けた後にも、破損などの事故や電気特性
上の異常を起さなかつた。
実施例 3
実施例1に記された集積回路パツケージにおい
て、第5図に示されるように、アルミニウムなど
の金属からなる冷却フイン9が絶縁基板4接着層
10に取付けられた。該フイン9は、熱伝導性フ
イラで充填されたエポキシ樹脂系またはシリコー
ン樹脂系接着剤によつて接着されることが、好ま
しい。また、フインは、炭化ケイ素質絶縁基板の
所望に従いメタライズされた部分に半田で接着さ
れることも可能である。このような構成において
は、半導体素子と外気雰囲気との間の熱抵抗は
9.3℃/Wになり、実施例2における12.5℃/W
よりも、さらに低減された。この値は、従来の集
積回路パツケージ(第1図参照)の熱抵抗約11.5
℃/Wに比べ、約20%低い。
さらに、変型例として、基板とフインとが炭化
ケイ素質セラミツクスで一体に製作されることが
でき、その適用によつて集積回路パツケージの熱
抵抗は5.1℃/Wに低減可能であつた。また、該
集積回路パツケージは−55〜150℃の冷熱サイク
ル100回の試験を受けた後も、破損などの事故や
電気特性の異常を来さなかつた。
実施例 4
本発明の集積回路パツケージの構造は、前記実
施例によつて限定されない。各種の変り型が可能
である。その例(断面)を第6図および第7図に
示す。箱形に成形された絶縁基板4の内側底面の
中央部に、メタライズ層8を介して半導体素子1
が接着されている。リード片3は、ボンデイング
ワイヤ2によつて一端を半導体素子1に電気的に
接続され、他方の絶縁基板内面に沿い立上り基板
周縁に引出された端に、ソルダー層7によりリー
ドフレーム11と接着される。そして、該基板4
の開口部に蓋状のキヤツプ5がはめ込まれ、基
板・キヤツプまたはリード片間の隙間はガラス6
をもつて封止される。
絶縁基板はベリリウムを0.05〜5重量%含む炭
化ケイ素質セラミツクスで、キヤツプは熱膨張係
数45×10-7/℃を有するムライト質セラミツクス
でそれぞれ作成された。また、封止には熱膨張係
数47×10-7/℃、封止温度460℃を有するガラス
が用いられた。
製作された集積回路パツケージは、−55〜150℃
の冷熱サイクル100回の試験に耐え、破損や電気
特性の異常を起さなかつた。
比較実験例
第1表に示すように、基板とキヤツプを接着す
る封止ガラスの熱膨張係数の異なるものを用い
て、パツケージを作成した。これを用いて、封止
後のリークテスト(Heガス)および冷熱サイク
ルの比較実験を行つた。結果を第1表に示す。
The present invention relates to an integrated circuit package, and more particularly to an integrated circuit package characterized by matching of the coefficient of thermal expansion and heat dissipation of ceramic package members. In a small chamber airtightly surrounded by a package consisting of a ceramic insulating substrate, a cap, and a sealing material, the semiconductor element, the end of the lead piece introduced from the outside, and the wire electrically connecting the two are placed. Integrated circuit packages (referring to packaged integrated circuit products), which are enclosed structures, are widely used today. One of the drawbacks of using such a ceramic package is that the heat dissipation properties generated in the semiconductor element are extremely poor. This is a major hindrance in achieving larger capacity, higher integration, and smaller size of semiconductor devices. Therefore, in integrated circuit packages, ceramics used for insulating substrates on which semiconductor elements are mounted are required to have excellent thermal conductivity as well as electrical insulation properties. In addition, as substrate materials,
It is also desired that the material satisfies conditions such as having a thermal expansion coefficient similar to that of a silicon semiconductor and having high mechanical strength. Currently, alumina sintered bodies are used as an insulating substrate material that meets these conditions to some extent.
However, its thermal conductivity is low, 0.05 cal/cm・s・
It is about ℃. Therefore, the alumina sintered body is not a preferable material from the viewpoint of heat dissipation characteristics of semiconductor elements. On the other hand, as a proposal to improve the heat dissipation characteristics of a semiconductor element from a structural aspect while using a ceramic package, as shown in FIG. Methods of attaching the semiconductor element 1 are known. A semiconductor element 1 is placed inside a package consisting of a substrate 4, a cap 5, and a sealing material 6.
A molybdenum support plate 3 is attached to the copper stud 31 to relieve stress caused by the difference in thermal expansion between the two.
The element 1 is electrically connected to the end of a lead piece 3 bonded on a substrate 4 by a bonding wire 2 . The heat generated in the semiconductor element 1 is transmitted to the outside of the package via the support plate 32 and the copper studs 31, and is further dissipated by the cooling fins 9. In such a structure, all the heat transfer paths from the semiconductor element 1 to the cooling fins 9 are made of metal with excellent thermal conductivity, so that an integrated circuit package with high heat dissipation characteristics can be obtained. However, this method has the disadvantages of (1) an increase in the number of parts and a complicated structure, which increases the number of assembly steps, and (2) the use of parts with high specific gravity such as copper and molybdenum, which increases the weight of the product. However, there are disadvantages such as the difficulty of attaching it to a printed wiring board or the like. In order to overcome this situation, the present inventors conducted various research and developed silicon carbide ceramics that meet the above-mentioned conditions and have higher thermal conductivity than conventional materials and a coefficient of thermal expansion similar to that of silicon. By applying it to an insulating substrate, it became possible to fabricate an integrated circuit package with good heat dissipation characteristics (Application No. 56-
195986). However, as studies on the application of the silicon carbide substrate progressed, a problem arose that when a conventional alumina ceramic cap was combined with the substrate, cracks appeared in the glass layer that bonded and sealed them together. This is due to the difference in thermal expansion between silicon carbide ceramics and alumina ceramics. Based on these findings, the present invention complements the above proposal by limiting the thermal expansion coefficient of the cap material, thereby providing an integrated circuit package with excellent heat dissipation characteristics and even higher stability and reliability. is aimed at. That is, the feature is that the semiconductor element mounted on the substrate and the end of the lead piece introduced from the outside are placed in a small chamber airtightly surrounded by a silicon carbide insulating substrate, a cap, and a sealing glass. In an integrated circuit package that houses wires and wires that electrically connect them, the cap has a coefficient of thermal expansion (20 to 55) x
10 -7 /℃. Furthermore, in the present invention, glass having a coefficient of thermal expansion (30 to 55) x 10 -7 /°C, in particular, is used as the sealing material.
In practice, glass having a coefficient of thermal expansion of (40 to 55) 10 -7 /°C is suitable. In the present invention, the insulating substrate to which the semiconductor element is attached is substantially silicon carbide containing silicon carbide as a main component and containing 0.05 to 5% by weight of at least one selected from beryllium and beryllium compounds. It is composed of a sintered body that is made of elementary ceramics and has a relative density of 90% or more of the theoretical density. Its thermal expansion coefficient is (35~40)×10 -7 /℃, which is close to that of silicon, and its thermal conductivity is 0.2 cal/℃.
cm・s・℃ or higher. This thermal conductivity is 0.2cal/
The value cm・s・℃ is the value that is suitable for silicon carbide ceramics made by sintering without adversely affecting electrical insulation (resistivity of 10 7 Ω・cm or more) and thermal expansion coefficient. This means the lower limit of thermal conductivity that can be obtained with good reproducibility, and moreover, it is about four times the thermal conductivity of conventional alumina ceramic substrates. In addition, since the coefficient of thermal expansion of the silicon carbide ceramic is close to that of silicon, when a semiconductor element is attached to an insulating substrate via an adhesive layer, the thermal stress caused by the difference in thermal expansion between the two is small. . Therefore, it is not necessary to insert a stress buffer material between the substrate and the element as shown in FIG. Using ceramics having such characteristics as the constituent material of the insulating substrate is a basic condition for improving the heat dissipation properties of the semiconductor element in the present invention. Based on this condition, in the present invention, a cap for covering and enclosing semiconductor elements, wiring, etc. on an insulating substrate has a coefficient of thermal expansion (20 to 55) x 10 -7 /
It is characterized by being made of material that has a temperature of ℃. As such materials, silicon carbide ceramics, mullite ceramics, zircon ceramics, silicon nitride ceramics, etc., which are the same as the materials of the insulating substrate, can be used. If a cap material with the above thermal expansion coefficient value is used, conventional alumina ceramics (thermal expansion coefficient of approximately 65×10 -7 /°C) will be used.
Compared to use, the expansion differential with the silicon carbide insulating substrate is reduced by 20 to 60%, and therefore the possible thermal stresses between the substrate and the cap are reduced accordingly. Ideally, the sealing glass material should have a thermal expansion coefficient close to that of the silicon carbide ceramic used for the insulating substrate, and the value is (30 to 55) x 10 -7 / °C is appropriate.
Note that since glass sealing is performed after bonding the semiconductor element onto the insulating substrate, glass with a high melting point is not suitable for use. Glass that can be sealed at temperatures below 500°C must be selected. By using ceramics and glass with the above-mentioned characteristics for the insulating substrate, cap, and encapsulant, it is possible to cool down from the sealing temperature to room temperature, and also to withstand thermal cycles between -55 and +150°C. Even when the process is repeated, it is possible to obtain an integrated circuit package that is stable without causing cracks in the sealing portion or abnormalities in electrical characteristics, has high reliability, and has excellent heat dissipation characteristics. Next, the present invention will be explained with reference to examples. Embodiment 1 FIG. 2 illustrates a cross section of an integrated circuit package of the present invention. In the figure, a semiconductor element 1 is bonded to the center of one surface 4a of an insulating substrate 4 made of silicon carbide ceramics with a metal solder layer 7, and a sealing glass layer 6 is bonded on the same surface. One ends 3 a of the plurality of lead pieces 3 and the element 1 are electrically connected by bonding wires 2 . The other end 3b of the lead piece 3 extends outward from the periphery of the substrate 4. The end portions 3a of the element 1, bonding wire 2, and lead piece 3 are surrounded by an insulating substrate 4 and a cap 5, and the gaps between the cap 5, the substrate 4, and the lead piece 3 are separated by a solder glass layer 6. Hermetically sealed. Now, in such a structure, when glass with a coefficient of thermal expansion (50 to 55) × 10 -7 /℃ is used for sealing, the maximum applied to the glass in the temperature range from the sealing temperature to room temperature is We calculated how thermal stress changes depending on the thermal expansion coefficient of the cap material. This calculation was performed by modeling the package as a hollow disk, dividing it into elements, and using a finite element method analysis program for three-dimensional axisymmetric problems. The results are shown in FIG. Since the strength of glass is about 4Kg/mm2, the coefficient of thermal expansion is 55×10 -7 /
Ceramics at temperatures above ℃ will cause cracks in the glass,
Unsuitable as cap material. Materials with a coefficient of thermal expansion (α) of (20 to 55) × 10 -7 /°C include the silicon carbide ceramics (α = (35 to 40) × 10 -7 / °C), mullite ceramics (α = (43 to 55) × 10 -7 /℃), zircon ceramics (α = (30 to 40) × 10 -7 /℃), certain silicon nitride ceramics (α = (20 to 35) ×
10 -7 /℃) etc. are used. The silicon carbide ceramic used here for the insulating substrate consists essentially of silicon carbide except for beryllium oxide in an amount of 0.05 to 5% by weight, and is sintered with a density of 90% or more of the theoretical density. It is the body. It has electrical insulation with a resistivity (room temperature) of 10 8 Ω・cm or more and a thermal conductivity of 0.2 to 0.7 cal/cm・s.
℃, and has a bending strength of 30Kg/mm2 or more . The integrated circuit package obtained with the above-mentioned material composition has an insulation resistance of 10 8 Ω or more between the lead pieces, and when cooled from the sealing temperature (460°C) to room temperature, and - 55-150℃ cooling cycle
Even after 1,000 tests, there were no accidents such as damage or abnormalities in electrical characteristics. Example 2 An integrated circuit package was produced basically in the same manner as in Example 1. The insulating substrate is silicon carbide ceramic made of a sintered body with a density of 98% of the theoretical density, except for the beryllium content (by weight of beryllium oxide) and other impurities that inevitably include silicon carbide. Made with. Its characteristic is that the specific gravity is approximately
3.2, resistivity 10-13 Ω・cm (room temperature), thermal expansion coefficient (25
~300℃) around 35×10 -7 /℃, thermal conductivity 0.6cal/
cm・s・℃ and bending strength values of around 45 kg/mm 2 were obtained. The cap was made from mullitic ceramics with a coefficient of thermal expansion of 45 x 10 -7 /°C. When glass having various coefficients of thermal expansion is used for sealing the insulating substrate and cap, the relationship between the maximum thermal stress applied to the glass and its coefficient of thermal expansion is shown in FIG. 3 of Example 2. I asked for it in the same way as in the case. The results are shown in FIG. When the coefficient of thermal expansion of glass exceeds 55×10 -7 /°C, the glass is subjected to excessive stress and cracks. On the other hand, glasses with thermal expansion coefficients of less than 55×10 −7 /° C. experience only small thermal stresses. But 30×
Since it is impossible to obtain a glass having a coefficient of thermal expansion of 10 -7 /°C or less and a low melting point desired for sealing, it is not practically practiced. Therefore,
Glass having a thermal expansion of (30 to 55)×10 -7 /°C is desirable. An integrated circuit package was prepared using the above-mentioned insulating substrate, cap, and sealing glass having a thermal expansion coefficient of (45 to 48) x 10 -7 /°C and a sealing temperature of 450 to 460°C. The integrated circuit package provided characteristic values of insulation resistance between lead pieces of 10 8 Ω or more and thermal resistance between the semiconductor element and the surface of the insulating substrate of 12.5° C./W. Also,
The package can withstand heating and cooling cycles between -55 and 150℃.
Even after being tested 100 times, there were no accidents such as damage or abnormalities in electrical characteristics. Example 3 In the integrated circuit package described in Example 1, cooling fins 9 made of metal such as aluminum were attached to the insulating substrate 4 and the adhesive layer 10, as shown in FIG. The fins 9 are preferably bonded with an epoxy resin or silicone resin adhesive filled with a thermally conductive filler. Furthermore, the fins can be bonded to the metalized portion of the silicon carbide insulating substrate by solder, as desired. In such a configuration, the thermal resistance between the semiconductor element and the outside atmosphere is
9.3℃/W, 12.5℃/W in Example 2
was further reduced. This value corresponds to the thermal resistance of a conventional integrated circuit package (see Figure 1), which is approximately 11.5
Approximately 20% lower than ℃/W. Furthermore, as a modification, the substrate and the fins can be integrally made of silicon carbide ceramics, and by applying this, the thermal resistance of the integrated circuit package can be reduced to 5.1° C./W. In addition, the integrated circuit package did not cause any accidents such as breakage or abnormality in electrical characteristics even after being subjected to 100 cycles of cooling and heating cycles at -55 to 150°C. Embodiment 4 The structure of the integrated circuit package of the present invention is not limited to the above embodiments. Various variants are possible. Examples (cross sections) are shown in FIGS. 6 and 7. A semiconductor element 1 is placed in the center of the inner bottom surface of the box-shaped insulating substrate 4 through a metallized layer 8.
is glued. One end of the lead piece 3 is electrically connected to the semiconductor element 1 by the bonding wire 2, and the end that rises along the inner surface of the other insulating substrate and is drawn out to the periphery of the substrate is bonded to the lead frame 11 by a solder layer 7. Ru. Then, the substrate 4
A lid-shaped cap 5 is fitted into the opening of the board, and a glass 6 is provided to fill the gap between the board, cap, or lead piece.
It is sealed with. The insulating substrate was made of silicon carbide ceramic containing 0.05 to 5% by weight of beryllium, and the cap was made of mullite ceramic having a coefficient of thermal expansion of 45×10 -7 /°C. Furthermore, glass having a thermal expansion coefficient of 47×10 -7 /°C and a sealing temperature of 460°C was used for sealing. The fabricated integrated circuit package is -55 to 150℃
It withstood 100 heating and cooling cycles without any damage or abnormalities in electrical characteristics. Comparative Experimental Example As shown in Table 1, packages were created using sealing glasses with different thermal expansion coefficients for bonding the substrate and cap. Using this, we conducted a post-sealing leak test (He gas) and a comparative experiment on cooling and heating cycles. The results are shown in Table 1.
【表】
第1表から明らかなように、No.5,6,8〜
11、およびNo.15で示される本発明のパツケージ
は、いずれもリークテストおよび冷熱サイクルに
おいて優れた結果を示し、封止部にクラツク等の
発生がないことを示している。[Table] As is clear from Table 1, No.5, 6, 8~
The packages of the present invention designated by No. 11 and No. 15 both showed excellent results in the leak test and the cooling/heating cycle, indicating that there were no cracks or the like in the sealed portion.
第1図は従来の集積回路パツケージの断面図、
第2、第5、第6および第7図は、本発明の一例
である集積回路パツケージの断面図、第3図はキ
ヤツプ材の熱膨張係数と封止ガラス層に生ずる最
大熱応力との関係を示すグラフ、第4図は封止ガ
ラスの熱膨張係数と該ガラス層に生ずる最大熱応
力との関係を示すグラフである。
1……半導体装置、2……ボンデイングワイ
ヤ、3……リード片、4……絶縁基板、5……キ
ヤツプ、6……封止ガラス、7……金属ソルダー
層、8……メタライズ層、9……冷却フイン、1
0……接着層、11……リードフレーム、31…
…銅スタツド、32……モリブデン製支持板。
Figure 1 is a cross-sectional view of a conventional integrated circuit package.
2, 5, 6, and 7 are cross-sectional views of an integrated circuit package that is an example of the present invention, and FIG. 3 is a relationship between the thermal expansion coefficient of the cap material and the maximum thermal stress generated in the sealing glass layer. FIG. 4 is a graph showing the relationship between the coefficient of thermal expansion of the sealing glass and the maximum thermal stress generated in the glass layer. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Bonding wire, 3... Lead piece, 4... Insulating substrate, 5... Cap, 6... Sealing glass, 7... Metal solder layer, 8... Metallized layer, 9 ...cooling fin, 1
0... Adhesive layer, 11... Lead frame, 31...
...Copper stud, 32...Molybdenum support plate.
Claims (1)
ガラスによつて気密に囲われた小室内に、該基板
上に載置された半導体と該室外から導入されたリ
ード片の端部およびそれらを電気的に接続したワ
イヤが収容されて成る集積回路パツケージにおい
て、 前記炭化ケイ素質絶縁基板が、ベリリウムおよ
びベリリウム化合物の少なくとも1種をベリリウ
ムとして0.05〜5重量%含む実質的に炭化ケイ素
から成る焼結体であつて、理論密度に対する相対
密度90%以上、室温における熱伝導率0.2cal/
cm・s・℃以上、熱膨張係数(35〜40)×10-7/
℃の電気絶縁性基板であり、 前記キヤツプが、熱膨張係数(20〜55)×
10-7/℃のムライト質、炭化ケイ素質、ジルコン
質および窒化ケイ素質から選ばれたセラミツクス
材料で形成されており、 前記基板とキヤツプは、融点500℃以下、熱膨
張係数(30〜55)×10-7/℃である封止ガラスに
より接合封止されており、 前記リード片が、前記基板とキヤツプの接合封
止部を通して前記小室内に挿通されていることを
特徴とする集積回路パツケージ。 2 炭化ケイ素質絶縁基板、キヤツプおよび封止
ガラスによつて気密に囲われた小室内に、該基板
上に載置された半導体と該室外から導入されたリ
ード片の端部およびそれらを電気的に接続したワ
イヤが収容されて成る集積回路パツケージにおい
て、 前記炭化ケイ素質絶縁基板が、ベリリウムおよ
びベリリウム化合物の少なくとも1種をベリリウ
ムとして0.05〜5重量%含む実質的に炭化ケイ素
から成る焼結体であつて、理論密度に対する相対
密度90%以上、室温における熱伝導率0.2cal/
cm・s・℃以上、熱膨張係数(35〜40)×10-7/
℃の電気絶縁性基板であり、 前記キヤツプが、熱膨張係数(20〜55)×
10-7/℃のムライト質、炭化ケイ素質、ジルコン
質および窒化ケイ素質から選ばれたセラミツクス
材料で形成されており、 前記基板とキヤツプは、融点500℃以下、熱膨
張係数(30〜55)×10-7/℃である封止ガラスに
より接合封止されており、 前記リード片が、前記基板とキヤツプの接合封
止部を通して前記小室内に挿通されており、 かつ、半導体素子が載置された基板の裏面に冷
却用フインが設けられていることを特徴とする集
積回路パツケージ。[Scope of Claims] 1. A semiconductor placed on the silicon carbide insulating substrate, a cap, and an end of a lead piece introduced from the outside into a small chamber airtightly surrounded by a sealing glass. In the integrated circuit package, the silicon carbide insulating substrate is made of substantially silicon carbide containing 0.05 to 5% by weight of at least one of beryllium and beryllium compounds as beryllium. A sintered body with a relative density of 90% or more of the theoretical density and a thermal conductivity of 0.2cal/at room temperature.
cm・s・℃ or more, thermal expansion coefficient (35 to 40) x 10 -7 /
℃ is an electrically insulating substrate, and the cap has a thermal expansion coefficient (20~55) x
10 -7 /℃ made of ceramic material selected from mullite, silicon carbide, zircon, and silicon nitride, and the substrate and cap have a melting point of 500℃ or less and a thermal expansion coefficient (30 to 55). ×10 -7 /°C bonded and sealed with a sealing glass, and the lead piece is inserted into the small chamber through the bonded and sealed portion of the substrate and the cap. . 2. In a small chamber airtightly surrounded by a silicon carbide insulating substrate, a cap, and a sealing glass, the semiconductor placed on the substrate, the ends of the lead pieces introduced from the outside, and the ends of the leads are electrically connected. In the integrated circuit package, the silicon carbide insulating substrate is a sintered body substantially made of silicon carbide containing 0.05 to 5% by weight of at least one of beryllium and beryllium compounds as beryllium. Relative density to theoretical density is 90% or more, thermal conductivity at room temperature is 0.2cal/
cm・s・℃ or more, thermal expansion coefficient (35 to 40) x 10 -7 /
℃ is an electrically insulating substrate, and the cap has a thermal expansion coefficient (20~55) x
10 -7 /℃ made of ceramic material selected from mullite, silicon carbide, zircon, and silicon nitride, and the substrate and cap have a melting point of 500℃ or less and a thermal expansion coefficient (30 to 55). ×10 -7 /℃ bonded and sealed with sealing glass, the lead piece is inserted into the small chamber through the bonded sealing part of the substrate and the cap, and the semiconductor element is mounted. An integrated circuit package characterized in that cooling fins are provided on the back side of a printed circuit board.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58007306A JPS59134852A (en) | 1983-01-21 | 1983-01-21 | Integrated circuit package |
GB08401603A GB2135513B (en) | 1983-01-21 | 1984-01-20 | Packaged integrated circuit device |
DE19843401984 DE3401984A1 (en) | 1983-01-21 | 1984-01-20 | ENCLOSED INTEGRATED CIRCUIT |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58007306A JPS59134852A (en) | 1983-01-21 | 1983-01-21 | Integrated circuit package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59134852A JPS59134852A (en) | 1984-08-02 |
JPH0117258B2 true JPH0117258B2 (en) | 1989-03-29 |
Family
ID=11662323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58007306A Granted JPS59134852A (en) | 1983-01-21 | 1983-01-21 | Integrated circuit package |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS59134852A (en) |
DE (1) | DE3401984A1 (en) |
GB (1) | GB2135513B (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3603912A1 (en) * | 1985-02-09 | 1986-08-14 | Alps Electric Co., Ltd., Tokio/Tokyo | Electronic network module and a method for producing the same |
US4729010A (en) * | 1985-08-05 | 1988-03-01 | Hitachi, Ltd. | Integrated circuit package with low-thermal expansion lead pieces |
JPS6247153A (en) * | 1985-08-27 | 1987-02-28 | Ibiden Co Ltd | Semiconductor device |
GB2197540B (en) * | 1986-11-12 | 1991-04-17 | Murata Manufacturing Co | A circuit structure. |
JP2572823B2 (en) * | 1988-09-22 | 1997-01-16 | 日本碍子株式会社 | Ceramic joint |
JPH03194952A (en) * | 1989-12-22 | 1991-08-26 | Nec Corp | Ceramic package |
JPH04322452A (en) * | 1991-04-23 | 1992-11-12 | Mitsubishi Electric Corp | Semiconductor device housing container of semiconductor element manufacture of semicondcutor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4954418A (en) * | 1972-09-27 | 1974-05-27 | ||
JPS5389664A (en) * | 1977-01-19 | 1978-08-07 | Hitachi Ltd | Package structure of semiconductor device |
JPS55143042A (en) * | 1979-04-25 | 1980-11-08 | Hitachi Ltd | Semiconductor device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3646405A (en) * | 1969-01-08 | 1972-02-29 | Mallory & Co Inc P R | Hermetic seal |
JPS52116074A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Electronic part |
US4161743A (en) * | 1977-03-28 | 1979-07-17 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor device with silicon carbide-glass-silicon carbide passivating overcoat |
DE3064598D1 (en) * | 1979-11-05 | 1983-09-22 | Hitachi Ltd | Electrically insulating substrate and a method of making such a substrate |
-
1983
- 1983-01-21 JP JP58007306A patent/JPS59134852A/en active Granted
-
1984
- 1984-01-20 DE DE19843401984 patent/DE3401984A1/en not_active Ceased
- 1984-01-20 GB GB08401603A patent/GB2135513B/en not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4954418A (en) * | 1972-09-27 | 1974-05-27 | ||
JPS5389664A (en) * | 1977-01-19 | 1978-08-07 | Hitachi Ltd | Package structure of semiconductor device |
JPS55143042A (en) * | 1979-04-25 | 1980-11-08 | Hitachi Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
GB2135513B (en) | 1987-08-19 |
GB8401603D0 (en) | 1984-02-22 |
DE3401984A1 (en) | 1984-07-26 |
JPS59134852A (en) | 1984-08-02 |
GB2135513A (en) | 1984-08-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4651192A (en) | Ceramic packaged semiconductor device | |
US4965660A (en) | Integrated circuit package having heat sink bonded with resinous adhesive | |
US4517584A (en) | Ceramic packaged semiconductor device | |
US4897508A (en) | Metal electronic package | |
US4961106A (en) | Metal packages having improved thermal dissipation | |
EP0211618B1 (en) | Integrated circuit package | |
JPH0117258B2 (en) | ||
JP4227610B2 (en) | Manufacturing method of heat dissipation base | |
JPH0337308B2 (en) | ||
US3504096A (en) | Semiconductor device and method | |
JPS63174339A (en) | Integrated circuit chip packaging construction | |
JP3426827B2 (en) | Semiconductor device | |
JP2828553B2 (en) | Semiconductor device | |
JPS61256746A (en) | Semiconductor device | |
JPH0547953A (en) | Package for semiconductor device | |
JP2572092Y2 (en) | Semiconductor device package | |
JP3850312B2 (en) | Semiconductor element storage package and semiconductor device | |
JPH0548953B2 (en) | ||
JP2831219B2 (en) | Semiconductor device | |
JP3872391B2 (en) | Package for storing semiconductor elements | |
JP3752447B2 (en) | Package for storing semiconductor elements | |
JP3335657B2 (en) | Semiconductor package | |
JPS63215057A (en) | Semiconductor device and its manufacture | |
JP3292609B2 (en) | Package for storing semiconductor elements | |
JP2004259804A (en) | Vessel for housing electronic part |