GB2135513A - Packaged integrated circuit device - Google Patents
Packaged integrated circuit device Download PDFInfo
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- GB2135513A GB2135513A GB08401603A GB8401603A GB2135513A GB 2135513 A GB2135513 A GB 2135513A GB 08401603 A GB08401603 A GB 08401603A GB 8401603 A GB8401603 A GB 8401603A GB 2135513 A GB2135513 A GB 2135513A
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- integrated circuit
- packaged integrated
- circuit device
- thermal expansion
- expansion coefficient
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
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Abstract
A packaged integrated circuit device has an insulating substrate (4) of silicon carbide base, a cap (5) made of a material having a linear thermal expansion coefficient of 20 to 55x10<-7>/ DEG C and a sealing glass 6 having a linear thermal expansion coefficient of 30 to 55 x 10<-7>/ DEG C for sealing the cap with the substrate to define a small hermetic chamber. A semiconductor device (1) is mounted on the substrate (4), lead members (3) are introduced from the outside of the chamber, and wires (2) connect end portions (3a) of the lead members (3) to the semiconductor device (1). The semiconductor device, the end portions (3a) of the lead members (3) and the wires (2) are enclosed in the chamber. Suitable cap materials having a linear coefficient of expansion of 20 to 55 x 10-7/ DEG C are ceramics consisting mainly of silicon carbide, or mullite, or zircon, or silicon nitride. <IMAGE>
Description
SPECIFICATION
Packaged integrated circuit device
The present invention relates to a packaged integrated circuit device and, more particularly, to a packaged integrated circuit device having the characteristics with respect to the heat dissipation properties and matching of the thermal expansion coefficients of ceramics package materials.
Nowadays, there is broadly used an integrated circuit package or a packaged integrated circuit product having a structure such that a semiconductor device, end portions of lead members introduced from the outside, and wires by which both of them are electrically connected are enclosed in a small chamber which is hermetically surrounded by a package consisting of a sealing member, a cap and an insulating substrate of the ceramics or the like.
As the drawback when such a ceramics package is used, a problem is pointed out whereby the dissipation propertly of the heat produced in the semiconductor device is extremely bad. This point becomes a large obstacle to realize a highly integrated and miniaturized semiconductor device with large capacity.
Therefore, in integrated circuit packages, it is necessary that the ceramics to be used as the insulating substrate on which a semiconductor device is mounted has an excellent thermal conductivity as well as an electrical insulative property. In addition, as material for the substrate, it is desired to satisfy such conditions that the thermal expansion coefficient is analogous to that of the silicon semiconductor and that it has a large mechanical strength.
At present, a sintered alumina body is used as insulating substrate material which can satisfy these conditions to a certain extent. However, its thermal conductivity is low; i.e., about 0.5 cal/cm ~ sec ~ C. Therefore, the sintered alumina body is not a preferable material in viewpoint of the heat dissipation characteristic of the semiconductor device. On the other hand, as a proposition to improve the heat dissipation characteristic of the semiconductor device from the viewpoint of structure while utilizing the ceramic package, a method is known whereby the semiconductor device is mounted on a copper stud which penetrates through the insulating substrate and extends to the outside of the package.The semiconductor device is adhered to the copper stud through a supporting plate made of molybdenum for relieving the stress to be caused due to the difference between the thermal expansions of them in the package consisting of the substrate, cap and sealing material. This device is electrically connected through bonding wires to the end portions of lead members adhered onto the substrate. The heat generated in the semiconductor device is transferred to the outside of the package through the supporting plate and copper stud and is further dissipated by cooling fins. In such a structure, since the heat conduction paths from the semiconductor device to the cooling fins all consist of metal having an excellent thermal conductivity, the integrated circuit package having a high heat dissipation property can be obtained.
However on the contrary, this method has such drawbacks that: (1) the number of assembling processes becomes large since the number of parts increases and the structure is complicate; (2) the weight of the product becomes heavy since the parts having large specific gravities, such as copper, molybdenum, etc. are used, so that the attachment to a printed circuit board and the like becomes complicated.
To effect a development in such a situation, the present inventors have made various researches and developed a ceramics of silicon carbide base having a higher thermal conductivity than that of a conventional one and a thermal expansion coefficient which is similar to that of silicon in accordance with the conditions already described above, and enabled a packaged integrated circuit device having a good heat dissipation property to be manufactured by applying such a silicon carbide ceramics to the insulating substrate (Japanese Patent Application No. Sho. 56195986).
However, in association with the development of the research with respect to the application of the above substrate of silicon carbide material, when assembled a conventional cap made of alumina ceramic to this substrate, there occurred such a problem that the glass layer which is adhered and seals them may be cracked. This problem occurs due to the difference in thermal expansion between the ceramics of silicon carbide base and the alumina ceramics.
The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a cross sectional view of a packaged integrated circuit device according to an embodiment of the present invention;
Fig. 2 shows the relationship between the thermal expansion coefficient of the cap material and the maximum thermal stress to be caused in the sealing glass layer;
Fig. 3 shows the relationship between the thermal expansion coefficient of the sealing glass and the maximum thermal stress to be caused in this glass layer; and
Figs. 4, 5 and 6 are cross sectional views of packaged integrated circuit devices according to respective embodiments of the present invention.
It is an object of the present invention to complement the above-described proposition by limiting the thermal expansion coefficient of the cap material, thereby to provide a packaged integrated circuit device having excellent heat dissipation characteristic and further high stability and reliability.Namely, its feature is that the packaged integrated circuit device comprises; a small chamber hermetically surrounded by an insulating substrate of silicon carbide base, a cap and a sealing glass; a semiconductor device mounted on that substrate; lead members introduced from the outside of that chamber; and wires by which the semiconductor device and end portions of the lead members are electrically connected; the semiconductor device, the end portions and the wires being enclosed in that chamber; and the cap being made of a material having a thermal expansion coefficient of (20--55)x10-7/OC.
Furthermore, in the present invention, the glass having a linear thermal expansion coefficient of (3()-55)x 1 0-7/oc is recommended as the sealing material. In particular, the glass having a linear thermal expansion coefficient of (4O-55)x 1 0-7/0 C is actually applied.
In the present invention, the insulating substrate on which a semiconductor device is mounted is substantially the ceramics of silicon carbide base consisting of silicon carbide as main component and containing at least one selected from the group consisting of beryllium and beryllium compounds by an amount of 0.05-5 weight percent calculated on the basis of beryllium. In this specification, the expression "ceramic of A base" will mean a ceramic containing substance A as a main component.
This substrate consists of the sintered body having a relative density which is not lower than 90% of the theoretical density. Its linear thermal expansion coefficient is (35~40) x 10-7/OC and is close to the linear thermal expansion coefficient of silicon, while thermal conductivity is not lower than 0.2 cal/cm ~ sec ~ OC. This value of 0.2 cal/cm ~ sec ~ 0C of the thermal conductivity denotes the lower limit of the thermal conductivity to be obtained with a good reproductivity without adversely affecting the electrical insulative property (the resistivity being not lower than 107 cm) and the thermal expansion coefficient in the case where the ceramic of silicon carbide base is produced by way of sintering. In addition, this value is about four times the thermal conductivity of a conventional alumina ceramics substrate.Also, since the thermal expansion coefficient of the ceramics of silicon carbide base is close to that of silicon, when a semiconductor device is mounted to the insulating substrate through an adhesive agent layer, the thermal stress to be caused due to the difference between the thermal expansions of them is small.
Therefore, it is not necessary to interpose a stress releasing material as employed in some conventional devices between the substrate and the device. It is a fundamental condition to increase the heat dissipation property of the semiconductor device in the present invention that the ceramics having such characteristics is used as a constitutional material of the insulating substrate.
On the basis of this condition, it is a feature of the present invention that the cap for enclosing and sealing the semiconductor device and wirings on the insulating substrate consists of the material having a thermal expansion coefficient of (2O-55)x 10-7/OC. As such a material, it is possible to use ceramics of silicon carbide base which is the same material as the insulating substrate, ceramics of mullite base, ceramics of zircon base, ceramics of silicon nitride base, etc.
The use of the cap material having the abovementioned thermal expansion coefficient value allows the difference in expansion between the cap and the insulating substrate of silicon carbide base to be reduced by at least 1/3 or more as compared with the use of a conventional alumina ceramics (having a thermal expansion coefficient of about 65x 1 o-7/oC); therefore, the thermal stress which can be caused between the substrate and the cap is diminished in accordance with that reduction.
As a sealing glass material also, it is ideally desirable to have a thermal expansion coefficient approximately equal to the thermal expansion coefficient of the ceramics of silicon carbide base used as the insulating substrate and a value of (30-55)x 1 0-7/oc is appropriate. In addition, since the glass sealing is performed after the semiconductor device was adhered on the insulating substrate, glass having a high melting point is not fitted for use. Glass which can be sealed at temperatures below 5000C at most has to be selected for preventing adverse effects on the semiconductor device.
The use of the ceramics and glass having the above-mentioned characteristics as the insulating substrate, cap and sealing material, enables the resultant packaged integrated circuit device to have excellent heat dissipation characteristic and stability and high reliability and not to cause any cracks in the sealing portion and the abnormality in the electrical characteristic, even in the cooling from the sealing temperature to the room temperature and also even in case of repeating the cooling cycle between~55 to +1 500 C.
The present invention will now be described with respect to preferred embodiments.
Embodiment 1
Fig. 1 shows a cross sectional view of the packaged integrated circuit device according to an embodiment of the present invention. In the figure, a semiconductor device 1 is adhered by a metal solder layer 7 on a central portion of one surface 4a of an insulating substrate 4 consisting of ceramics of silicon carbide base. Each one end 3a of a plurality of lead members 3 adhered on that surface by a sealing glass layer 6 is electrically connected to the device 1 by a bonding wire 2. Each other end 3b of the lead members 3 extends outwardly from the periphery of the substrate 4. The device 1 , the bonding wires 2 and the end portions 3a of the lead members 3 are surrounded by the insulating substrate 4 and cap 5. The gaps between the cap 5 and the substrate 4 and between the cap 5 and the lead members 3 are hermetically sealed through the solder glass layer 6.
With such a structure, when a glass having a linear thermal expansion coefficient of (50 55)x 1 0-V0 C was used for sealing, the relationship was obtained by the calculation with respect to the change of the maximum thermal stress to be applied to the above glass in a temperature range from the sealing temperature to the room temperature depending upon the thermal expansion coefficient of the cap material.
This calculation was performed by regarding the package as a hollow disk model and dividing it into elements, and by using a finite element analytic program for three-dimensional axially symmetrical objects.
The result is shown in Fig. 2. Since the strength of the glass is about 4 kg/cm2, the ceramics having a thermal expansion coefficient of 55x 1 0-7/oc or more is not fitted as a cap material because the glass will crack.
As a material having a linear thermal expansion
coefficient (~) of (20-55)x10-7/0C, such materials are used as the previously-mentioned ceramics of silicon carbide base (a=(35-4O)x 10-7/OC), ceramics of mullite base a=(43-55)x 1 0-7/0C), ceramics of zircon base (a=(30--40)x 10-7/OC), a certain kind of
ceramics of silicon nitride base (a=(20-35)x 1 0-7/0 C).
The ceramics of silicon carbide base used as the insulating substrate is a sintered body which substantially consists of silicon carbide and contains beryllium oxide of an amount of 0.05-5 weight % calculated on the basis of beryllium and which has a density of not lower than 90% of the theoretical density. It has such characteristics as an electrical insulative property of the resistivity (at the room temperature) of not lower than 1 03Q ~ cm, a thermal conductivity of 0.2-0.7 cal/cm ~ sec ~ OC, and a bending strength is not lower than 30 kg/mm2.
The packaged integrated circuit device obtained on the basis of such component materials as mentioned above has an insulative resistance of not lower than 108 Q between the
lead members and did not show the accident such as failure and the abnormality on the electrical characteristic when it was cooled from the sealing temperature (4600 C) to the room temperature and even after the tests of the repeated heat cycles of 1000 times between~55 to 1 500 C.
Embodiment 2
A packaged integrated circuit device was made in the manner fundamentally similar to
Embodiment 1.
The insulating substrate was made of the ceramics of silicon carbide base which consists of silicon carbide except some weight percent of beryllium (beryllium oxide being used) impurity inevitably mixed therein, and was formed of a
sintered body having a density of 98% of the theoretical density. As its characteristic properties, there were obtained the values, such as a specific gravity of about 3.2, a resistivity of 10'3sot ~ cm (at the room temperature), a thermal expansion coefficient of about 35x 1 o-7/oC (at 25#3000 C), a thermal conductivity of 0.6
cal/cm ~ sec ~ OC, and a bending strength of about
45 kg/mm2.
The cap was made of ceramics of mullite base
having a linear thermal expansion coefficient of 45x 1 0-V00.
When the glasses having various linear thermal
expansion coefficients were used to seal the
above insulating substrate and cap, the relation
ship between the maximum thermal stress to be
applied to the glass and its thermal expansion
coefficient was obtained in the manner similar to
the case of Fig. 2 of Embodiment 2. The result is
as shown in Fig. 3.
When the linear thermal expansion coefficient
of the glass exceeds 55 x10-7/OC, the glass is
subjected to an excessive stress and cracks. On
the other hand, the glass having a linear thermal
expansion coefficient of not larger than 55x 10-7 is merely subjected to a small thermal stress.
However, since it is impossible to obtain a glass
having a linear thermal expansion coefficient of
not larger than 30x 1 0-7/0 C and a low melting
point which is desired as a glass for sealing, such
material can not practically be employed.
Therefore, the glass having a linear thermal
expansion coefficient of (30-55)x 1 0-7/ C is
desirable.
Packaged integrated circuit devices were made
using the previously-mentioned insulating
substrate and cap, and the sealing glass having a
linear thermal expansion coefficient of (45~48) x 1 0-7/00 and a sealing temperature of 450--460"C.
The packaged integrated circuit devices
presented the characteristic values, such as an
insulative resistance of not lower than 1 our between the lead members, and a thermal
resistance of 12.5 oC/W between the semi
conductor device and the surface of the insulating
substrate. In addition, the device did not cause
the accident such as failure and the abnormality
on the electrical characteristic even after it was
subjected to the heat cycles between~55 to 1500C of 100 times.
Embodiment 3
In the packaged integrated circuit device
described in Embodiment 1, a cooling fin 9 made
of metal such as aluminium or the like was
attached to the insulating substrate 4, as shown
in Fig. 4. It is preferable that this fin 9 is adhered
by an adhesive agent of the epoxy resin series or
silicone resin series which is filled with thermally
conductive filler. In addition, the fin can be also
adhered by a solder to a desired metallized
portion on the insulating substrate of silicon
carbide base. With such a constitution, the
thermal resistance between the semiconductor
device and the outside atmospheric ambience
becomes 9.30C/W, which is further below 12.5 C/W of Embodiment 2. This value is about
20% lower than the thermal resistance of about 11 .50C/W of a conventional packaged integrated
circuit device.
Furthermore, as a modification, the substrate and fin can be integrally manufactured by the ceramics of silicon carbide base; this application enabled the thermal resistance of the packaged integrated circuit device to be reduced to 5.1 C/W. In addition, this packaged integrated circuit device did not cause the accident such as failure and the abnormality on the electrical characteristic even after it was subjected to the tests of the heat cycles between~55 to 1 5000 of 100 times.
Embodiment 4
The structure of the pac#kaged integrated circuit device of the present invention is not limited to the above-mentioned embodiments.
Various modifications are possible. Examples (cross sections) are shown in Figs. 5 and 6. The semiconductor device 1 is adhered through a metallized layer 8 to the central portion of the inside bottom surface of the insulating substrate 4 which was molded like a box. The lead members 3 are electrically connected at each one end to the semiconductor device 1 by bonding wires 2, while each other end is pulled out along the inside surface of the insulating substrate to the substrate periphery and is adhered to a lead frame 10 through a solder layer 7'. The lid-like cap 5 is put in the opening portion of the substrate 4. The gap among the substrate, the cap and the lead members is sealed by the glass 6.
The insulating substrate was made of the ceramics of silicon carbide base containing 0.05-5 weight % of beryllium while the cap was made of the ceramics of mullite base having a thermal expansion coefficient of 45 x 1 0-7/00. For the sealing, a glass having a linear thermal expansion coefficient of 47x10-7/OC and a sealing temperature of 46000 was used.
The packaged integrated circuit device manufactured withstood the tests of the heat cycles between~55 to 1 5000 of 100 times and did not cause the failure and the abnormality on the electrical characteristic.
Claims (13)
1. A packaged integrated circuit device comprising: an insulating substrate of silicon carbide base, a cap and a sealing glass sealing said cap with said substrate to define a small hermatic chamber; a semiconductor device mounted on said substrate; lead members introduced from the outside of said chamber; wires by which said semiconductor device and end portions of said lead members are electrically connected; said device, said end portions and said wires being enclosed in said chamber; and said cap being made of ceramics having a thermal expansion coefficient of (20-55)x 10-7/00.
2. A packaged integrated circuit device according to claim 1, wherein said sealing glass has a thermal expansion coefficient of (30-55)x 10-7/00.
3. A packaged integrated circuit device according to claim 1, wherein the constitutional material of said cap is at least one kind selected from the group consisting of ceramics of mullite base, silicon carbide base, zircon base, and silicon nitride base.
4. A packaged integrated circuit device according to claim 1, wherein said insulating substrate has a thermal conductivity of not lower than 0.2 cal/cm ~ sec ~ C at room temperature, a thermal expansion coefficient of (3 5--40)x 1 0-7/0 C and an electrically insulative 'property.
5. A packaged integrated circuit device according to claim 1 , wherein said insulating substrate is a sintered body which substantially consists of silicon carbide and contains at least one selected from the group consisting of beryllium and beryllium compounds by an amount of 0.05-5 weight percent calculated on the basis of beryllium and it has a density of not lower than 90% of the theoretical density.
6. A packaged integrated circuit device according to claim 1, further comprising a cooling fin adhered onto the back surface of said insulating substrate on the front surface of which said semiconductor device is mounted.
7. A packaged integrated circuit device comprising: an insulating substrate of silicon carbide base a cap and a sealing glass sealing said cap with said substrate to define a small hermatic chamber; a semiconductor device mounted on said substrate; lead members introduced from the outside of said chamber; and wires by which end portions of said lead members and said semiconductor device are electrically connected; said device, said end portions and said wires being enclosed in said chamber; the constitutional material of said cap having a thermal expansion coefficient of (20-55)x 1 0-7/oc and said glass (6) having a thermal expansion coefficient of (30-55)x 10-7/00.
8. A packaged integrated circuit device according to claim 7, wherein the constitutional material of the cap is at least one selected from the group consisting of ceramics of mullite base, silicon carbide base, zircon base, and silicon nitride base.
9. A packaged integrated circuit device according to claim 7, wherein said insulating substrate is a sintered body which substantially consists of silicon carbide and contains at least one selected from the group consisting of beryllium and beryllium compounds by an amount of 0.05-5 weight percent calculated on the basis of beryllium and the sintered body has a relative density of not lower than 90% of the theoretical density, a thermal conductivity of not lower than 0.2 callcm ~ sec ~ C at the room temperature, and a thermal expansion coefficient of (35-40)x 1 o-7/oC and has an electrical insulative property.
10. A packaged integrated circuit device according to claim 7, further comprising a cooling fin adhered onto the back surface of said insulating substrate on the front surface of which said semiconductor device is mounted.
11. A packaged integrated circuit device according to claim 2, wherein said insulating substrate has a thermal conductivity of not lower than 0.2 cal/cm ~ sec #O C at the room temperature a thermal expansion coefficient of (35-40)x 1 0-7/ C and an electrically insulative property.
12. A packaged integrated circuit device according to claim 3, wherein said insulating substrate has a thermal conductivity of not lower than 0.2 cal/cm ~ sec ~ C at room temperature, a thermal expansion coefficient of (3 5--40)x 1 0-7/oc and an electrically insulative property.
13. A packaged integrated circuit device substantially as herein described with reference to and as illustrated in any one of Figures 1, and 4 to 6 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58007306A JPS59134852A (en) | 1983-01-21 | 1983-01-21 | Integrated circuit package |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8401603D0 GB8401603D0 (en) | 1984-02-22 |
| GB2135513A true GB2135513A (en) | 1984-08-30 |
| GB2135513B GB2135513B (en) | 1987-08-19 |
Family
ID=11662323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08401603A Expired GB2135513B (en) | 1983-01-21 | 1984-01-20 | Packaged integrated circuit device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS59134852A (en) |
| DE (1) | DE3401984A1 (en) |
| GB (1) | GB2135513B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2197540A (en) * | 1986-11-12 | 1988-05-18 | Murata Manufacturing Co | Circuit substrate |
| US5138426A (en) * | 1988-09-22 | 1992-08-11 | Ngk Insulators, Ltd. | Ceramic joined body |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3603912A1 (en) * | 1985-02-09 | 1986-08-14 | Alps Electric Co., Ltd., Tokio/Tokyo | Electronic network module and a method for producing the same |
| US4729010A (en) * | 1985-08-05 | 1988-03-01 | Hitachi, Ltd. | Integrated circuit package with low-thermal expansion lead pieces |
| JPS6247153A (en) * | 1985-08-27 | 1987-02-28 | Ibiden Co Ltd | Semiconductor device |
| JPH03194952A (en) * | 1989-12-22 | 1991-08-26 | Nec Corp | Ceramic package |
| JPH04322452A (en) * | 1991-04-23 | 1992-11-12 | Mitsubishi Electric Corp | Semiconductor device housing container of semiconductor element manufacture of semicondcutor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3646405A (en) * | 1969-01-08 | 1972-02-29 | Mallory & Co Inc P R | Hermetic seal |
| JPS4954418A (en) * | 1972-09-27 | 1974-05-27 | ||
| JPS52116074A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Electronic part |
| JPS5389664A (en) * | 1977-01-19 | 1978-08-07 | Hitachi Ltd | Package structure of semiconductor device |
| US4161743A (en) * | 1977-03-28 | 1979-07-17 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor device with silicon carbide-glass-silicon carbide passivating overcoat |
| JPS55143042A (en) * | 1979-04-25 | 1980-11-08 | Hitachi Ltd | Semiconductor device |
| EP0028802B1 (en) * | 1979-11-05 | 1983-08-17 | Hitachi, Ltd. | Electrically insulating substrate and a method of making such a substrate |
-
1983
- 1983-01-21 JP JP58007306A patent/JPS59134852A/en active Granted
-
1984
- 1984-01-20 GB GB08401603A patent/GB2135513B/en not_active Expired
- 1984-01-20 DE DE19843401984 patent/DE3401984A1/en not_active Ceased
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2197540A (en) * | 1986-11-12 | 1988-05-18 | Murata Manufacturing Co | Circuit substrate |
| US4800459A (en) * | 1986-11-12 | 1989-01-24 | Murata Manufacturing Co., Ltd. | Circuit substrate having ceramic multilayer structure containing chip-like electronic components |
| GB2197540B (en) * | 1986-11-12 | 1991-04-17 | Murata Manufacturing Co | A circuit structure. |
| US5138426A (en) * | 1988-09-22 | 1992-08-11 | Ngk Insulators, Ltd. | Ceramic joined body |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8401603D0 (en) | 1984-02-22 |
| GB2135513B (en) | 1987-08-19 |
| JPH0117258B2 (en) | 1989-03-29 |
| JPS59134852A (en) | 1984-08-02 |
| DE3401984A1 (en) | 1984-07-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |