JPH01168043A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01168043A JPH01168043A JP32588087A JP32588087A JPH01168043A JP H01168043 A JPH01168043 A JP H01168043A JP 32588087 A JP32588087 A JP 32588087A JP 32588087 A JP32588087 A JP 32588087A JP H01168043 A JPH01168043 A JP H01168043A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- deposited
- substrate
- polysilicon
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000010408 film Substances 0.000 abstract description 13
- 239000010409 thin film Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置のコンタクトホールの形成過程に
おける製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a manufacturing method in the process of forming contact holes in a semiconductor device.
従来の技術 以下に、従来の半導体装置について説明する。Conventional technology A conventional semiconductor device will be described below.
第２図ａｘｄは従来の半導体装置の工程順断面図である
。第２図ａのように、トランジスタ形成後のシリコン（
Ｓｉ）基板１上に、ポリシリコン電極配線２を有する下
地に、ＣＶＤ法による酸化膜３を堆積し、ホトレジスト
によるパターンニングを行い、ドライエッチにより、所
定の箇所に第１のコンタクトホールを形成する。FIG. 2axd is a cross-sectional view of a conventional semiconductor device in the order of steps. As shown in Figure 2a, the silicon (
Si) On the substrate 1, an oxide film 3 is deposited by CVD on a base having polysilicon electrode wiring 2, patterned with photoresist, and a first contact hole is formed at a predetermined location by dry etching. .
次に、第２図すのように、ポリシリコン５を堆積し、不
純物を拡散し、タングステンシリサイド（ＷＳｉ）膜６
を蒸着し、ホトレジスト、ドライエッチによりパターン
ニングを行う。ついで、第２図Ｃのように、ＣＶＤ法に
より酸化膜７を堆積する。Next, as shown in FIG. 2, polysilicon 5 is deposited, impurities are diffused, and a tungsten silicide (WSi) film 6 is deposited.
is deposited and patterned using photoresist and dry etching. Then, as shown in FIG. 2C, an oxide film 7 is deposited by the CVD method.
さらに、第２図ｄのように、第１のコンタクトホール以
外の箇所に第２のコンタクトホールを形成し、アルミ合
金８を蒸着する。Furthermore, as shown in FIG. 2d, a second contact hole is formed at a location other than the first contact hole, and aluminum alloy 8 is deposited.
以上のａ−ｄの工程によって半導体装置の製造を行って
いた。A semiconductor device was manufactured through the steps a to d above.
発明が解決しようとする問題点
しかしながら上記従来の方法では、第２のコンタクトホ
ール形成の際にＳｉ基板１の面に掘り込みが発生し、ま
た、フィールド酸化膜４下に注入されたチャネルストッ
パーとアルミ合金とが接触し、チャネルストッパーがＰ
型の場合には、素子分離の不備が生じるという問題点を
有していた。Problems to be Solved by the Invention However, in the conventional method described above, digging occurs in the surface of the Si substrate 1 when forming the second contact hole, and the channel stopper implanted under the field oxide film 4 also The channel stopper is in contact with the aluminum alloy and the channel stopper is P.
In the case of a mold, there is a problem in that element isolation is insufficient.
本発明は上記従来の問題点を解決するもので、コンタク
トホール形成時に生ずるＳｔの基板の掘れをなくすと同
時に、薄ｍｇ域とコンタクトホールの重ね合わせマージ
ンを大きくすることができる半導体装置の製造方法を提
供することを目的とする。The present invention solves the above-mentioned conventional problems, and is a method for manufacturing a semiconductor device that can eliminate the digging of the St substrate that occurs when forming contact holes, and at the same time increase the overlapping margin between the thin mg region and the contact hole. The purpose is to provide
問題点を解決するための手段
この目的を達成するために、本発明の半導体装置の製造
方法は、第２のコンタクトホール形成の箇所にあらかじ
め、第１のコンタクトホールと同時形成した第２のコン
タクトホールを形成し、第１のコンタクトホールおよび
第２のコンタクトホール内にポリシリコンを堆積し、Ｎ
型基板に対してはリン、ヒ素、Ｐ型基板に対してはボロ
ンを拡散し、タングステンシリサイドを堆積するもので
ある。Means for Solving the Problems In order to achieve this object, the method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device in which a second contact hole is formed simultaneously with the first contact hole in advance at the location where the second contact hole is to be formed. forming holes, depositing polysilicon in the first contact hole and the second contact hole, and depositing polysilicon in the first contact hole and the second contact hole;
For a type substrate, phosphorus and arsenic are diffused, and for a P type substrate, boron is diffused and tungsten silicide is deposited.
作用
この構成によって、コンタクトホール形成時のＳｉ基板
の掘れおよびポリシリコン堆積後の不純物拡散によって
薄膜領域と第２のコンタクトホールの重ね合わせマージ
ンが大きくなる。Effect: With this configuration, the overlapping margin between the thin film region and the second contact hole becomes large due to the trenching of the Si substrate during formation of the contact hole and the diffusion of impurities after polysilicon deposition.
実施例
以下に本発明の一実施例について図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図ａ−ｄは、本発明の一実施例における半導体装置
の製造方法を示す工程順断面図であり、基板１内にトラ
ンジスタを形成し、ポリシリコン配線２を設けた後に、
ＣＶＤ法による酸化膜３を堆積し、フォトレジスト５を
用いて、第１．第２のコンタクトホール形成のためのパ
ターンニングを行う。1A to 1D are step-by-step cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. After forming a transistor in a substrate 1 and providing a polysilicon wiring 2,
An oxide film 3 is deposited by the CVD method, and a photoresist 5 is used to form the first. Patterning is performed to form a second contact hole.
次に、第１図すのように、第１のコンタクトホールと第
２のコンタクトホールとを開孔した後、ポリシリコンロ
を堆積し、基板１内にリンを拡散して、ｎ＋拡散層１２
を形成し、その後クンゲステンシリサイド（ポリサイド
）７を蒸着し、フォトレジスト９を用いてポリサイド７
のパターンニングを行う。この時、ポリサイド配線形成
と同時に、第２のコンタクトホールの形成箇所にも、第
１のコンタクトホール内と同様に、ポリシリコンロにポ
リサイド７を埋め込む。Next, as shown in FIG.
After that, Kungesten silicide (polycide) 7 is deposited, and a photoresist 9 is used to form polycide 7.
Perform patterning. At this time, at the same time as forming the polycide wiring, polycide 7 is embedded in the polysilicon at the location where the second contact hole is to be formed, similarly to the inside of the first contact hole.
次いで、第１図Ｃのように、ＣＶＤ法による酸化膜１１
を堆積した後、フォトレジストを用いて第２のコンタク
トホール部のパターンニングを行う。Next, as shown in FIG. 1C, an oxide film 11 is formed by CVD.
After depositing, patterning of the second contact hole portion is performed using a photoresist.
そして、第１図ｄのように、第２のコンタクトホール形
成後、アルミニウム合金１０を蒸着する。ここで、アル
ミニウム合金１０と基板１との接触は、ポリシリコンロ
、ポリサイド７を介して行うことになる。Then, as shown in FIG. 1d, after forming the second contact hole, an aluminum alloy 10 is deposited. Here, the aluminum alloy 10 and the substrate 1 are brought into contact via polysilicon or polycide 7.
発明の効果
以上のように本発明によると、第２のコンタクトホール
を第１のコンタクトホールを開孔する際に同時形成し、
内部にポリサイドを埋め込むことにより、第２のコンタ
クトホール形成時のＳｉ基板の掘り込みを防止するとと
もに、第２のコンタクトホールと薄膜領域との重ね合わ
せマージンを増大することができる。Effects of the Invention As described above, according to the present invention, the second contact hole is formed simultaneously when the first contact hole is formed,
By embedding polycide inside, it is possible to prevent digging into the Si substrate when forming the second contact hole and to increase the overlapping margin between the second contact hole and the thin film region.
第１図ａ−ｄは本発明の一実施例方法を示す工程順断面
図、第２図ａ−ｄは本発明実施例の工程順断面図である
。
１・・・・・・Ｓｉ基板、２・・・・・・ポリシリコン
、３・・・・・・ＣＶＤ法による酸化膜、４・・・・・
・フィールド酸化膜、５・・・・・・ポリシリコン、６
・・・・・・タングステンシリサイド膜、７・・・・・
・ＣＶＤ法による酸化膜、８・・・・・・アルミニウム
合金膜。
代理人の氏名 弁理士 中尾敏男 ほか１名１ −−
Ｓ ｉ 幕榎
４− フィル酸化酸化臘
■−一一一一一一一1A to 1D are step-by-step sectional views showing a method according to an embodiment of the present invention, and FIGS. 2A to 2D are step-by-step sectional views of an embodiment of the present invention. 1... Si substrate, 2... Polysilicon, 3... Oxide film by CVD method, 4...
・Field oxide film, 5...Polysilicon, 6
...Tungsten silicide film, 7...
- Oxide film by CVD method, 8... Aluminum alloy film. Name of agent: Patent attorney Toshio Nakao and 1 other person 1 --
S i Makueno 4- Phil oxidation oxidation ■-1111111
Claims (1)
した後にＣＶＤ法による酸化膜を堆積する工程と、前記
酸化膜に第１のコンタクトホールを形成する工程と、ポ
リシリコンをＣＶＤ法により堆積する工程と、不純物を
拡散する工程と、タングステンシリサイドを蒸着する工
程とホトレジストを用いてコンタクトホール内にポリサ
イドを埋め込む工程と、ＣＶＤ法により酸化膜を堆積す
る工程と第２のコンタクトホールをポリサイドを埋め込
んだ第１のコンタクトホールと同一箇所に開孔する工程
とアルミ合金膜を蒸着する工程を含んでなる半導体装置
の製造方法。In the manufacturing process of a semiconductor device, after forming a transistor, a step of depositing an oxide film by CVD method, a step of forming a first contact hole in the oxide film, a step of depositing polysilicon by CVD method, and an impurity a step of vapor depositing tungsten silicide; a step of embedding polycide into the contact hole using photoresist; a step of depositing an oxide film by CVD; A method for manufacturing a semiconductor device comprising the steps of forming a hole in the same location as a contact hole and depositing an aluminum alloy film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32588087A JPH01168043A (en) | 1987-12-23 | 1987-12-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32588087A JPH01168043A (en) | 1987-12-23 | 1987-12-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01168043A true JPH01168043A (en) | 1989-07-03 |
Family
ID=18181642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32588087A Pending JPH01168043A (en) | 1987-12-23 | 1987-12-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01168043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8304807B2 (en) | 2002-12-31 | 2012-11-06 | Intel Corporation | Low-capacitance electrostatic discharge protection diodes |
-
1987
- 1987-12-23 JP JP32588087A patent/JPH01168043A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8304807B2 (en) | 2002-12-31 | 2012-11-06 | Intel Corporation | Low-capacitance electrostatic discharge protection diodes |
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