JPH01167042U - - Google Patents
Info
- Publication number
- JPH01167042U JPH01167042U JP6385488U JP6385488U JPH01167042U JP H01167042 U JPH01167042 U JP H01167042U JP 6385488 U JP6385488 U JP 6385488U JP 6385488 U JP6385488 U JP 6385488U JP H01167042 U JPH01167042 U JP H01167042U
- Authority
- JP
- Japan
- Prior art keywords
- package
- circuits
- separated
- stepped portion
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の電子部品用パツケージの一部
省略平面図、第２図は第１図のパツケージの一部
拡大平面図、第３図は第２図のパツケージのＡ―
Ａ断面図、第４図ないし第１０図は従来の電子部
品用パツケージのインデツクスマークやターゲツ
トマークを備えた部分の拡大平面図である。 １，１００……パツケージ、２……キヤビテイ
、３……段差部、４，４ａ……回路、５……イン
デツクスマーク、６……ターゲツトマーク、８…
…ワイヤ、１２……内部回路。
省略平面図、第２図は第１図のパツケージの一部
拡大平面図、第３図は第２図のパツケージのＡ―
Ａ断面図、第４図ないし第１０図は従来の電子部
品用パツケージのインデツクスマークやターゲツ
トマークを備えた部分の拡大平面図である。 １，１００……パツケージ、２……キヤビテイ
、３……段差部、４，４ａ……回路、５……イン
デツクスマーク、６……ターゲツトマーク、８…
…ワイヤ、１２……内部回路。
Claims (1)
- キヤビテイ内の段差部表面に複数の回路を形成
したパツケージにおいて、上記段差部表面の一部
の回路の中途部を分断するとともに、該分断した
回路の中途部間を上記パツケージ内部に形成した
内部回路で電気的に接続してなる電子部品用パツ
ケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6385488U JPH0622989Y2 (ja) | 1988-05-13 | 1988-05-13 | 電子部品用パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6385488U JPH0622989Y2 (ja) | 1988-05-13 | 1988-05-13 | 電子部品用パッケージ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01167042U true JPH01167042U (ja) | 1989-11-22 |
| JPH0622989Y2 JPH0622989Y2 (ja) | 1994-06-15 |
Family
ID=31289342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6385488U Expired - Lifetime JPH0622989Y2 (ja) | 1988-05-13 | 1988-05-13 | 電子部品用パッケージ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622989Y2 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014027585A (ja) * | 2012-07-30 | 2014-02-06 | Seiko Epson Corp | 電子部品の製造方法および電子モジュールの製造方法 |
-
1988
- 1988-05-13 JP JP6385488U patent/JPH0622989Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014027585A (ja) * | 2012-07-30 | 2014-02-06 | Seiko Epson Corp | 電子部品の製造方法および電子モジュールの製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622989Y2 (ja) | 1994-06-15 |