JPH01166220A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve the efficiency of each of different processes by adding a constant to the address of a microinstruction which designates execution of the processing of a common part and producing a return address after execution of said processing based on the result of said addition and the condition selecting information. CONSTITUTION:A constant 2 or 4 corresponding to the number of bits of the conditional value 9 received from a conditioned flip-flop selected by a selector 8 is added by an address adder 6 to the address of a subroutine call instruction stored in a microinstruction address register 5. A return address is set after execution of a subroutine based on the result of said addition and the value 9. In such constitution, the different types of processes can be carried out just after a resetting state from the subroutine based on the conditions set previously after execution of the common processing and without holding the contents of the conditional flip-flop after execution of the common processings.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device, and more particularly to creating a return address for a subroutine in a microprogram.

Traditionally, in microprogram control devices, when processing for multiple events includes common processing, the common processing is made into a subroutine, and this subroutine is called and used in each processing. ,
Alternatively, a method is generally adopted in which the main routine is shared and only the relevant part of the process performs a conditional branch by determining the value set in a conditional flip-flop, and the conditional branch performs a different process.

In other words, as shown in Figure 3, there is a method in which one condition is branched and a common process is performed at each conditional branch destination, and then different processes are performed.As shown in Figure 4, a common process is performed and then different processes are performed depending on the conditional branch. There are several methods for processing.

In the method shown in Figure 3, the internal or external state is read by a microprogram, the read state is determined after common processing is performed, and when branching to a different process depending on the condition, the The read state is set in the conditional flip-flop, the content set in the conditional flip-flop is judged, and branching is performed (Step 3 in Figure 3).
0-32).

When the contents set in the conditional flip-flops are A to C, other processing is performed (Steps 33, 37, and 41 in Figure 3).
), the same subroutine for common processing is called (steps 34, 38, 4.2 in FIG. 3), and after executing the same subroutine for common processing (steps 35 to 39 in FIG. 3). 43) and perform different processing for each (
Steps 36, 40 and 44 in Figure 3), and when the content set in the conditional flip-flop is D, the same subroutine for common processing is called (Step 45 in Figure 3).
) After executing the same subroutine for common processing (
(Step 46 in Figure 3), different processing is being performed (Step 46 in Figure 3).
Figure step 47).

In addition, in the method shown in Figure 4, the internal or external state is read by a microprogram, the read state is judged after common processing is performed, and when branching to a different process depending on the condition, , set the read state to the conditional flip-flop (step 50 in Figure 4).
, after performing common processing (step 51 in FIG. 4), determines the contents set in the conditional flip-flop and branches (steps 52 and 53 in FIG. 4), and then determines the contents set in the conditional flip-flops A to A. Different processes are performed depending on D (steps 54 to 57 in FIG. 4).

At this time, the contents set in the conditional flip-flop (
The read value (which is the basis for condition determination) is held until the common processing is completed.

In conventional conditional branching methods like this, when a conditional branch is executed and a common process is performed at each conditional branch destination to perform different processing, the microprogram step to call the same subroutine after the conditional branch is set as a condition. Since it must be provided at each branch destination, the number of steps in the microprogram increases, and there is a drawback in terms of performance that the subroutine cannot be executed immediately.

In addition, when performing a common process and then performing a different process by conditional branching, it is necessary to hold the contents set in the conditional flip-flop (the read value for condition judgment) while the common process is being executed. There are restrictions.

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the drawbacks of the conventional methods as described above.The present invention has been made in order to eliminate the drawbacks of the conventional methods as described above. The object of the present invention is to provide a microprogram control device that can execute different processes depending on the specified conditions.

Structure of the Invention A microprogram control device according to the present invention executes a plurality of microprograms including a common part, and executes processing other than the common part according to condition selection information given to each of the plurality of microprograms. A microprogram control device, comprising an addition means for adding a predetermined constant to an address of a microinstruction that instructs execution of processing of the common part, and an addition means corresponding to the addition result of the addition means and the condition selection information. The present invention is characterized by comprising a generating means for generating a return address after execution of the processing of the common portion based on a preset condition value.

艮1 Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. Control circuit 3 and selector 4.8
, a microinstruction address register 5 , an address adder 6 , and a return address register 7 .

The microinstruction stored in the microinstruction register 2 has a condition selection field 21, an order control field 22,
It is configured to include an operation and other control field 23 and a next execution address field 24.

The order control circuit 3 controls the next execution address according to the contents of the order control field 22 of the microinstruction stored in the microinstruction register 2, so that the sequence control circuit 3 controls the next execution address from a condition flip-flop (not shown) selected according to the contents of the condition selection field 21. Depending on whether the condition value 9 is 1 bit or 2 bits, r2° or "4" is output to the address adder 6 as a constant value.

Selector 4 is microinstruction register 2 for normal branch instructions.
The next execution address in the next execution address field 24 of the microinstruction stored in the subroutine is selected, and the return address stored in the return address register 7 is selected when a return instruction is executed in a subroutine.

The microinstruction address register 5 stores the microinstruction address (next execution address or return address) from the selector 4 and outputs this microinstruction address to the control storage device 1 and the address adder 6.

Address adder 6 adds the constant value from sequence control circuit 3 to the microinstruction address from microinstruction address register 5 and outputs the result to return address register 7.

The selector 8 selects one of the condition values 9 from the condition flip-flop according to the contents of the condition selection field 21 of the microinstruction stored in the microinstruction register 12 and outputs it to the return address register 7.

Note that Figure 1 does not illustrate all the functions necessary for microprogram control, and may include conditional branching used in conventional microprogram control devices, or setting 1 to the address of a microinstruction being executed in a normal subroutine call. The function of setting the added contents in the return address register 7 is omitted.

FIG. 2 is a flowchart of a microprogram for explaining the operation of one embodiment of the present invention.

In the figure, after reading an external signal (step 10 in FIG. 2) and executing common processing (steps 11 to 13 in FIG. 2), the state fiA of 2 bits of the read external signal is ~D shows a microprogram that performs four different processes.

The operation of one embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

First, at address 100, a microinstruction is issued to set an external signal to the conditional flip-flop, and the process proceeds to address 101 (step 10 in FIG. 2). Here, the set instruction to the conditional flip-flop is instructed by the operation and other control field 23 of the microinstruction stored in the microinstruction read register 2.

At the next address 101, 2 bits of the condition value 9 set in the conditional flip-flop are specified, and a conditional return address set instruction (RAR option) and subroutine "s" are specified.
Subroutine call instruction to read ua s” (LL to C
5t18S) is described (step 11 in FIG. 2).

The conditional return address set instruction is specified by the order control field 22, and the microinstruction address stored in the microinstruction address register 5 and "4" as a constant value from the order control circuit 3 are added to the address adder 6.
[101+4 = 105 (011
01001″)], the adder is output to the return address register 7.

On the other hand, the 2-bit condition value 9 from the condition flip-flop selected by the selector 8 according to the contents of the condition selection field 21 [“00′, “01”.

“io” or “11”] is set in the lower two bits of the return address register 7. Also,
The upper bits of the return address register 7 contain the value of the output from the address adder 6 excluding the lower 2 bits [“01
1010"] is selected, and as a result, the 2-bit condition value from the condition flip-flop selected by the selector 8 results in selecting ["011010" among addresses 104 to 107.
00", "01101001", "01101010
”.

Any address among "01101011'" is sent to the return address register 7 (step 12 in FIG. 2).

By the subroutine call instruction, the start address of the subroutine is specified by the next execution address field 24, selected by the selector 4, and supplied from the microinstruction address register 5 to the control storage device 1, so that this subroutine is executed (the subroutine is executed). Figure 2 Step 13).

When a return instruction is specified by the order control field 22 at the end of the subroutine, the output from the return address register 7 is selected by the selector 4 and addresses 104 to 10 are selected.
After the execution of the microinstruction processing step of any one of the microinstruction processing steps at the address No. 7, that is, the common process °, execution is started according to states A to D (steps 14 to 17 in FIG. 2).

In this way, at address 100 of the subroutine call instruction stored in the microinstruction address register 5,
A constant value (“2” or “4”) corresponding to the number of bits of condition fM9 from condition flip 70 selected by selector 8.
) is added by the address adder 6, and this addition result is combined with the condition fi! from the condition flip-flop selected by the selector 8.
! By setting the return address after subroutine execution using 9 and 9, the contents of the conditional flip-flop (read value for condition judgment) are not held during common processing, and the return address can be set after returning from the subroutine, that is, when the return instruction is executed. Upon instruction, different processes can be executed immediately after the common process according to states A to D.

As described above, according to the present invention, a predetermined constant is added to the address of a microinstruction that instructs the execution of processing of a common part included in a plurality of microprograms,
By generating the return address after executing the processing of the common part using the addition result and the condition value set in advance corresponding to the condition selection information given to each of the plurality of microprograms, the common part This has the advantage that different processes can be executed in accordance with preset conditions immediately after returning from the subroutine without holding read values for condition determination during execution of the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a flowchart of a microprogram for explaining the operation of an embodiment of the present invention, and FIGS. 3 and 4 are conventional examples. 2 is a flowchart of a microprogram. Explanation of symbols of main parts 1... Control storage device 2... Micro instruction read register 3...
... Sequence control circuit 4.8 ... Selector 5 ... Microinstruction address register 6 ...
... Adder 7 ... Return address register 9 ... Condition value 21 ... Condition selection field 22 ... Order control field

Claims (1)

[Claims] A microprogram control device that executes a plurality of microprograms including a common part and executes processing other than the common part according to condition selection information given to each of the plurality of microprograms, an addition means for adding a predetermined constant to the address of a microinstruction that instructs execution of a process, and a condition value set in advance corresponding to the addition result of the addition means and the condition selection information to determine the common part. A microprogram control device comprising: generating means for generating a return address after execution of a process.