JPH01166155A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To operate with a sufficient margin by stopping a switching from the access signal of a CPU system to the access signal of a DMAC system for at least one clock before and after a non-synchronous DMAC is activated by synchronizing with the clock of the CPU. CONSTITUTION:A request signal of the switching to a DMAC 20 inputted to the R.REQ of an MB88867 102 of a CPU 10 is outputted as a permission signal R.GRNT to the DMAC 20 and inputted as the permission signal of an MB8861 201 of the DMAC 20. The inputted signal is delayed by one clock and inputted as a selection signal SEL to the S terminal of a selector 12. The signal of the 102 equivalent to a clock c1 of the CPU 10 and a signal 2DMA of the 201 equivalent to a clock c2 of the DMAC 20 are selected, outputted as an access clock c2 to a timing generating part 3, a read/write signal R/W1 of the CPU 10 to be inputted to an input terminal 2A and a read/write signal R/W2 of the DMAC 20 to be inputted to an input terminal 2B are selected and the read/write signal R/W2 of the DMAC 20 is outputted as a read/write signal for access from an output terminal 2Y of the selector 12 to the timing generating part 3.

Description

[Detailed Description of the Invention] [Summary] Memory access control in which the direct memory access controller DMAC, which operates asynchronously with the CPU, controls access timing for accessing the memory or input/output device I10 that coexists with the CPU. Regarding the circuit, when an asynchronous DMAC accesses the shared memory, the switching is pseudo-synchronized with the CPU access, and the purpose of the DMAC is to ensure that read/write operations of the shared memory are performed correctly with a margin. At startup, the DMAC clock C2 is
The clock c2 of the DMAC is controlled by the clock c1 of the DMAC.
It generates a control signal SEL that stops for one clock period, and outputs the clock cl from the CPU and the read/write signal R/W.
1 is switched to the clock C2 from the DMAC and the read/write signal R/W2, and the access clock c2. R/W2
a clock system switching circuit that outputs the access clock c2. a timing generation circuit that generates an access signal t for accessing the shared memory by inputting the R/W2;
The access signal t is configured to stop in synchronization with the CPU clock c1 for at least one clock period before and after the activation of the DMAC when switching from a CPU system signal to a DMAC system signal.

[Industrial Application Field] The present invention provides a system for determining the access timing when a direct memory access controller DMAC that operates asynchronously with the CPU accesses the memory or input/output device I10 shared with the CPU in a certain CPU system. This is related to the memory access control circuit that controls the memory access control circuit, and when the asynchronous DMAC accesses the memory, the switching is pseudo-synchronized with the CPU access, and the read/write operation of the shared memory or Ilo has a margin. It is desirable to ensure that the process is carried out correctly.

[Conventional technology]

A conventional memory access control circuit is shown in FIG.
, when the CPU IOA and the DMAC 20A, which operate asynchronously with the CPU IOA, use independent clocks to access the shared memory of the system or the T1030A, in addition to the asynchronous DMAC 20A, the CPU IO
Another DMAC 40A that operates in synchronization with A, and a buffer register 50A that temporarily stores and relays transfer data between the synchronous DMAC 40A and the asynchronous DMAC 2OA, and between the synchronous DMAC 40A or the CPU 108 and the memory 30A. It is set up.

[Problem that the invention seeks to solve]

As mentioned above, the conventional memory access control circuit
When the DMAC 2OA, which operates asynchronously with the IOA, reads and writes data to the shared memory 30A on the system, it uses another DMAC 40A, which operates synchronously with the CPU IOA, and a buffer register 50A, which temporarily stores the transferred data. Since this is done through an intermediary, there is a problem that the circuit size increases due to the sending and receiving of address codes associated with data transfer, which increases costs.In order to avoid this, the CPU IOA and the asynchronous DMAC2OA are directly connected to the shared memory When accessing the shared memory 30A, there is a problem that since independent clocks are used, there is no guarantee that the reading/writing of the shared memory 30A will be performed correctly.

[Means for solving problems]

This problem arises when switching from the CPU 10's access to the memory 30 to the asynchronous DMAC 20's access, in the clock system switching circuit 1, the clock c2 of the DMAC 20 is controlled by the clock cl of the CPU 10 for a period equivalent to one clock of the clock c2. A control signal SEL is generated to stop the CPU by the control signal SEL.
The clock c1 and read/write signal R/W2 from the DMAC 20 are switched and outputted to the clock c2 and read/write signal R/W2 from the DMAC 20. Then, in the timing generation circuit 2, an access signal t for the memory or Ilo 30 is generated based on the access clock c2 output from the clock system switching circuit 1 and the read/write signal R/W2.
, and the access signals t1 to D of the CPU 10 system are generated.
The switching to the access signal t2 of the MAC 20 system is stopped in synchronization with the clock c1 of the CPU 10 for at least one clock before and after the asynchronous DMAC 20 is activated, so that read/write operations to the memory 30 are guaranteed. This problem is solved by the configuration of the present invention.

In the principle diagram of FIG. 1 showing the configuration of the memory access control circuit of the present invention, 1 indicates that when the asynchronous DMAC 20 is activated, the CPU io
The clock c1 from the CPU 10 is controlled by the clock c2 of the DMAC 20 to generate a control signal SEL that stops the clock c2 for one clock period.

The read/write signal R/Wl is input to the clock c2. The clock system switching circuit 2 switches to the read/write signal R/W2 and outputs the read/write signal R/W2.
and a timing generation circuit that generates an access signal t for accessing a memory 30 shared by the DMAC 20, and which generates an access signal t of the CPU 10 systems of the output t of the timing generation circuit 2 to an access signal t of the DMAC 20 systems.
The switching to 2 is configured such that at least one clock before and after the DMAC 20 starts is stopped in synchronization with the clock c1 of the CPU 10.

[Effect]

When the asynchronous DMAC 20 is activated, the clock system switching circuit 1 controls the clock c1 of the CPU 10 by the clock c2 of the DMAC 20, generates a control signal SEL that stops the clock c2 for one clock period, and
Clock cl from 10, read/write signal R/Wl
, clock c2+ ift output from DMAC20/
It is switched to the write signal R/W2 and output to the timing generation circuit 2.

The timing generation circuit 2 uses the access clock C2 output from the clock system switching circuit 1 and the read/write signal R/W2.
is input, an access signal t synchronized with the clock c1 of the CPU 10 is generated for one clock before and after the activation of the DMAC 20 and output to the shared memory 30.

The memory access control circuit of the present invention converts the access signal t output from the timing generation circuit 2 from the access signal t1 of 10 CPU systems to the access signal t of 20 DMAC systems.
Since switching to 2 is stopped in synchronization with the CPU IO clock c1 for at least one clock before and after the DMAC 20 is activated, the read/write operation of the shared memory 30 is guaranteed and the problem is solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a memory access control circuit according to an embodiment of the present invention, FIG. 3 is a memory access time chart for explaining its operation, and FIG. 4 is a clock system thereof. It is a time chart of switching operation.

In the block diagram of FIG. 2, the CPU 10 is an IC M
B8861101 and MB8867102 and buffer 10
3, and the asynchronous DMAC20 is the HD68 IC.
It consists of a B44201 and a clock oscillator 202.

Address AI5 of MB8861101 of CPU 10
AO and data Do-D7 are sent to the MB886120 of the DMAC 20 via the buffer 103 driven by the control signal VMA output by the clock c1 of the CPU 10.
1 addresses AI5 to AO and data Do to D7.

The clock system switching circuit 1 includes a flip-flop 11° selector 12. The flip-flop 11 is composed of an AND gate 13, and when the DMAC 20 is activated, the control signal DRQT is output from the MB8861201 using the clock c2 of the DMAC 20, and the control signal MCL is output from the MB8867102 using the clock C1 from the CPU 10.
K and the output is input to R- of MB8867102.
Input to 12EQ. MB886710 with CPU 10
Is the request signal for switching to DMAC20 input to R-REQ of 2 the permission signal R/Gl? As NT [1MAC20
and is input as the permission signal D-GRNT of the liver 8861201 of the DPIAC 20.

The signal inputted as D-GRNT of MII 8861201 is delayed by one clock inside MB 8861201, output from TxSTB, and inputted to the S terminal of selector 12 as selection signal SEL.

The selector 12 selects the CPU 1 input to the input terminal IA based on the selection signal SEL input from TxSTB to the S terminal.
The signal MCLK of the M88867102 corresponding to the clock c1 of 0 and the signal Φ2D of the MB8861201 corresponding to the clock c2 of the DMAC20 input to the input terminal IB.
The CPU 1 selects MA and outputs the signal Φ2DMA from the output terminal IY of the selector 12 to the timing generator 3 as the access clock c2, and also inputs it to the input terminal 2A.
The read/write signal R/Wl of 0 and the read/write signal R/W2 of the DMAC 20 input to the input terminal 2B are selected, and the read/write signal R/W2 of the DMAC 20 is accessed from the output terminal 2Y of the selector 12. Read/
It is output to the timing generator 3 as a write signal. AND gate 13 is MB8861101 (
7) VBA output inversion (i and Mn of DMMC20
The TxSTB output of the 8861201 is subjected to AND processing and inputted to the enable/disable terminal G of the selector 12.

The timing generation circuit 3 receives the access clock C2 from the selector 12 and the access read/write signal R/W2.
That is, in the time chart of FIG. 3, the access clock and the access signal W are input, and as the access signal t that provides the timing of access to the memory 30, the RAS and CAS that define the vertical and horizontal addresses, and the read/write ■WE that specifies writing is generated and output to the memory 30.

The memory 30 is composed of a dynamic RAM 301 and an address decoder 302.
1 is Mn8861101 of CPU 10 and DMAC
20 Mn8861201 output bus address code■
ADRESS is decoded by the address decoder 302 and inputted to the dynamic RAM 301 as a chip select signal ■C3.

The dynamic RAM 301 of the memory 30 specifies the column data position in the horizontal direction of the memory using the chip select signal C8 and the address signal t from the timing generation circuit 3 using the RAS, and specifies the row data position in the vertical direction of the memory using the CAS. Define the location of data. And ■Data by WE■
Write/output DATA to the above defined address location.

FIG. 3 shows the timing of access to the memory 30 by the DMAC 20 described above, and shows how one cycle of writing/reading to the memory 30 ends in synchronization with the access clock of the output of the timing generation circuit 2. ing.

FIG. 4 is a time chart 1 showing details of the switching timing of the clock systems of the CPU 10 and DMAC 20 in FIG. 2. In the block diagram of FIG.
When the DMAC 20 attempts to access the memory 30 that is being used by the DM 8, the DROT of the DM system 20 is output to the flip-flop 11, and the
The falling and rising edges of CLK are transmitted from the flip-flop 11 to the CPU system 10 as a request signal R-REQ.

At the next falling edge of ■MCLK of the CPU system 10, the permission signal ■R-GRNT output is sent directly to ■D of the DMAC system 20.
-GI? At the same time as the data is input to the NT, the CPU system 10 stops its write/read operations as shown in ■R/H.
At that moment, the selector 12 of the clock switching circuit 1 is disabled by the output @lG of the AND gate 13.

Then, the DMAC system 20 acquires the address and data bus to the memory 30, and also transmits TxS according to its own timing.
It outputs TB to the selector 12 as a selection signal SEL and enters memory access. At that time, the selector 12 is also enabled by the AND gate 13, and the logic level of the input S [phase] is H, so the D of the B port, that is, the input IB
Clock c2 of MAC system 20 and R/W signal R of input 2B
/W2 is the output terminal I of the selector 12 as an access signal.
Dynamic RAM 301 of memory 30 from Y, 2Y
Output to.

The DJ'lAC system 20 performs access according to the 20th time chart, but after the access is completed, the output ■DR
Disable QT and start up. Then, due to the falling and rising edges of MCLK of the CPU system 10, the R-REQ becomes invalid and rises. ■By the next falling edge of MCLK, ■V
As shown at the right end of the MA, the CPU system 10 again has the right to access the memory.

The relationship between the input and output of the selector 12 in FIG. 4 is such that even when the input is from the asynchronous DMAC system 20, the output is output without any loss of memory access timing as shown in FIG. Therefore, it appears that the upper CPU
There is no problem in synchronizing with the clock of 10.

〔Effect of the invention〕

As explained above, according to the present invention, the CPU and the asynchronous DMAC can be apparently synchronized when accessing the memory or input/output device common to both, and can be configured with a small number of circuits. This provides the effect of allowing operation with sufficient margin.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of the memory access control circuit of the present invention, FIG. 2 is a principle time chart for explaining the operation of the memory access control circuit of the present invention, and FIG. 3 is a principle diagram showing the structure of the memory access control circuit of the present invention. FIG. 4 and FIG. 5 are time charts for explaining the operation of the embodiment of the present invention. FIG. 6 is a block diagram of a conventional memory access control circuit. In the figure, 1 is a clock system switching circuit, 11 is a flip-flop, 12 is a selector, 13 is an AND gate, 2 is a timing generation circuit, 10 is a CPU, 20 is a DMAC, and 30 is a memory. eO■O○○OO

Claims (1)

[Scope of Claims] A memory access control circuit in which a direct memory access controller DMAC (20) that operates asynchronously with a processor CPU (10) accesses a memory (30) shared with the CPU (10) to read and write data. When the DMAC (20) is activated, the clock (c2) of the DMAC (20) is controlled by the clock (c1) of the CPU (10), and the clock (c2) of the DMAC (20) is stopped for one clock period. It generates a control signal (SEL) to output the clock (c1) and read/write signal (R/W1) from the CPU (10), and outputs the clock (c2) and read/write signal (R/W2) from the DMAC (20). ) and outputs the access clock (c2, R/W2), and inputs the access clock (c2, R/W2) output from the clock system switching circuit (1) and outputs the access clock (c2, R/W2). It includes a timing generation circuit (2) that generates an access signal (t) that provides timing for accessing the memory (30), and the access signal (t) output from the timing generation circuit (2) is generated when the CP
From the U (10) system signal (t1) to the DMAC (20)
When switching to the system signal (t2), at least the DMA
During the one clock period before and after the activation of C(20), the CP
A memory access control circuit characterized in that it stops in synchronization with a clock (c1) of U(10).