JPH01162422A - Analog/digital converter - Google Patents
Analog/digital converterInfo
- Publication number
- JPH01162422A JPH01162422A JP32182887A JP32182887A JPH01162422A JP H01162422 A JPH01162422 A JP H01162422A JP 32182887 A JP32182887 A JP 32182887A JP 32182887 A JP32182887 A JP 32182887A JP H01162422 A JPH01162422 A JP H01162422A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistor
- voltage
- analog
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 241001342562 Mimon Species 0.000 description 1
- 101001031591 Mus musculus Heart- and neural crest derivatives-expressed protein 2 Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002574 poison Substances 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
アナログ/デジタル変換器に係り、特に全並列型アナロ
グ/デジタル変換器に関し。[Detailed Description of the Invention] [Summary] The present invention relates to an analog/digital converter, and particularly to a fully parallel analog/digital converter.
変換精度の向上を目的とし。The purpose is to improve conversion accuracy.
第1の抵抗(R1)乃至第nの抵抗(Rn(n−62)
)を有し、基準電圧を抵抗で分割する全並列型アナログ
/デジタル変換器であって、該第1の抵抗(R1)は第
1基準抵抗(1)により構成され、該第2乃至第nの抵
抗(Rz〜Rn (n=62))は該第1基準抵抗(1
)にコンパレータ入力電流による電圧誤差分を補償する
補償抵抗部(2)を付加したものにより構成され、該第
1の抵抗から第nの抵抗に向かって漸次抵抗値が減少し
ていることを特徴とするアナログ/デジタル変換器をも
って構成とする。The first resistor (R1) to the nth resistor (Rn(n-62)
), and divides a reference voltage by a resistor, the first resistor (R1) is constituted by a first reference resistor (1), and the second to nth The resistance (Rz~Rn (n=62)) is the first reference resistance (1
) with a compensation resistor section (2) that compensates for the voltage error caused by the comparator input current, and is characterized in that the resistance value gradually decreases from the first resistor to the nth resistor. It consists of an analog/digital converter.
本発明はアナログ/デジタル変換器(以下A/D変換器
と云う)に係り、特に全並列型A/D変換器に関する。The present invention relates to an analog/digital converter (hereinafter referred to as an A/D converter), and particularly to a fully parallel type A/D converter.
かかる変換器において変換精度の向上が要求されている
。There is a demand for improved conversion accuracy in such converters.
従来の全並列型A/D変換器の変換方式では。 In the conventional fully parallel A/D converter conversion method.
例えばアナログ信号を6ビツトのデジタル信号に変換す
る場合、基準電圧をへ1配線で作った基準抵抗で62分
割し、それぞれの電位とアナログ電圧とを63個のコン
パレータで一気に比較するという方式がとられている。For example, when converting an analog signal to a 6-bit digital signal, a common method is to divide the reference voltage into 62 parts using a reference resistor made with one wire, and compare each potential with the analog voltage at once using 63 comparators. It is being
この場合基準抵抗で分割された電圧が均等でないと変換
精度が低下する。In this case, if the voltages divided by the reference resistors are not equal, conversion accuracy will decrease.
基準抵抗で分割された電圧は、基準抵抗と基準抵抗を流
れる電流で決定されるが2個々の基準抵抗に流れる電流
はコンパレータの入力電流分の誤差を生しる。The voltage divided by the reference resistor is determined by the reference resistor and the current flowing through the reference resistor, but the current flowing through the two individual reference resistors causes an error equal to the input current of the comparator.
第3図にA/D変換器の従来例を示す。FIG. 3 shows a conventional example of an A/D converter.
R,l (n=1.2.’−・・、62)は基準抵抗で
すべて等しい。この値をRoとする。図中、記号は下記
の意味を有する。R, l (n=1.2.'-..., 62) are reference resistances and are all equal. Let this value be Ro. In the figure, symbols have the following meanings.
IC=コンパレータ入力電流
Ir:Vrbに流れ込む電流
Vrt:変換を行う上限電位
Vrb:変換を行う下限電位
Vin:A/D変換されるアナログ入力電圧n番目の基
準抵抗で分割される電圧をVn(n=1.2. ・・
・、62)とすると。IC = Comparator input current Ir: Current flowing into Vrb Vrt: Upper limit potential for conversion Vrb: Lower limit potential for conversion Vin: Analog input voltage to be A/D converted The voltage divided by the nth reference resistor is Vn(n =1.2.
, 62).
Vl =R111=Ro (Ir+I c )V2
=R2I2 =Ro (Ir+21 c )= V
1+−1’jo乙j−c、−
Vr+(n=61>
−Rn (n=61) x I n (n=61)−R
o (Ir+611 c )
−V、十玉副−Tj9−Q−I−+q、−Vn (n−
62)
−Rn (n=62) x I n (n=[i 2)
=Ro (Ir+62I c )
−Vl 十−旦一シ−R8o−−−3−L−(−となる
。Vlを基準とすると分割された電圧には下線で示した
ような誤差が生じる。Vl = R111 = Ro (Ir+I c )V2
=R2I2 =Ro(Ir+21c)=V
1+-1'jo otsuj-c, -Vr+(n=61>-Rn (n=61) x I n (n=61)-R
o (Ir+611 c) -V, ten ball sub-Tj9-Q-I-+q, -Vn (n-
62) −Rn (n=62) x I n (n=[i 2)
=Ro (Ir+62I c ) -Vl 10-Danichi-R8o--3-L-(-. If Vl is used as a reference, the divided voltage will have an error as shown by the underline.
本発明はこのコンパレータ入力電流による電圧誤差分を
補信し1分割された電圧を均等にし、変換精度を向上さ
せたA/D変換器を提供することを目的とする。An object of the present invention is to provide an A/D converter that compensates for voltage errors caused by this comparator input current, equalizes the divided voltages, and improves conversion accuracy.
第1の抵抗(R1)乃至第nの抵抗(Ro (n=62
))を有し、基準電圧を抵抗で分割する全並列型アナロ
グ/デジタル変換器であって、該第1の抵抗(R+)は
第1基準抵抗(1)により構成され、該第2乃至第nの
抵抗(Rz〜Rn(n=62))は該第1基準抵抗(1
)にコンパレータ入力電流による電圧誤差分を補償する
補償抵抗部(2)を付加したものにより構成され、該第
1の抵抗から第nの抵抗に向かって漸次抵抗値が減少し
ていることを特徴とするアナログ/デジタル変換器によ
り、上記問題点は解決される。The first resistor (R1) to the nth resistor (Ro (n=62
)) and divides a reference voltage by a resistor, the first resistor (R+) being constituted by a first reference resistor (1), and the second to The resistance n (Rz to Rn (n=62)) is the first reference resistance (1
) with a compensation resistor section (2) that compensates for the voltage error caused by the comparator input current, and is characterized in that the resistance value gradually decreases from the first resistor to the nth resistor. The above problem is solved by the analog/digital converter.
本発明の第1の方法では第3図のR1で分割された電圧
V1を基準にする。In the first method of the present invention, the voltage V1 divided by R1 in FIG. 3 is used as a reference.
Vl =Ro XI H=Ro (Tr +Ic )
■2を■1と等しくするためには。Vl = Ro XI H = Ro (Tr + Ic)
■To make 2 equal to ■1.
V2 =R2X (Ir +2 Ic )であるから、
V、=V2とすると
Rz =Ro x
(Ir +Ic ) / (Ir +21c )=Ro
X
(j Ic/ <Ir +21c))R3=Ro x
(Ir + Ic ) / (Ir +31c )=R
oX
(1−21c / (Ir +31c ) )Rn
(n=61) −Ro x
(Ir 十Ic ) / (Lr +61 re )=
RoX
(1−60Ic/ (Ir +611c))Rn C
rに62) =Ro x
(Ir +Ic)/ (Ir +62Ic)=RoX
(1611c/(Tr+621c))
故に。Since V2 = R2X (Ir +2 Ic),
V, = V2, then Rz = Ro x (Ir + Ic) / (Ir + 21c) = Ro
X (j Ic/ <Ir + 21c)) R3 = Ro x (Ir + Ic) / (Ir + 31c) = R
oX (1-21c/(Ir+31c))Rn
(n=61) - Ro x (Ir + Ic) / (Lr +61 re) =
RoX (1-60Ic/ (Ir +611c))Rn C
62) = Ro x (Ir + Ic) / (Ir + 62 Ic) = RoX (1611c/(Tr + 621c)) Therefore.
Rn=ROX (1(n−1)Ic/(Ir+n1c))となり。Rn=ROX (1(n-1)Ic/(Ir+n1c)).
(n−1) Ic / (Ir +n Ic )は補
償すべき抵抗分となる。(n-1) Ic/(Ir+n Ic) is the resistance to be compensated.
従って、補償抵抗部を個々の基準抵抗に加えることによ
って9分割される電圧を均等にし、変換精度を向上させ
ることができる。Therefore, by adding a compensation resistor to each reference resistor, it is possible to equalize the voltage divided into nine parts and improve conversion accuracy.
本発明の第2の方法では第3図のR1(n=62)で分
割された電圧Vn (n=62)を基準にする。In the second method of the present invention, the voltage Vn (n=62) divided by R1 (n=62) in FIG. 3 is used as a reference.
ごの場合も第1の方法と同様の計算により1分割される
各部において補償すべき抵抗分を求めることができる。In this case as well, the resistance to be compensated for in each divided portion can be determined by calculation similar to the first method.
この場合は補償すべき抵抗分の符号が第1の場合の符号
と逆になる。In this case, the sign of the resistance to be compensated is opposite to that in the first case.
従って、この場合は抵抗値の補正のために補正抵抗部を
基準抵抗から除去することによって9分割される電圧を
均等にし、変換精度を向上させることができる。Therefore, in this case, by removing the correction resistance section from the reference resistance for correcting the resistance value, it is possible to equalize the voltage divided into nine and improve the conversion accuracy.
以下添付図により本発明の実施例について説明する。6
ビントA/D変換器の基準抵抗に補償または補正を加え
た場合の例を示す。Embodiments of the present invention will be described below with reference to the accompanying drawings. 6
An example will be shown in which compensation or correction is applied to the reference resistance of the Vint A/D converter.
実施例■では第1図の平面パターンに示す通り幅W1.
長さ11の第1基準抵抗1をAI膜で形成する。この第
1基準抵抗の値を第1の抵抗R1(−Ro)とする。第
2の抵抗R2は前記基準抵抗R1に並列状に微小体積の
補償抵抗部2を付加し。In Example 2, the width W1.
A first reference resistor 1 having a length of 11 is formed of an AI film. The value of this first reference resistance is defined as a first resistance R1 (-Ro). The second resistor R2 includes a compensating resistor 2 with a small volume added in parallel to the reference resistor R1.
Ro X Ic / (Ir +2 Ic )だしJ抵
抗値を下げる。Ro X Ic / (Ir +2 Ic) and lowers the J resistance value.
以下同様にしてRn (n=62)の場合はRo x(
i 11c / (Ir +621c )たけ抵抗値を
下げる。Similarly, in the case of Rn (n=62), Ro x (
Lower the resistance value by i 11c / (Ir +621c).
実施例■では第2図の平面パターンに示す通り幅W2.
長さ”21の第2基準抵抗3をA1膜で形成する。この
基準抵抗の値はR1(n−62)である。R,、(n=
61)は前記第2基準抵抗3がら補正抵抗部4を除去し
。In Example 2, the width W2.
A second reference resistor 3 with a length of "21" is formed of an A1 film.The value of this reference resistor is R1 (n-62).R,, (n=
61) removes the correction resistor section 4 from the second reference resistor 3;
Ro X Ic / (Ir +2 Ic )だ番ノ抵
抗値を上げる。Increase the resistance value by RoXIc/(Ir+2Ic).
n−61以下同様にして、順次除去すべき補正抵抗部4
の体積を増して行く。Correcting resistor section 4 to be sequentially removed in the same manner from n-61 onwards.
increase the volume of
即ち、実施例■でも別の見方をすれば第1の抵抗R1に
補償抵抗部2を漸次付加していることになり、実施例I
と基本的には同等である。In other words, if you look at it in another way, the compensation resistance section 2 is gradually added to the first resistor R1 even in the embodiment (I).
is basically equivalent.
補償抵抗部2の付加はAIの真空蒸着法、補正抵抗部4
の除去はレーザによるl−リミング法等を用いて行うこ
とができる。The compensation resistor part 2 is added using the AI vacuum evaporation method, and the compensation resistor part 4
The removal can be performed using an L-rimming method using a laser or the like.
以上説明した様に1本発明によれば、変換精度の高いA
/D変換器を提供することができる。As explained above, according to the present invention, A with high conversion accuracy
/D converter can be provided.
第1図は実施例I。 第2図は実施例■。 第3図はA/D変換器の従来例 である。 図において。 lは第1基準抵抗。 2は補償抵抗部。 3は第2基準抵抗。 4は補正抵抗部 R1(=茅隊ギ林−I’O) (α) F’?:z=[’?0(1−闇■) (b、) R62=ビ。(1−≠毒、) (C) iミ蒙F毬也イタ’3 工 竿 1 口 F’<b2(=事2基準抵軌) (a) T?:乙I C’o) 実施4ダ1」■ 千 2 口 FIG. 1 shows Example I. Figure 2 is an example ■. Figure 3 shows a conventional example of an A/D converter. It is. In the figure. l is the first reference resistance. 2 is a compensation resistance section. 3 is the second reference resistance. 4 is the correction resistance section R1 (=Kayatai Girin-I’O) (α) F’? :z=['? 0 (1-dark■) (b,) R62 = Bi. (1-≠ poison,) (C) i Mimon F Mariya Ita’3 Engineering Rod 1 mouth F’<b2 (=Thing 2 standard resistance gauge) (a) T? :Otsu I C’o) Implementation 4 da 1” ■ thousand and two mouths
Claims (1)
2))を有し、基準電圧を抵抗で分割する全並列型アナ
ログ/デジタル変換器であって、該第1の抵抗(R_1
)は第1基準抵抗(1)により構成され、該第2乃至第
nの抵抗(R_z〜R_n(n=62))は該第1基準
抵抗(1)にコンパレータ入力電流による電圧誤差分を
補償する補償抵抗部(2)を付加したものにより構成さ
れ、該第1の抵抗から第nの抵抗に向かって漸次抵抗値
が減少していることを特徴とするアナログ/デジタル変
換器。The first resistor (R_1) to the nth resistor (R_n (n=6
2)) and divides a reference voltage by a resistor, the first resistor (R_1
) is composed of a first reference resistor (1), and the second to nth resistors (R_z to R_n (n=62)) compensate the voltage error due to the comparator input current to the first reference resistor (1). An analog/digital converter comprising a compensating resistor (2) added thereto, the resistance value of which gradually decreases from the first resistor to the n-th resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32182887A JPH01162422A (en) | 1987-12-18 | 1987-12-18 | Analog/digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32182887A JPH01162422A (en) | 1987-12-18 | 1987-12-18 | Analog/digital converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01162422A true JPH01162422A (en) | 1989-06-26 |
Family
ID=18136874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32182887A Pending JPH01162422A (en) | 1987-12-18 | 1987-12-18 | Analog/digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01162422A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5744331A (en) * | 1980-08-29 | 1982-03-12 | Toshiba Corp | A/d converter |
JPS60189329A (en) * | 1984-02-15 | 1985-09-26 | シーメンス、アクチエンゲゼルシヤフト | Analog/digital converter |
-
1987
- 1987-12-18 JP JP32182887A patent/JPH01162422A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5744331A (en) * | 1980-08-29 | 1982-03-12 | Toshiba Corp | A/d converter |
JPS60189329A (en) * | 1984-02-15 | 1985-09-26 | シーメンス、アクチエンゲゼルシヤフト | Analog/digital converter |
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