JPH01161916A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To always attain high speed output by setting a circuit current characteristic of each current control circuit inversely corresponding to the power voltage dependancy and the temperature dependancy of the driving capability of a P and N-channel MOS transistor(TR). CONSTITUTION:The current with an output P-channel MOS TR Q1 turned on is controlled bi the current of a 1st current control circuit 1 when an output of a 1st logic circuit controlling the gate potential of the said TR changes to a ground potential. Similarly, the current with an output N-channel MOS TR Q2 turned on is controlled by the current of a 2nd current control circuit 2 when an output of a 2nd logic circuit controlling the gate potential of the N-channel TR changes to a power potential. Thus, it is possible to allow the current control circuits 1, 2 to control so that the power voltage dependancy and the temperature dependancy of the output MOS TRs are cancelled. Then the output waveform is immune to the change in the power voltage and temperature and output noise suppression and high speed output are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a MOS type (insulated gate type) semiconductor integrated circuit, and particularly to an output circuit.

(Prior Art) A conventional output circuit of this type is shown in FIG. Here, QIIQ2 is a P channel for output, an N channel MO
The S transistor INI is an inverter that controls the gate voltage PDR 1 k of the P channel transistor Q, and is composed of a P channel transistor Q3 and an N channel transistor Q4.

1N2 is an inverter that controls the gate voltage NDR1 of the N-channel transistor Q2, and is composed of a P-channel transistor Q5 and an N-channel transistor R6.

In the above output circuit, when outputting a high level 1H'' as the output voltage OUT, the input signal PDR is input from the output control circuit in the previous stage to the inverters INI and IN2.

NIlyR is at low level ""L"→""H'"H
' level, and accordingly the y-t voltage PDR J, N
DR1 changes from "H' to "L", and the output transistors Ql and Q2 respectively turn on and off.

In this state, no through current flows between the vDD power supply terminal and the va8 power supply terminal (ground terminal).

Contrary to the above, when the output voltage OUT is at the "L" level, the input signals PDR and NDR change from L# to '
"Changes to H#, gate voltage PDR 1, NDR
1 changes from @L# to @H#, and the output transistor Ql
．． Q2 is turned off and on correspondingly, and no through current flows. The operating waveforms of the gate voltage NDR J and output voltage OUT C) at this time are shown in Figure 12 for the case of VDD = 5.5 V and the case of DD = 4.5 V. Compare these two waveforms. Then, vDD'I!
The higher the voltage, the greater the driving ability of the P-Ternel transistor Q5, so the rise of the gate voltage NDR1 is faster, and the waveform of the output voltage OUT becomes steeper. However, if the output waveform becomes too steep, voltage fluctuations will occur due to the inductance components of the power and ground lines between the output transistor and the power and ground terminals, causing voltage fluctuations in the power and ground lines inside the integrated circuit chip. Noise (output noise) is generated, causing malfunction of the chip's internal circuits. To avoid this, the v
If the output waveform is changed slowly enough so that the noise does not occur when the zero voltage is high (for example, 5.5 V), the output waveform will change when the vDD power supply voltage is low (for example, 4.5 V). The change in output becomes even more gradual, resulting in a larger output delay. By the way, V...
= 4. In the case of 5 V, the output delay (time t1 from the rising time of the output waveform to the time when the predetermined voltage reaches 0.8 V), and the output delay (t) in the case of VDD = 5.5 V.

~Lx). However, since the operating speed of a semiconductor integrated circuit is limited by the low value of the vDD voltage, the output delay (to-tx) when the vDD voltage is low becomes a problem when increasing the speed of the semiconductor integrated circuit.

On the other hand, conventional output circuits have the following problems with respect to temperature changes. That is, FIG. 13 shows the gate voltage NDR when the output voltage OUT changes from @H1 to @L''K.
1. The operating waveform of the output voltage OUT is set to the operating temperature Ta=0.
℃ and Ta=85°C.

Comparing these two waveforms, T. When the temperature is low (for example, 0° C.), the driving ability of the MOS transistor is large, so the change in the output waveform becomes steep. If T1 is high (
For example, at 85° C.), the driving ability of the MOS transistor is small, so the change in the output waveform becomes gradual. T,=
The output delay (to=Ls) at 85°C is T. = approximately 1.5 times the output delay (t(+-t4)) at θ°C. Therefore, when T is low, the change in the output waveform is made gradual to prevent malfunction of the chip's internal circuitry due to output noise. However, if T1 is high, the output delay becomes large, which is a problem in semiconductor integrated circuits that require high-speed operation.

(Problems to be Solved by the Invention) As described above, the drive capability of the MOS transistor has power supply voltage dependence and temperature dependence, which makes it difficult to optimize the output waveform when designing for high speed. The present invention has been developed to solve the problem that the above-mentioned power supply voltage dependence and temperature dependence are small, and it is an object of the present invention to provide a semiconductor integrated circuit that is capable of suppressing output noise and high-speed output.

[Structure of the Invention (Means for Solving Problems) The semiconductor integrated circuit of the present invention includes an output P-channel MOS transistor and an N-channel MOS connected in series between a power supply node and a ground node. and a first logic circuit that controls the gate potential of the P channel MO8), a first current control circuit that controls the current flowing to the ground potential side of the first logic circuit, and the N
The P-channel MO8) includes a second logic circuit that controls the gate potential of the channel MOS transistor, and a second current control circuit that controls the current flowing to the power supply potential side of the second logic circuit. N channel MO
S) The control current characteristic of the optical control circuit is set for each of the above so as to correspond inversely to the power supply voltage dependence and temperature dependence of the driving capacity of the nostar.

(Function) The current when the output P-channel MOS transistor is turned on is the current of the first undercurrent control circuit when the output of the first logic circuit that controls the gate potential of this transistor changes from ground to ground. Controlled by the first stream. Similarly, the current when the output N-channel transistor is turned on is controlled by the current of the second current control circuit when the output of the second logic circuit that controls the gate potential of this transistor changes to the power supply potential. be done. Therefore, it becomes possible to perform control by the current control circuit so as to cancel out the power supply voltage dependence and temperature dependence of the output MOS transistor.
The output waveform hardly changes due to power supply voltage and temperature, making it possible to suppress output noise and achieve high-speed output.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows the output circuit of the MO8d semiconductor integrated circuit, where Ql and Q2 are an output P-channel MOS transistor and an N-channel MOS transistor connected in series between the vDD power supply node and the ground node. . INI is an inverter that controls the gate voltage PDR1 of the output P-channel transistor Q4, and is used to control the gate voltage PDR1 of the output P-channel transistor Q4.
are connected in series, and each gate is commonly connected. The source of this P-channel transistor 3 is connected to the vDD' source node, and the source of this P-channel transistor 4 is connected to the vDD' source node.
A first current control circuit 1 is inserted between the source and the ground node. INJ is an inverter that controls the gate voltage NDR1 of the output N-channel transistor Q2, and a P-channel trannostar Q5 and an N-channel trannostar Q6 are connected in series, and their gates are commonly connected. The source of this N-channel trannoster Q6 is connected to the ground node, and the second current control circuit 2 is inserted between the source of the P-channel trannoster Q5 and the vDD power supply node.

The second current control circuit 2 is configured as shown in FIG. 2, for example. In other words, the source of the N-Tenyanel transistor Q13 to which the vDD voltage is applied to ff-) and one end of the resistive element R11 are commonly connected and grounded via the N-Tanyanel transistor Q14 for current limiting. . A P-channel transistor QJJ, whose gate and drain are connected to each other for loading, is inserted between the drain of the transistor Q13 and the source node of vDD'.

A current mirror is connected to this transistor Q7J.
A channel controller/nostar Q12 is inserted between the other end of the resistor wire R11 and the vDD power supply node. The connection point between this resistance element RJJ and the transistor Q12 is a P-channel transistor Q15 for current control (this is inserted in series with the impurator IN2).
connected to the gate. Note that the gate potential V of the current limiting transistor Q14. , for example v0
voltage is applied.

On the other hand, the first current control circuit 1 is configured, for example, as shown in FIG. 3, and is formed symmetrically with the above-mentioned first current control circuit. That is, the source of the P-channel transistor Q22 whose gate is grounded and the resistance element R
21 are connected in common, and also connected to the vDD power supply node via a current limiting P-channel transistor Q21. Between the drain of the transistor Q22 and the ground node is inserted an N-channel transistor Q23 whose e-) and drains are connected to each other for a load, and an N-channel transistor Q24 which is current mirror-connected to this transistor Q23. is the resistance element R2
1 and the ground node. The connection point between this resistance element R21 and the transistor Q24 is f-) of an N-channel transistor Q25 for current control (which is inserted in series with the inverter INZ).
It is connected to the. Note that, for example, a ground potential is applied as the gate potential vG2 of the current limiting transistor Q21.

Note that the resistance element RJJ of the second current control circuit 2 is
For example, it is formed of polysilicon or the like containing a high concentration of impurities, and its resistance value has almost no temperature dependence. The gate of the N-channel transistor Q13, which forms the differential amplifier Dkl together with the resistance element all, is set to the vDD power supply voltage. Therefore, this transistor Q1
The equivalent resistance of 3 becomes smaller as the power supply voltage becomes higher.

As a result, the potential Vll of the output node Nil of the differential amplifier DAJ increases as the power supply voltage increases, and the gate potential of the current control transistor QJ5 increases, so that the control current flowing through the transistor Q15 becomes smaller. Therefore, the control current corresponds inversely to the power supply voltage dependency of the driving force of the MOS (MOS) lannostar.

Note that as the temperature increases, the equivalent resistance of the N-channel transistor QlB for differential amplification increases. As a result, as the temperature increases by 1 m, the output potential Vll of the differential amplifier DAJ becomes lower and the control current becomes larger. As a result, the control wL characteristic corresponds inversely to the temperature dependence of the driving capability of the MOS transistor.

On the other hand, also in the first current control circuit 1, the second
The current control circuit 2 operates in accordance with the current control circuit 2, and its control current corresponds inversely to the vDD voltage dependence and temperature dependence of the drive capability of the MOS (MOS) Lanno-Suter. In the first current control circuit 1 shown in FIG. 3, DA2 is a differential amplifier, and its output is represented by V21.

That is, v of the control current in each of the above current control circuits 1.2
The dependence of DD'flL on the source heart pressure is as shown in Fig. 4, for example, and the v
This cancels out the DD voltage dependence. That is.

MOS) Runnostar driving capacity is VDD==5.5
When V, vDD = 5.0, about 1 compared to when V
Increased by 5.

V = 4.5V (1cVDD = 5.0V in case of D (reduced by about 15% compared to case of D). On the other hand, the control current is vD,
= 5. If s vo, then vDD=s, o V
Approximately 15% decrease compared to O field, vI)D=-4,s
In the case of vo, vDD=5, which increases by about 15% compared to the case of Ov, so the vDD voltage dependence of the control current and the vDD voltage dependence of the drive ability cancel each other out.

Therefore, in the output circuit of FIG. 1, when the output P-channel transistor Q turns on, the output of the inverter INJ, which applies the gate potential PDRJ to the transistor Q, changes to the ground potential. Since the driving ability of the transistor Q1 is controlled by the control current of the first current control circuit 10, almost no vDD voltage dependence occurs. Similarly, when the output N-channel transistor Q2 is turned on, this transistor Q 2 Kf −)
[The output of inverter IN2 which provides NDRl is vD
The gain l1 of the second current control circuit 2 when changing to the D potential
Since the driving ability of the transistor Q2 is controlled by the g1 torque, there is almost no vDDIt pressure dependence.

Note that when the output P-channel transistor Q1 is turned off, it is turned off according to the driving ability of the P-channel transistor Q3, and the output N-channel transistor Q2 is turned off.
When turned off, it is turned off according to the driving ability of the N-channel transistor 6.

Here, for example, an N-channel transistor for the output,
fiQ 2 times; 4-7 years *, vDD = 5.
5V.

V,, = 4.5 V 12) If Kj? "Keb'r"
-)' The operating waveforms of NDRJ and output voltage OUT are shown in FIG. That is, the control current vDD=4.5V (7)
Since the voltage in the case of VDD=5.5V is larger than that in the case of VDD=5.5V, the gate potential NDR1 rises more quickly in the case of vDD=4.5V than in the case of 1tvDD=s,svokm. Therefore, vDD=4. In the case of sV, vDD=5. Compared to the case of sv, it is possible to compensate for the decrease in driving ability due to the smaller N-channel transistor Q2 (D source/drain/voltage).
Even if VDD= 4.5 V IZ), vDD−
It becomes possible to output at the same speed as S and SV.

Further, the temperature dependence of the control current in each of the above current control circuits 1.2 is as shown in FIG. 6, for example, and the MO
S) The temperature dependence of the driving ability of the lannostar is canceled out. That is, the drive capacity of the MOS (MOS) runnostar increases by about 50% when the temperature is 0°C compared to 85°C, but when the control current is 85°C it increases by about 50 qb compared to 0°C. If you set it like this,
Their temperature dependencies cancel each other out. As a result, when the N-channel transnoster Q2 for output in the output circuit of FIG. 1 is turned off, the operating waveforms of the gate potential NDRJ and output voltage OUT at temperatures of 0°C and 85°C are shown in FIG. It comes to show. That is, the control current is 85
Since the temperature at 85° C. is about 50 degrees higher than that at 0° C., the gate potential NDR1 rises much faster at 85° C. than at 0° C. 85 degrees Celsius
In this case, it is possible to compensate for the drop in the driving ability of MOS transistor Q2 to about 1/1.5 compared to the case at 0°C, and even at 85°C it is almost the same as at 0°C. It becomes possible to output at the same speed.

According to the output circuit of the above embodiment, there is almost no voltage dependence or temperature dependence, so the output waveform should be set so as to suppress the output noise when the driving force of the MOS) lannostar is large. For example, even when the driving force of the MOS transistor is small, an output waveform equivalent to that when the driving force is large can be obtained, so high-speed output with small output delay is possible.

Note that the resistance element RJJ of the current control circuit 2 is a MOS)
If it is formed using polysilicon wiring, etc. in the same layer as the Lansostar f-) electrode, if the gate is etched with many poles and the line width becomes narrower due to process variations, the resistance value will change. becomes higher, and the driving ability of the transistor becomes thicker. Therefore, the differential amplifier DA
The output potential v11 of J becomes high, and the control current becomes small.

On the other hand, if the gate electrode is etched less and the line width becomes thicker, its resistance value becomes lower, the driving ability of the MOS transistor becomes smaller, and the output of the differential amplifier DAJ becomes smaller. The potential Vll becomes low and is controlled? 1
The JJt style is multifaceted. A similar thing can be done with MOS
The same can be said about process variations in transistor threshold values. Further, the same thing as above can be said about the first current control circuit 1 as well. Therefore, since the control current responds inversely to variations in the driving force of the MOS transistor due to process variations, it is possible to obtain an output circuit with little variation in response to process variations.

Note that the current control circuits 1 and 20' are MOS transistors for current limiting.
Tranostar Q21. In place of Q14, a resistance element (for example, polysilicon) with low vDD voltage dependence and low temperature dependence may be used.

Further, the current control circuits 1 and 2 each have a current control transistor Q25.
Although the gate control of Q15 was performed, the second current control circuit 2
For example, as shown in FIG. 8, and as the first current control circuit 1.

For example, as shown in FIG. 9, differential amplifiers DAJ and DAZ are connected in two stages.

MOS transistor Q39 for ti control. Depending on the driving ability of the Q49, it becomes possible to perform even greater control over the tortoise flow.

Further, in the above embodiment, the first current control circuit 1f is inserted only on the ground potential side of the inverter INl0, and the inverter I
N.? Although the second current control circuit 2 is inserted only on the power supply potential side of the inverter IN, as shown in FIG.
A third current control circuit 3 (similar to the second current control circuit 2) is also inserted on the power supply potential side of the inverter I.
A fourth current control circuit 4 (the first
No. 1! A flow control circuit (similar to the flow control circuit 1) may be inserted.

In this way, the output P-channel transistor Q
It becomes possible to control the rise of the gate potential PDR1 when the gate is turned off by the third current control circuit 3,
It becomes possible for the fourth current control circuit 4 to control the fall of the r-) potential NDR1 when the output N-channel transistor RO2 is turned off.

Furthermore, the logic circuit for controlling the gate potential of the output transistor is not limited to the inverters INi and IN2.
The present invention can also be applied to cases where other logic circuits (NAND circuits, NOR circuits, etc.) are used.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, the output circuit has almost no power supply voltage dependence and temperature dependence, so it is possible to make the output delay constant, and the output Even if the output delay is determined to suppress noise, the output delay does not become large when the power supply voltage is low or the temperature is high, and high-speed output is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of the output circuit in the semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram showing one specific example of the second current control circuit in FIG. 1, and FIG. is a circuit diagram showing a specific example of the first current control circuit in FIG. 1, and FIG. 4 shows the control current and output M of the current control circuit in FIGS. 2 and 3.
A characteristic diagram showing the dependence of the drive current of the OS transistor on the vDD power supply voltage. Fig. 5 shows the voltage dependence of the output voltage on the gate when the output N-channel transistor in Fig. 1 is turned on, and the vDD voltage dependence of the output voltage. The characteristic diagram shown in Fig. 6 is Fig. 2,
Control current and output MO8) of the current control circuit in Figure 3
FIG. 7 is a characteristic diagram showing the temperature dependence of the transistor drive current and the gate voltage when the output N-channel transistor in FIG. 1 is turned on, and a characteristic diagram showing the temperature dependence of the output voltage. 9 and 9 are circuit diagrams showing modified examples of the current control circuits in FIGS. 2 and 3, respectively, FIG. 10 is a circuit jma diagram showing another embodiment of the present invention, and FIG. 11 is a conventional output FIG. 12 is a characteristic diagram showing the power supply voltage dependence of the output circuit of FIG. 11, and FIG. 13 is a characteristic diagram showing the temperature dependence of the output circuit of FIG. 11. Q + Q J... Output transistor, INJ, I
N2...Inverter, 1, 2, 3.4... Current control circuit, Q11 to Q15. Q21 to Q25...transistors. R11, R21...resistance element, DAJ, DA, ?・・・
・Differential amplifier. Applicant's agent Patent attorney Takehiko Suzue Vo. 2nd t! 1 7$J3 figure i source 1! And figure 4 foot figure 5 figure 6rl! J Figure 7 Figure 8 Figure 9 Vo. Figure 10 Figure 11 Figure 12 Figure 13

Claims (5)

[Claims] (1) An output P-channel MOS transistor and an N-channel MOS transistor connected in series between a power supply node and a ground node, a first logic circuit that controls the gate potential of the P-channel MOS transistor, and a first current control circuit that controls the current flowing to the ground potential side of the first logic circuit; a second logic circuit that controls the gate potential of the N-channel MOS transistor; and a power supply potential of the second logic circuit. The second one controls the current flowing to the side.
and a current control circuit, the control current characteristics of each of the current control circuits being set so as to correspond inversely to the power supply voltage dependence and temperature dependence of the drive capability of the P-channel MOS transistor and the N-channel MOS transistor. A semiconductor integrated circuit characterized by: (2) The second current control circuit inputs the output of a first differential amplifier having a differentially connected N-channel MOS transistor and a resistance element to the gate of a P-channel MOS transistor for current control. The first current control circuit is configured by inputting the output of a second differential amplifier having a differentially connected P-channel MOS transistor and a resistance element to the gate of an N-channel MOS transistor for current control. A semiconductor integrated circuit according to claim 1, characterized in that: (3) The first differential amplifier is connected in two stages, and the second
3. The semiconductor integrated circuit according to claim 2, wherein two stages of differential amplifiers are connected. (4) The semiconductor integrated circuit according to claim 2, wherein each of the resistive elements is made of the same material as the gate electrode of the MOS transistor. (5) a third current control circuit that controls the current flowing to the power supply potential side of the first logic circuit; and a fourth current control circuit that controls the current flowing to the ground potential side of the second logic circuit. further comprising, the third current control circuit is connected to the second current control circuit.
Claims 1 or 2, characterized in that the fourth current control circuit has the same configuration as the first current control circuit, and the fourth current control circuit has the same configuration as the first current control circuit.
4. The semiconductor integrated circuit according to item 4.