JPH01161476A - Memory access control system - Google Patents

Abstract

PURPOSE:To simultaneously make access to two apparent vector data and to improve a memory throughput by providing a means for alternately transmitting a request to the memory of the respective elements of two vector data when it is detected that two banks are not overlapped. CONSTITUTION:Corresponding to the access of the two vector data, a detecting means for detecting that the banks made access by the two vector data are not overlapped from the leading addresses B1, B2 of the respective vector data and distances D1, D2 between elements are provided, and the means for transmitting alternately the requests RQ1, RQ2 to the memory of the respective elements of the two vector data when the banks being not overlapped are detected is provided. Thereby, the two apparent vector data are simultaneously made access to improve the memory throughput.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control method in information processing, and particularly to a memory access control method for accessing vector data arranged at regular intervals on a memory.

(Prior Art) Conventionally, this type of memory access control method is disclosed in, for example, Japanese Patent Application No. 58-165955 r Memory Access Control Method.
As shown in , the cycle and number of memory requests were calculated from the distance between elements of vector data and the number of memory banks. Since it is not known which bank will be accessed when vector data is accessed, all banks are usually kept busy, and access to the next vector data cannot be started until the bank is no longer busy due to accessing the last element. Ta.

To solve this problem, when the distance between two vector data elements is the same, for example, they are arranged consecutively in memory, the last element of the vector data that was previously requested to the memory is A memory access control device has been proposed that calculates the timing to start accessing subsequent vector data from the bank address and the bank address of the first element of the subsequent vector data (for example, Japanese Patent Application No. 58-234486; 5
8-243323).

[The interlayer point that the invention attempts to solve]

In the above-mentioned conventional memory access control device, since two vector data are accessed consecutively in time, even if the time interval between sending requests for accessing the preceding vector data is wide, the following Accessing vector data cannot begin until the preceding vector data has been accessed, and this occurs even if, for example, the bank accessed by the preceding vector data is not accessed by the subsequent vector data.
The disadvantage is that the start of access is delayed.

(Means for Solving the Problems) The memory access control method of the present invention simultaneously processes first vector data in which the address of the first element is 81 and the inter-element interval is Dl;
Alternatively, when accessing second vector data whose first element is accessed with a time delay and whose address is 82 and the inter-element interval is Dl, Bl, B2 . DI, Dl to 1st
The bank in which each element of the vector data is arranged does not overlap the bank in which each element of the second vector data is arranged, and both the first and second vector data are stored in the storage means. a detection means for detecting that a bank conflict occurs in which requests are made for all elements in a temporally continuous manner; Priority control means for prioritizing sending of requests to the storage unit of vector data.

and a sending stage for sending a request to the storage means for second vector data even if access to the first vector data is not completed when a detection condition by the detection means is satisfied.

(Function) In response to accessing two vector data, the start address of each vector data is calculated from the distance between elements.
tV sinks accessed by two vector data are provided with a detection means for detecting that they do not overlap, and when it is detected that the banks are not overlapped, means for alternately sending requests to the memory of each element of the two vector data. By providing this, it is possible to seemingly access two vector data at the same time and improve memory throughput.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the memory access control system of the present invention, and FIG. 2 is a block diagram showing details of the memory access controller 3 of the embodiment of FIG. 1. /S3 is a block diagram showing details of the control circuit 37 of the memory access control device 3, and FIG. 4 is a timing chart showing the operation of the embodiment.

The arithmetic processing units 1.2 respectively send request signals RQ, , RQ2 via connection lines 11.21 to connection lines 12.22.
Address Bl, B of the first element of vector data via
2 (hereinafter referred to as base addresses Bl and B2) is connected to the inter-element pressure 1111 of the vector data via the connection line 13.23.
DI, D2 (hereinafter referred to as inter-element distance DI, D2) is output to the memory access control device 3. Based on these data, the memory access control device 3 connects the connection line 41.4.
2 respectively request (No. 3 RQ and address M
AD and is output to the memory 4 for access.

The memory access control device 3 sends request signals RQ+ and RQ7 from the connection lines 11 and 21 to the control circuit 37.
manually input the base addresses Bl and B2 from the connection lines 12 and 22 to the base address registers 31, , 31, respectively.
2, the inter-element pressures 1i11 from the connection lines 13 and 23, respectively.
D1. D2 respectively into the inter-element distance registers 32, , 3
22, it is inputted and held in synchronization with the human-powered request signals RQI and RQ2 from connection lines 11 and 21, respectively.

Memory address register 351 is controlled by control signal CL, and base address register 31. Either the output of the adder circuit 36I or the output of the adder circuit 36I is selected and held. Address register 35. is controlled by the control signal CL2 and outputs the output of the base address register 312 or the adder circuit 36.
．． Select and hold one of the outputs. adder circuit 3B,
is memory address register 35. and the output of the inter-element distance register 312 are added to update the request address for the memory 4. Addition circuit 362
adds the output of the memory address register 352 and the output of the inter-element distance register 322 in order to update the request address for the memory 4. The comparison circuit 33 includes base address registers 31, , 31 . compares the least significant bits of base addresses Bl and B2 that are held respectively, and outputs logic level 1 if base addresses Bl and B2 are odd and even numbers, and outputs logic level O if both are odd or even numbers. Output. The determination circuit 34 outputs a logic level 1 if the inter-element distances Di and D2 held by the inter-element distance registers 32+ and 322, respectively, are even numbers, and outputs a logic level 0 otherwise. The switching circuit 38 is controlled by the control signal CL3, and the memory address register: 15. , : selects one of the 152 outputs and outputs it as the address MAD. The control circuit 37 receives input request signals RQI and RQ2.
, the inter-element distances DI, D2, the output of the comparison circuit 33, and the judgment result of the judgment circuit 34, output the memory request RQ, and send the control signals CL, ct, 2 to the memory address register 35. , 352, and the control signal C
L3 is output to the switching circuit 38. The control circuit 37 also includes a timing generation circuit 37. , 372. AND circuit 3
73. OR circuit 376, flip-flop 374.37
．． , 378. AND circuit 373
ANDs the output of the comparison circuit 33 and the output of the determination circuit 34, and the result is held in the flip-flop 374. Timing generation circuit 37. , 37. are request signals RQ+, RQ2, and inter-element pressures 1i1D1. D2
This circuit generates a memory request RQ for the memory 4 from the memory 4. If neither is accessing memory 4, try Rikuku Quest RQ+ first.

The timing generation circuits 37□ and 372 that have received RQ 2 start operating in their own cycles. When request signals RQ+ and RQ2 are received at the same time, timing generation circuit 371 has priority, and timing generation circuit 372 is inhibited by request signal RQI. In this timing generation, the request cycle for the memory 4 can be obtained by decoding the inter-element distances DI and D2, as disclosed in Japanese Patent Application No. 58-165955, for example. If one side is accessing memory 4 and there is a request from the other side, the base address Bl,
The AND circuit 373 performs an AND operation between the comparison result by the B2 comparison circuit 33 and the determination result of the inter-element distance DI and D2 by the determination circuit 34, and under the condition that no bank conflict occurs, even if the other is accessing. Initiate access. Comparison circuit 37° receives request signals RQ+, R
Signal CL13. based on Q2. The CLI 4 is manually controlled by the timing generation circuits 37, 372, respectively, and if there is a possibility that the request timings match, the CLI 4 is controlled to delay the timing of the access that will be started later and shift the timing. The OR circuit 376 is the timing generating circuit 37. , 37. The request signal R output by
Take the OR of Q + and RQ 2. The flip-flop 377 inputs the output of the OR circuit 376 and outputs it to the memory 4 as a memory request RQ. The flip-flop 378 inputs the request signal RQ2 output from the timing generation circuit and outputs it as a control signal CL3.

Next, the operation of this embodiment will be explained with reference to FIG.

In this embodiment, the memory 4 has banks 0.1, .
~． 15, and the address is set to be incremented from bank 0 to bank 15.

Table 1 Vector data v from arithmetic processing unit 1 at timing TO
A request signal RQ + regarding 1 is output to the connection line 11. Also, at the same time as the request signal RQ+, the base address B1 and the inter-element distance D1 are connected to tt5AI.
2.13, and the base address registers 310. Inter-element distance register 32. is set to Here, if 81=O, DI=4, depending on the vector data v1, addresses 0, 4, 8,
Accessed in the order of addresses 122 and 166, 0 bank, 4
Bank, 8th bank, and 12th bank are accessed cyclically every 4 elements, so the request RQ for memory 4
is controlled by the control circuit 37 so that it is sent only once every four clock cycles. This control method is disclosed in Japanese Patent Application No. 58-1
65955, so the explanation will be omitted.

Until timing T1, the request signal RQ2 has not been output from the arithmetic processing unit 2, so the request (
No. A RQ + is output as memory requests R and Q at timing T2. Thereafter, vector data v1 is accessed to the memory by outputting a request signal RQs as a memory request RQ every four clock cycles, and at timing T6. TIO,...
・Accessed with Further, the address for access is set at timing T5. prior to the access timing. T9.・
... and updated at timing T6. In TIO, -..., memory address register 35. Data B1+ for each
DI, B1+2XD1. ... is held, and the switching circuit 3
8 to memory.

On the other hand, when a request signal RQ2 of vector data v2 with base address B2=1 and inter-element distance D2=2 is sent from the arithmetic processing unit 2 via the connection line 21 at timing T2, connection is made at the same timing T2. The base address B2 sent through the line 22 is taken into the base address register 312, and the element open chain @D2 sent through the connection line 23 is taken into the inter-element distance register 322.

The base address B2 taken into the base address register 312 is transferred to the memory address register 352 at the next timing T3. B2=1. Since D2=2, vector data ■2 will result in addresses 1, 3, 5, and 7.
Odd addresses are accessed in the order of addresses, . . . . Therefore, the odd banks are accessed cyclically every eight elements, and the memory 4 is controlled to be accessed only once, which is two clock cycles. B1=0. Since B2=1, the least significant bits of base address Bl and B2 are different, and the output of comparison circuit 33 is "1", and D1=4.
．． Since D2=2, element open chain IIDI.

Since D2 is an even number, the output of the determination circuit 34 is "1". The output of the AND circuit 373 obtained by ANDing the output of the comparison circuit 33 and the output of the determination circuit 34 becomes logic level 1, and is held in the flip-flop 374.

Since the output of flip-flop 374 is at logic level 1, timing circuit 37. , 372 is vector data V
1 and V2, it is detected that there is no conflict between the banks to be accessed. Additionally, the timing generation circuits 37, . 37,
are controlled to access the memory 4 at different timings by control signals CL, 5°CL, and 6 of the comparison circuit 375, respectively. Therefore, timing generation circuit 3
72 is timing T5°T7. T9. T11. Outputs memory request signal RQ2 to ~. This request signal RQ7 is connected to the OR circuit 376 and the flip-flop 37.
7 and is output as a memory request RQ.

Furthermore, the request signal RQ2 is applied to the flip-flop 37B.
The address MAD for accessing the memory 4 is output in synchronization with the memory request RQ based on the request signal RQ2. In other words, after the base address B2 of V2 is set in the memory address register 312 at timing T3, one clock cycle of request timing RQ2 for the second and subsequent elements, that is, timing T6. T8. ... and is updated at timing T7. T9. T11. ~ then memory address register 3
12 respectively B2+D2. B2+2xD2°... is held and sent to the memory 4 as the address MAD.

[Effects of the Invention] As explained below, in the present invention, in response to the access of two vector data, the banks that are accessed with the two vector data from the start address of the vector data and the distance between the elements are fixed. By providing a detection means for detecting that the banks do not overlap, and by providing means for alternately sending requests to the memories of the two vector data elements when it is detected that the banks do not overlap, the appearance of This has the effect of allowing vector data to be accessed simultaneously and improving memory throughput.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the memory access control method of the present invention, FIG. 2 is a block diagram showing details of the memory access control device 3 of the embodiment of FIG. 1, and FIG. 3 is a memory access control FIG. 4 is a block diagram showing details of the control circuit 37 of the device 3, and a timing chart showing the operation of the embodiment. 1.2-... Arithmetic processing unit, 3... Memory access jti (J
Control device, 4... Memory, 31, , 322... Base address register, 32, , 322-old... Inter-element distance register, 34
......... Judgment circuit, 34, , 352
...Memory address register, 36, , 36
2-・・・Addition circuit, 38・・・・・・・・・・・・
・Switching circuit.

Claims (1)

[Claims] 1. Memory access that controls access to vector data in which each element is arranged at regular intervals in a storage means that is composed of n banks that can be accessed independently of each other and is addressed in the order of bank numbers. In the control method, the first vector data whose first element address is B1 and the inter-element interval is D1, and the first vector data are simultaneously transmitted.
Or, when accessing second vector data whose head element address is B2 and the inter-element interval is D2, the first element is accessed with a time delay from B1, B2, D1, D2.
The bank in which each element of the vector data is arranged does not overlap the bank in which each element of the second vector data is arranged, and both the first and second vector data are stored in the storage means. detecting means for detecting that a bank conflict occurs in which all elements are requested sequentially in time; priority control means for prioritizing sending requests to the storage unit of data; and when a detection condition by the detection means is satisfied, even if access to the first vector data has not been completed, the storage of the second vector data is performed. A memory access control method comprising: sending means for sending a request to the means. 2. Comparing means for detecting that the difference between B1 and B2 is a divisor of n other than 1 or a multiple of n;
1 and D2 are both divisors or multiples of n other than 1, and inter-element interval decoding means detects that the same bank is accessed within the bank cycle time when all elements are accessed sequentially in time. A memory access control method according to claim 1.